Abstract: Embodiments of methods, apparatuses, devices, and/or systems for load balancing two processors, such as for graphics and/or video processing, for example, are described.

Abstract: A method for synchronizing two of more graphics processing units. The method includes the steps of determining whether the phase of a first timing signal of a first graphics processing unit and the phase of a second timing signal of a second graphics processing unit are synchronized, and adjusting the frequency of the first timing signal to the frequency of the second timing signal if the first timing signal and the second timing signal are not synchronized.

Abstract: The present invention provides a cost effective method to improve the performance of communication appliances by retargeting the graphics processing unit as a coprocessor to accelerate networking operations. A system and method is disclosed for using a coprocessor on a standard personal computer to accelerate packet processing operations common to network appliances. The appliances include but are not limited to routers, switches, load balancers and Unified Threat Management appliances. More specifically, the method uses common advanced graphics processor engines to accelerate the packet processing tasks.

Abstract: A portable game system includes two display screens, at least one of which is touch-sensitive. A memory card is selectively connectable to the portable game system.

Abstract: Dual processor accelerated graphics rendering is a method which allows for optimizing graphics performance using two processors and 3D hardware accelerators. This method allows for real time embedded systems to have multiple partitions to render to multiple windows with non-blocking graphics calls. One processor queues up graphics calls within a discrete time because they do not interface with the graphics accelerator hardware. The second processor supports the hardware accelerator with drivers operating in a single partition. This design abstracts the graphics calls from the native interface of the graphics hardware accelerator.

Abstract: One embodiment of a video processor includes a first media processing device coupled to a first memory and a second media processing device coupled to a second memory. The second media processing device is coupled to the first media processing device via a scalable bus. A software driver configures the media processing devices to provide video processing functionality. The scalable bus carries video data processed by the second media processing device to the first media processing device where the data is combined with video data processed by the first media processing device to produce a processed video frame. The first media processing device transmits the combined video data to a display device. Each media processing device is configured to process separate portions of the video data, thereby enabling the video processor to process video data more quickly than a single-GPU video processor.

Abstract: This invention discloses a method for executing vertex shader in a computer system, the method comprising running software vertex shader for a predetermined vertex shader command in a CPU thread when a GPU is overloaded by vertex shader execution, buffering the output of the software vertex shader, running hardware vertex shader for z-values of the vertex shader command, and replacing z-values from the software vertex shader with the z-values from the hardware vertex shader, wherein the vertex shader overloading can be lessoned yet the vertex shader z-values are consistently transformed by the hardware vertex shader.

Abstract: A distributed resource system comprises a plurality of compute resource units operable to execute graphics applications and generate graphics data, and a plurality of visualization resource units communicatively coupled to the plurality of compute resource units and operable to render pixel data from the graphics data. A first network couples a network compositor to the plurality of visualization resource units. The network compositor is operable to synchronize the received pixel data from the plurality of visualization resource units and receive the pixel data from the visualization resource units and to composite the synchronized pixel data into at least one image. A plurality of display devices, at least one of which is located remotely from the plurality of compute resource units, are coupled to the network compositor and operable to display the at least one image.

Abstract: A PC-based computing system employing a silicon chip having a routing unit, a control unit and profiling unit for parallelizing multiple GPU-driven pipeline cores according to the object division mode of parallelization operation, during a graphics application. The PC-based computing system includes system memory for storing software graphics applications, software drivers and graphics libraries, and an operating system (OS), stored in the system memory, and a central processing unit (CPU), for executing the OS, graphics applications, drivers and graphics libraries. The system also includes a CPU/memory interface module and a CPU bus. The routing unit (i) routes the stream of geometrical data and graphic commands from the graphics application to one or more of the GPU-driven pipeline cores, and (ii) routes pixel data output from one or more of GPU-driven pipeline cores during the composition of frames of pixel data corresponding to final images for display on the display surface.

Abstract: A system for activating an appliance responsive to one of many transmission schemes includes a transmitter, memory holding data describing the transmission schemes, and a controller in communication with the transmitter and the memory. The controller is operable to store a fixed code. If a fixed code is stored, then the controller transmits a sequence of fixed code activation schemes, based on the fixed code and data held in the memory, until input indicating activation of the appliance is received. If no fixed code is stored, then the controller transmits a sequence of rolling code activation schemes, based on data held in the memory, until input indicating activation of the appliance is received. The controller stores in the memory an indication as to which activation scheme activated the appliance based on the received input. The controller generates an activation signal based on the stored indication and a received activation input.

Abstract: An architecture for storing, addressing and retrieving graphics data from one of multiple memory controllers. In a first embodiment of the invention, one of the memory controllers having an accelerated graphics port (AGP) includes a set of registers defining a range of addresses handled by the memory controller that are preferably to be used for all AGP transactions. The AGP uses a graphics address remapping table (GART) for mapping memory. The GART includes page table entries having translation information to remap virtual addresses falling within the GART range to their corresponding physical addresses. In a second embodiment of the invention, a plurality of the memory controllers have an AGP, wherein each of the plurality of the memory controllers supplies a set of registers defining a range of addresses that is preferably used for AGP transactions.

Abstract: A system and method for optimizing the performance of a graphics intensive software program for graphics acceleration hardware. This system and method encompasses a procedure that validates the different functions of a 3D acceleration capable video card, decides whether to use the acceleration hardware and optimizes the software application to selectively use the functions that work on the specific video acceleration card. Functions checked include sub-pixel positioning, opacity, color replacement and fog. If these tests are successful, then the graphics acceleration is used by the software application. However, if the tests are not successful the decision is made not to use graphics accelerator. Those with ordinary skill in the art will realize that it is not necessary to perform all of the tests in a specific order.

Abstract: A processor generates Z-cull information for tiles and groups of tiles. In one embodiment the processor includes an on-chip cache to coalesce Z information for tiles to identify occluded tiles. In a coprocessor embodiment, the processor provides Z-culling information to a graphics processor.

Abstract: Methods and systems for processing a geometry shader program developed in a high-level shading language are disclosed. Specifically, in one embodiment, after having received the geometry shader program configured to be executed by a first processing unit in a programmable execution environment, the high-level shading language instructions of the geometry shader program is converted into low-level programming language instructions. The low-level programming language instructions are then linked with the low-level programming language instructions of a domain-specific shader program, which is configured to be executed by a second processing unit also residing in the programmable execution environment. The linked instructions of the geometry shader program are directed to the first processing unit, and the linked instructions of the domain-specific shader program are directed to the second processing unit.

Abstract: A system and method for optimizing the performance of a graphics intensive software program for graphics acceleration hardware. This system and method encompasses a procedure that validates the different functions of a 3D acceleration capable video card, decides whether to use the acceleration hardware and optimizes the software application to selectively use the functions that work on the specific video acceleration card. Functions checked include sub-pixel positioning, opacity, color replacement and fog. If these tests are successful, then the graphics acceleration is used by the software application. However, if the tests are not successful the decision is made not to use graphics accelerator. Those with ordinary skill in the art will realize that it is not necessary to perform all of the tests in a specific order.

Abstract: A method of providing physics data within a game program or simulation using a hardware-based physics processing unit having unique architecture designed to efficiently calculate physics related data.

Abstract: According to one embodiment, an information processing apparatus includes: a plurality of graphics processing units (GPUs) having different characteristics; a memory configured to store information on association between one of the plurality of GPUs and an application program; and a drawing control unit configured to control the GPU associated with the application program to perform drawing processing when the application program is run.

Abstract: Although GPUs have been harnessed to solve non-graphics problems, these solutions are not widespread because GPUs remain difficult to program. Instead, an interpreter simplifies the task of programming a GPU by providing language constructs such as a set of data types and operations that are more familiar to non-graphics programmers. The interpreter maps these familiar language constructs to the more difficult graphics programming resources such as DirectX®, OpenGL®, Cg®, and/or HLSL®.

Abstract: Many computing device may now include two or more graphics subsystems. The multiple graphics subsystems may have different abilities, and may, for example, consume differing amount of electrical power, with one subsystem consuming more average power than the others. The higher power consuming graphics subsystem may be coupled to the device and used instead of, or in addition to, the lower power consuming graphics subsystem, resulting in higher performance or additional capabilities, but increased overall power consumption. By transitioning from the use of the higher power consuming graphics subsystem to the lower power consuming graphics subsystem, while placing the higher power consuming graphics subsystem in a lower power consumption mode, overall power consumption is reduced.

Abstract: A storage apparatus comprises: a memory for storing a processing ratio/upper limit table, which stores an upper limit number per prescribed time for input/output processing in accordance with the processing of a processing type for each of a plurality of processing types executed by a host computer; and a processor which receives an input/output request from the host computer, and executes input/output processing corresponding to the input/output request, such that input/output processing corresponding to the processing of each processing type per prescribed time falls within the upper limit number. According to this constitution, the input/output processing count per prescribed time can be properly controlled in accordance with the processing type.

Abstract: A system, method and apparatus to provide flexible texture filtering. A programmable texture filtering module is introduced into the graphics processing pipeline of a graphic coprocessor and graphic processor integrated with the host. A program from a defined instruction set may then be loaded into texture processing cores to process texture data consistent with the program.

Abstract: Methods and systems for video format transformation in a mobile terminal having a video display may include converting interleaved YUV 4:2:2 color space video data to YUV 4:2:0 color space video data as the interleaved YUV 4:2:2 color space video data is received. The conversion may use Y, U, and V components in the interleaved YUV 4:2:2 color space video data for a horizontal line of video data. The conversion may also use only a Y component in the interleaved YUV 4:2:2 color space video data for a previous horizontal line or a successive horizontal line of video data. The converted 4:2:0 color space video data may be transferred to memory via, for example, direct memory access. The YUV 4:2:0 color space video data may be transferred to the memory as, for example, 32-bit words.

Abstract: An enhanced graphics pipeline is provided that enables common core hardware to perform as different components of the graphics pipeline, programmability of primitives including lines and triangles by a component in the pipeline, and a stream output before or simultaneously with the rendering a graphical display with the data in the pipeline. The programmer does not have to optimize the code, as the common core will balance the load of functions necessary and dynamically allocate those instructions on the common core hardware. The programmer may program primitives using algorithms to simplify all vertex calculations by substituting with topology made with lines and triangles. The programmer takes the calculated output data and can read it before or while it is being rendered. Thus, a programmer has greater flexibility in programming.

Abstract: A multiple GPU (graphics processor unit) graphics system is disclosed. The multiple GPU graphics system includes a plurality of GPUs configured to execute graphics instructions from a computer system. A GPU output multiplexer and a controller unit are coupled to the GPUs. The controller unit is configured to control the GPUs and the output multiplexer such that the GPUs cooperatively execute the graphics instructions from the computer system.

Abstract: Improved keyboard accelerators are provided for executing functionalities of a software application utilizing text-based and non text-based buttons or controls. Upon selection of a prescribed keyboard accelerator initiation key, for example, the “Alt” key, a keyboard accelerator key tip in the form of a small window is displayed over the functionality buttons or controls displayed in a deployed user interface. Each key tip is labeled with one or more text characters for informing a user as to a secondary keyboard selection that must be made to execute the associated functionality.

Abstract: An interactive cinematic lighting system used in the production of computer-animated feature films containing environments of very high complexity, in which surface and light appearances are described using procedural RenderMan shaders. The system provides lighting artists with high-quality previews at interactive framerates with only small approximations compared to the final rendered images. This is accomplished by combining numerical estimation of surface response, image-space caching, deferred shading, and the computational power of modern graphics hardware.

Abstract: Systems and methods are provided for processing data. The systems and methods include multiple processors that each couple to receive commands and data, where the commands and/or data correspond to frames of video that include multiple pixels. An interlink module is coupled to receive processed data corresponding to the frames from each of the processors. The interlink module divides a first frame into multiple frame portions by dividing pixels of the first frame using at least one balance point. The interlink module dynamically determines a position for the balance point that minimizes differences between the workload of the processors during processing of commands and/or data of one or more subsequent frames.

Abstract: A method comprises searching in a video stream a first frame and a second frame that each has enough point correspondence with a image model, wherein the first frame is the nearest previous frame prior to a third frame, and the second frame is the nearest subsequent frame to follow the third frame. The method further comprises calculating an interpolation between a first mapping matrix of the first frame and a second mapping matrix of the second frame to obtain a third mapping matrix of the third frame that has insufficient point correspondence with the image model.

Abstract: A pixel is textured by storing a first texel reference value, a second texel reference value, and texel mapping values where each texel mapping value represents a k-tuple of (ternary) references to the first texel reference value, the second texel reference value and a third texel reference value to thereby represent a block of texels. A pixel value for the pixel is generated from the stored texel values and the pixel is displayed responsive to the generated pixel value. In some embodiments, respective pluralities of texel reference values and texel mapping values that map thereto are stored for respective ones of a plurality of overlapping blocks of texels. In further embodiments, a first mipmap value for a pixel is bilinearly interpolated from the retrieved texel values for the set of nearest neighbor texels. A second mipmap value for the pixel is generated by averaging the retrieved texel values for the set of nearest neighbor texels.

Abstract: Multiple graphics processors in a graphics processing system are interconnected in a unidirectional or bidirectional ring topology, allowing pixels to transferred from any one graphics processor to any other graphics processor. The system can automatically identify one or more “master” graphics processors to which a monitor is connected and configures the links of the ring such that one or more other graphics processors can deliver pixels to the master graphics processor, facilitating distributed rendering operations. The system can also automatically detect the connections or lack thereof between the graphics processors.

Abstract: A shader program capable of execution on a GPU is analyzed for constant expressions. These constant expressions are replaced with references to registers or memory addresses on the GPU. A preshader is created that comprises two executable files. The first executable file contains the shader program with the each constant expression removed and replaced with a unique reference accessible by the GPU. The first file is executable at the GPU. A second file contains the removed constant expressions along with instructions to place the values generated at the associated reference. The second executable file is executable at a CPU. When the preshader is executed, an instance of the first file is executed at the GPU for each vertex or pixel that is displayed. One instance of the second file is executed at the CPU. As the preshader is executed, the constant expressions in the second file are evaluated and the resulting intermediate values are passed to each instance of the first file on the GPU.

Abstract: A methods and system for utilizing memory interface bandwidth to connect multiple graphics processing units are disclosed. According to one embodiment of the present invention, a first graphics processing unit is configured to allocate a portion of an initial memory interface supported by both the first graphics processing unit and a first video memory for a private connection. This private connection enables this first graphics processing unit to directly communicate with a second graphics processing unit and also access resources of the second graphics processing unit.

Abstract: Multichip graphics processing subsystems include at least three distinct graphics devices (e.g., expansion cards) coupled to a high-speed bus (e.g., a PCI Express bus) and operable in a distributed rendering mode. One of the graphics devices provides pixel data to a display device, and at least one of the other graphics devices transfers the pixel data it generates to another of the devices via the bus to be displayed. Where the high-speed bus provides data transfer lanes, allocation of lanes among the graphics devices can be optimized.

Abstract: A method for rendering a real-time conformal view of terrestrial body's terrain being traversed by a mobile platform includes storing digital terrain elevation data (DTED) tiles for at least a portion of the terrain of a terrestrial body into an external removable mass data storage device (ERMDSD). The ERMDSD is connectable to an onboard computer system (OCS) comprising embedded mobile platform components that include at least one processing card, at least random access memory (RAM) device and at least one graphics card. The method additionally includes executing a real-time rendering assist application (RTRAA) stored in the processing card to dynamically repackage the DTED tiles into DTED chunks being representative of an area of the terrestrial body to be traversed (ATBT) by the mobile platform. The method further includes executing the RTRAA to create a base mesh of root diamonds representative of the ATBT and tessellate the root diamonds to create a plurality of leaf diamonds.

Abstract: The invention refers to a video data processing system and a video data processing circuit, comprising at least two functional blocks of which at least a first functional block is programmable so that different functions can be provided by said first functional block.

Abstract: A method and apparatus for performing multisampling-based antialiasing in a system that includes first and second graphics processing unit (GPUs) that reduces the amount of data transferred between the GPUs and improves the efficiency with which such data is transferred. The first GPU renders a first version of a frame using a first multisampling pattern and the second GPU renders a second version of a frame in the second GPU using a second multisampling pattern. The second GPU identifies non-edge pixels in the second version of the frame. The pixels in the first version of the frame are then combined with only those pixels in the second version of the frame that have not been identified as non-edge pixels to generate a combined frame.

Abstract: A system, method, and computer program product are provided for offloading application tasks in a multi-processor environment. In use, an application is executed utilizing a first processor. Such application performs a plurality of tasks. A driver is provided for determining at least a subset of the tasks. To this end, the subset of tasks may be executed utilizing a second processor.

Abstract: A method of guided attachment of hardware accelerators to slots of a computing system includes dividing a first group of hardware accelerators into a plurality of priority classes, dividing a first group of slots of the computing system into a plurality of hierarchical tiers, and attaching each hardware accelerator of the first group of hardware accelerators to a slot matched to the hardware accelerators based on comparison of a priority class of the hardware accelerator and a hierarchical tier of the slot.

Abstract: A system, method and apparatus are disclosed, in which an instruction scheduler of a compiler, e.g., a shader compiler, reduces instruction latency based on a determined instruction distance between a dependent predecessor and successor instructions.

Abstract: A system and method for providing a dedicated interface between two or more graphics adapters installed on a motherboard. Surplus signals within an interface conforming to an interface specification are used to create the dedicated interface. The dedicated interface may connect the two or more graphics adapters using connectors via an interface device. Alternatively the dedicated interface may directly connect the two or more graphics adapters using dedicated connectors or a portion of the connectors coupled through conductive traces integrated onto the motherboard.

Abstract: A method and system for controlling the algorithmic elements in 3D graphics systems via an improved 3D graphics API is provided. In one aspect, in a 3D graphics system having privatized formats with privatized drivers used to increase the efficiency of display, existing problems are eliminated that are associated with multiple redundant copies of the publicly formatted graphics data made in host system memory pursuant to various graphics operations e.g., lock and unlock operations. The ability to make a system copy of publicly formatted data is exposed to the developer, eliminating the creation of unnecessary, and redundant copies. Efficient switching between the privatized and public format remains hidden from the developers so that applications execute efficiently while removing consideration thereof from the developers. Thus, developers are free to consider other tasks.

Abstract: The present invention relates to a data processing apparatus provided with a multi-graphic controller and a data processing method using the data processing apparatus. A data processing apparatus of the present invention comprises a first graphic controller 10a and a second graphic controller 20 for processing and displaying inputted image data; and a control unit 50 for distributing the image data in consideration of data processing capabilities of the first and second graphic controllers 10a and 20. According to the present invention, there is provided a data processing apparatus and method capable of simultaneously using a plurality of graphic controllers, so that data processing speed can be improved. Image data are appropriately distributed, whereby the efficiency of data processing can be enhanced.

Abstract: A system for decoding a stream of compressed digital video images comprises a graphics accelerator for reading the stream of compressed digital video images, creating, starting from said stream of compressed digital video images, three-dimensional scenes to be rendered, and converting the three-dimensional scenes to be rendered into decoded video images. The graphics accelerator is preferentially configured as pipeline selectively switchable between operation in a graphics context and operation for decoding the stream of video images. The graphics accelerator is controllable during operation for decoding the stream of compressed digital video images via a set of application programming interfaces comprising, in addition to new APIs, also standard APIs for operation of the graphics accelerator in a graphics context.

Abstract: A visual tree structure as specified by a program is constructed and maintained by a visual system's user interface thread. As needed, the tree structure is traversed on the UI thread, with changes compiled into change queues. A secondary rendering thread that handles animation and graphical composition takes the content from the change queues, to construct and maintain a condensed visual tree. Static visual subtrees are collapsed, leaving a condensed tree with only animated attributes such as transforms as parent nodes, such that animation data is managed on the secondary thread, with references into the visual tree. When run, the rendering thread processes the change queues, applies changes to the condensed trees, and updates the structure of the animation list as necessary by resampling animated values at their new times. Content in the condensed visual tree is then rendered and composed. Animation and a composition communication protocol are also provided.

Abstract: Methods and systems are described that unite various shading applications under a single language, enable the simple re-use and re-purposing of shaders, facilitate the design and construction of shaders without need for computer programming, and enable the graphical debugging of shaders.

Abstract: An apparatus generally having an internal memory and an external transfer circuit is disclosed. The internal memory may be disposed on a chip and may contain at least one first buffer for storing a subset of at least one reference frame (i) suitable for motion compensation and (ii) stored in an external memory off the chip. A size of the at least one first buffer generally exceeds one row of blocks in the reference frame. The external transfer circuit may be disposed on the chip and configured to transfer the subset from the external memory to the internal memory.

Abstract: An API is provided to feed multiple data objects, wherever originated or located at the time of operation, to a 3D graphics chip simultaneously or in parallel. Multiple containers may be fed to a 3D graphics chip memory at the same time. In the case where data is being transmitted to a graphics chip memory, wherein the data includes the same spatial position of pixel(s), but only the orientation or color is changing, the data may be loaded into two separate containers, with a header description understood by the graphics chip and implemented by the graphics API, whereby a single copy of the position data can be loaded into one container, and the changing color or orientation data may be loaded into a second container. Thus, when received by the graphics chip, the data is loaded correctly into register space and processed according to the header description.

Abstract: One embodiment of a video processor includes a first media processing device coupled to a first memory and a second media processing device coupled to a second memory. The second media processing device is coupled to the first media processing device via a scalable bus. A software driver configures the media processing devices to provide video processing functionality. The scalable bus carries video data processed by the second media processing device to the first media processing device where the data is combined with video data processed by the first media processing device to produce a processed video frame. The first media processing device transmits the combined video data to a display device. Each media processing device is configured to process separate portions of the video data, thereby enabling the video processor to process video data more quickly than a single-GPU video processor.

Abstract: A graphics processing unit has a set of parallel processing units. A primitive pipeline delivers tiles of a primitive to selected processing units of the set of processing units. An attribute pipeline distributes attributes to the selected processing units when the end of the primitive is reached, while withholding attributes from the remaining processing units of the set of processing units.

Abstract: A floating point rasterization and frame buffer in a computer system graphics program. The rasterization, fog, lighting, texturing, blending, and antialiasing processes operate on floating point values. In one embodiment, a 16-bit floating point format consisting of one sign bit, ten mantissa bits, and five exponent bits (s10e5), is used to optimize the range and precision afforded by the 16 available bits of information. In other embodiments, the floating point format can be defined in the manner preferred in order to achieve a desired range and precision of the data stored in the frame buffer. The final floating point values corresponding to pixel attributes are stored in a frame buffer and eventually read and drawn for display. The graphics program can operate directly on the data in the frame buffer without losing any of the desired range and precision of the data.

Abstract: A spatial positioning and measurement system provides three-dimensional position and/or measurement information of an object using one or more fixed referent station systems, and one or more portable position sensor systems. Each fixed station produces at least one primary laser beam which is rotated at a constant angular velocity about a vertical axis. The primary laser beam has a predetermined angle of divergence or angle of spread which is inclined at a predetermined angle from the vertical axis. Each fixed station also preferably includes at least one reflective surface for generating a secondary laser beam.The portable position sensor includes a light sensitive detector, computer, and a display. The light sensitive detector can be formed of at least one "axicon" which directs incoming light to a photosensitive detector. The photosensitive detector generates an electrical pulse when struck by crossing laser beam and sends this pulse to the computer.