Abstract: One embodiment of the invention sets forth a computing system for performing cryptographic computations. The computing system comprises a central processing unit, a graphics processing unit, and a driver. The central processing requests a cryptographic computation. In response, the driver downloads microcode to perform the cryptographic computation to the graphics processing unit and the graphics processing unit executes microcode. This offloads cryptographic computations from the CPU. As a result, cryptographic computations are performed faster and more efficiently on the GPU, freeing resources on the CPU for other tasks.

Abstract: A functional unit is added to a graphics processor to provide direct support for double-precision arithmetic, in addition to the single-precision functional units used for rendering. The double-precision functional unit can execute a number of different operations, including fused multiply-add, on double-precision inputs using data paths and/or logic circuits that are at least double-precision width. The double-precision and single-precision functional units can be controlled by a shared instruction issue circuit, and the number of copies of the double-precision functional unit included in a core can be less than the number of copies of the single-precision functional units, thereby reducing the effect of adding support for double-precision on chip area.

Abstract: An accelerator chip can be positioned between a processor chip and a memory. The accelerator chip enhances the operation of a Java program by running portions of the Java program for the processor chip. In a preferred embodiment, the accelerator chip includes a hardware translator unit and a dedicated execution engine.

Abstract: A graphics processor may be operated in a reduced power mode to render frames at rate equal to or less than the rate at which frames are presented on an interconnected display. Graphics processor clock speeds are controlled to reduce the time during which the graphics processor is idle between rendering frames. The graphics processor clock speed may thus be slowed without impacting the quality of rendered images. At the same time the voltage applied to power the graphics processor may be reduced. Optionally, a back bias voltage may further be applied to the processor substrate to reduce power consumption. Clock speed and voltage levels may be adjusted using closed-loop control.

Abstract: A system, method and apparatus are disclosed, in which an instruction scheduler of a compiler, e.g., a shader compiler, reduces instruction latency based on a determined instruction distance between a dependent predecessor and successor instructions.

Abstract: Systems and techniques for processing sequences of video images involve receiving, on a computer, data corresponding to a sequence of video images detected by an image sensor. The received data is processed using a graphics processor to adjust one or more visual characteristics of the video images corresponding to the received data. The received data can include video data defining pixel values and ancillary data relating to settings on the image sensor. The video data can be processed in accordance with ancillary data to adjust the visual characteristics, which can include filtering the images, blending images, and/or other processing operations.

Abstract: An accelerator chip can be positioned between a processor chip and a memory. The accelerator chip enhances the operation of a Java program by running portions of the Java program for the processor chip. In a preferred embodiment, the accelerator chip includes a hardware translator unit and a dedicated execution engine.

Abstract: A multi-mode parallel 3-D graphics system having multiple graphics processing pipelines with multiple GPUs supporting a parallel graphics rendering process having time, frame and object division modes of operation, wherein each GPU comprises video memory, a geometry processing subsystem and a pixel processing subsystem, and wherein 3D scene profiling is performed in real-time, and the parallelization state/modes of the system are dynamically controlled to meet graphics application requirements. The multiple modes of parallel graphics rendering use real-time graphics application profiling, and dynamic control over time-division, frame-division, and object-division modes of parallel operation, within the same parallel graphics platform, which can be realized on PC-based computing system architectures.

Abstract: Systems and methods for assembling pixel shader program threads for execution based on resource limitations of a multithreaded processor may improve processing throughput. Pixels to be processed by the pixel shader program are assembled into a launch group for processing by the multithreaded processor as multiple shader program threads. The pixels are assembled based on parameter storage resource limitations of the multithreaded processor so that common parameters shared by multiple pixels are not stored separately for each pixel. Therefore, the limited parameter storage resources are efficiently used, allowing more shader program threads to execute simultaneously.

Abstract: A system and method for optimizing the performance of a graphics intensive software program for graphics acceleration hardware. This system and method encompasses a procedure that validates the different functions of a 3D acceleration capable video card, decides whether to use the acceleration hardware and optimizes the software application to selectively use the functions that work on the specific video acceleration card. Functions checked include sub-pixel positioning, opacity, color replacement and fog. If these tests are successful, then the graphics acceleration is used by the software application. However, if the tests are not successful the decision is made not to use graphics accelerator. Those with ordinary skill in the art will realize that it is not necessary to perform all of the tests in a specific order.

Abstract: An information processing apparatus performs switching between an exception handler and normal processing. The information processing apparatus includes a processor; a data processing unit that performs particular processing upon receiving a processing request from the processor; an interrupt controller that issues an interrupt request to the processor; and an exception control unit that controls the interrupt controller, wherein the data processing unit is connected with the exception control unit via a dedicated line. The data processing unit includes a notification unit that notifies, via the dedicated line, the exception control unit of status information indicating current status of the data processing unit, and based on the notified status information and setup information set by the processor, the exception control unit judges whether to cause the interrupt controller to issue an interrupt request to execute an exception handler to the processor.

Abstract: The present invention provides a cost effective method to improve the performance of communication appliances by retargeting the graphics processing unit as a coprocessor to accelerate networking operations. A system and method is disclosed for using a coprocessor on a standard personal computer to accelerate packet processing operations common to network appliances. The appliances include but are not limited to routers, switches, load balancers and Unified Threat Management appliances. More specifically, the method uses common advanced graphics processor engines to accelerate the packet processing tasks.

Abstract: An information processing apparatus that includes a first graphic processing module having a first level of graphic performance and a second graphic processing module having a second level of graphic performance, which is greater than the first level of graphic performance. The information processing apparatus also includes a controller that selects one of the first graphic processing module or the second graphic processing module by determining whether the information processing apparatus is capable of outputting data with the first level of graphic performance or the second level of graphic performance, and detects whether the information processing apparatus is provided with power via a battery or via an external power source.

Abstract: Multichip graphics processing subsystems include at least three distinct graphics devices (e.g., expansion cards) coupled to a high-speed bus (e.g., a PCI Express bus) and operable in a distributed rendering mode. One of the graphics devices provides pixel data to a display device, and at least one of the other graphics devices transfers the pixel data it generates to another of the devices via the bus to be displayed. Where the high-speed bus provides data transfer lanes, allocation of lanes among the graphics devices can be optimized.

Abstract: A drawing apparatus includes a reception unit, a first holding unit and a drawing processing unit. The reception unit receives graphic information. The first holding unit holds a plurality of first data which is a part of the graphic information received by the reception unit, in association with identification numbers assigned to the first data. The drawing processing unit draws a graphic on the basis of the first data held in the first holding unit. The drawing processing unit uses the plurality of the first data in a same task to draw the graphic. The reception unit records the identification numbers of the first data and a synchronization flag in order of reception. The synchronization flag is set for the first data received first among the plurality of first data processed by the same task in the drawing processing unit.

Abstract: A rendering processing unit of a graphics processor selects a buffer in a frame buffer in which to write rendering data by switching between multiple buffers in the frame buffer and writes rendering data accordingly; a display controller selects a buffer in the frame buffer from which to read rendering data by switching between a plurality of buffers in the frame buffer according to a sequence, and supplies the rendering data read by scanning the frame buffer to a display; a switching signal generating unit generates a buffer switching signal for directing the display controller to switch the buffer in the frame buffer from which to read at a frequency different from a vertical synchronization frequency of the display assumed by the graphics processor.

Abstract: Apparatus are provided including assets defining 3D models, including 3D icons and scenes, and animations of the 3D models. An offline optimization engine is provided to process data to be acted upon by a graphics engine of a target embedded device. A graphics engine simulator is provided to simulate, on a computer platform other than a target embedded device, select functions of a target embedded device running a graphics engine including API calls that directly calls API functions of a hardware level API of the target embedded device.

Abstract: A method and apparatus which includes a graphics accelerator, circuitry responsive to pixel texture coordinates to select texels and generate therefrom a texture value for any pixel the color of which is to be modified by a texture, a cache to hold texels for use by the circuitry to generate texture value for any pixel, a stage for buffering the acquisition of texel data, and control circuitry for controlling the acquisition of texture data, storing the texture data in the cache, and furnishing the texture data for blending with pixel data.

Abstract: A multi-screen signal processing device includes a main graphics processor and a plurality of sub-graphics processors. The main graphics processor is electrically connected to the plurality of sub-graphics processors respectively. The main graphics processor is used for receiving an external image data, and capable of decoding the external image data and outputting a frame data. Each sub-graphics processor respectively captures a part of the frame data synchronously and outputs a broadcasting signal. The multi-screen signal processing device may be connected to multiple screens to play multiple images at the same time. Moreover, the decoding step using a single graphics processor enables easy synchronization of frames displayed on different screens and saves energy consumed by repeating the decoding step.

Abstract: A server apparatus and a server control method which transmits display data to a client apparatus and which displays the display data on a display screen of the client apparatus, wherein there are provided a plurality of accelerators, each of the plurality of accelerators being equipped with a difference detection circuit which compares the display data for a previous screen transmitted to the client apparatus with the display data for a current screen to be transmitted to the client apparatus to detect a difference therebetween. Then, the size of a drawing area to be allocated to each of the plurality of accelerators is calculated for each of the accelerators in response to a request from the client apparatus, and when a display request is made from a new client apparatus, the accelerator having a smaller drawing area among the calculated drawing areas is allocated to the new client apparatus.

Abstract: A boost table stores adjusted target levels for pairs of original and target pixel levels. The adjusted target levels can be used to as a substitute for the target pixel level to improve pixel response in reaching the desired target pixel level. A reduced boost table can be used, storing a subset of the adjusted target levels. Fuzzy logic control rules can be used to calculate adjusted target levels not actually stored in the reduced boost table.

Abstract: An arithmetic processing unit in a graphics processor alternately executes a process of a first image processing which generates a main image of an application, i.e., a base image and a process of a second image processing which generates a display image eventually displayed by performing a desired processing of the base image. Processing time for the process of the first image processing is designated by a first process executing unit in a main processor which requests execution of the process of the first image processing. Processing time for the process of the second image processing is predetermined. The first process executing unit further determines an address of storage area in a frame buffer storing the base image and, upon determination, transmits to the second process executing unit which requests execution of the process of the second image processing.

Abstract: Methods and systems are disclosed for an information handling system comprising an internal graphics system and an external graphics system, wherein both the internal and external graphics systems may operate simultaneously to support multiple monitors. The internal graphics system may be provided, for example, from a notebook computer. The external graphics system may comprise a pass thru port providing graphics from the internal graphics to a first monitor simultaneously with a graphics card of the external graphics system supporting a second monitor. The external graphics system can support two monitors, as well. HDTV can be supported instead of one of the monitors supported by the external graphics system. The system which contains internal graphics capabilities may include an Express card socket, wherein an external graphics processor unit of the external graphics system is coupled to Express card socket.

Abstract: A1A system embodying the invention includes a controlling device and a set of rendering devices, with the effect that the controlling device can distribute a set of objects to the rendering devices. Each rendering device computes a (2D) image in response to the objects assigned to it, including computing multiple overlapping images and using a graphics processor to blend those images into a resultant image. To interface with the graphics processor, each rendering device spoofs the ?-value with a pixel feature other than opacity (opacity is expected by the graphics processor), with the effect that the graphics processor delivers useful ?-values, while still delivering correct color values, for each pixel. This has the effect that the resultant images include transparency information sufficient to combine them using transparency blending.

Abstract: The disclosed embodiments provide a system that configures a computer system to switch between graphics-processing units (GPUs). In one embodiment, the system drives a display using a first graphics-processing unit (GPU) in the computer system. Next, the system detects one or more events associated with one or more dependencies on a second GPU in the computer system. Finally, in response to the event, the system prepares to switch from the first GPU to the second GPU as a signal source for driving the display.

Abstract: Embodiments of the present invention are directed to provide a method and system for applying automatic power conservation techniques in a computing system. Embodiments are described herein that automatically limits the frame rate of an application executing in a discrete graphics processing unit operating off battery or other such exhaustible power source. By automatically limiting the frame rate in certain detected circumstances, the rate of power consumption, and thus, the life of the current charge stored in a battery may be dramatically extended. Another embodiment is also provided which allows for the more effective application of automatic power conservation techniques during detected periods of inactivity by applying a low power state immediately after a last packet of a frame is rendered and displayed.

Abstract: Described are a system and method for broadcasting write requests to a plurality of graphics devices. A different address range of graphics device addresses is associated with each graphics device of the plurality of graphics devices. A controller receives a write request directed to a memory address and generates a plurality of graphics device addresses based on the memory address of the write request when the memory address is within a particular range of broadcast addresses. An offset may be applied to a reference address in each address range associated with one of the graphics devices when generating the plurality of graphics device addresses. The write request is forwarded to each graphics device of the plurality of graphics devices associated with one of the generated graphics device addresses.

Abstract: This invention relates to an information-signal-processing apparatus etc. for performing a series of processing pieces by using plural functional blocks in response to any information signals, in which functions can be easily upgraded through version upgrading of the functional blocks. Control block 110 issues a common command and transmits it to a control block 120 via a control bus 111. Control I/F 120 of the functional block 120 converts this common command into an intra-functional-block command if the common command is the common command related to its own functional block, and supplies the functional section 120e with it. This enables the functional block 120 to operate adaptively in accordance with the common command. When performing upgrade of the functions by the version updating of a predetermined function block, the common command need not be changed.

Abstract: There is disclosed a character rendering device capable of rendering characters at a higher speed.

Abstract: A “Variable-Rate Perfect Hasher” maps sparse variable-rate data of one or more dimensions into a hash table using a perfect hash function. In various embodiments, perfect hash tables are populated by first computing offset table address for each data point of a domain of sparse variable-rate data elements. Offset vectors are then computed for each offset table address based in part on the size of each data element by evaluating offset vectors in order of a sum of the data point addresses mapping to each offset vector. These offset vectors are then stored in the offset table. For each data point, the corresponding offset vector is then used to compute a hash table address. Data elements are then perfectly hashed into the hash table using the computed hash table addresses. The resulting hash tables support efficient random access of the variable-sized data elements stored therein.

Abstract: The invention refers to a video data processing system and a video data processing circuit, comprising at least two functional blocks of which at least a first functional block is programmable so that different functions can be provided by said first functional block.

Abstract: Embodiments of the invention provide assigning two different class identifiers to a device to allow loading to an operating system as different devices. The device may be a graphics device. The graphics device may be integrated in various configurations, including but not limited to a central processing unit, chipset and so forth. The processor or chipset may be associated with a first identifier associated with a graphics processor and a second device identifier that enables the processor or chipset as a co-processor.

Abstract: A method of guided attachment of hardware accelerators to slots of a computing system includes dividing a first group of hardware accelerators into a plurality of priority classes, dividing a first group of slots of the computing system into a plurality of hierarchical tiers, and attaching each hardware accelerator of the first group of hardware accelerators to a slot matched to the hardware accelerators based on comparison of a priority class of the hardware accelerator and a hierarchical tier of the slot.

Abstract: A novel personal electronic device includes a first (embedded) and second (non-embedded) processors including associated operating systems and functions. In one aspect, the first processor performs relatively limited functions, while the second processor performs relatively broader functions under control of the first processor. Often the second processor requires more power than the first processor and is selectively operated by the first processor to minimize overall power consumption. Protocols for functions to be performed by the second processor may be provided directly to the second processor and processed by the second processor. In another aspect, a display controller is designed to interface with both processors. In another aspect, the operating systems work with one another. In another aspect, the first processor employs a thermal control program. Advantages of the invention include a broad array of functions performed by a relatively small personal electronic device.

Abstract: An information processor for information registration, capturing means captures a graphics processing command, and database registering means registers, as information about completed work in the database, information about a series of graphics processing commands concerning completed works out of the captured graphics processing commands. In an information processor for information retrieval, proceeding work detecting means detects a work in progress as a proceeding work based on the captured graphics processing command, and information acquiring means searches a database for the information about the work in progress which has been done before based on the graphics processing command concerning the proceeding work and acquires the information about the work in progress which has been done before.

Abstract: A method of operating a Linear Complementarity Problem (LCP) solver is disclosed, where the LCP solver is characterized by multiple execution units operating in parallel to implement a competent computational method adapted to resolve physics-based LCPs in real-time.

Abstract: An information processing apparatus performs switching between an exception handler and normal processing. The information processing apparatus includes a processor a data processing unit that performs a particular processing upon receiving a processing request from the processor; an interrupt controller that issues an interrupt request to the processor; and an exception control unit that controls the interrupt controller, wherein the data processing unit is connected with the exception control unit via a dedicated line. The data processing unit includes a notification unit that notifies, via the dedicated line, the exception control unit of status information indicating current status of the data processing unit, and based on the notified status information and setup information set by the processor, the exception control unit judges whether to cause the interrupt controller to issue to the processor an interrupt request to execute an exception handler.

Abstract: A data processing system is provided with a general purpose programmable processor and an accelerator processor. Coherency control circuitry manages data coherence between data items which may be stored within a cache memory and/or a further memory. Memory access requests from the accelerator processor are received by a memory request switching circuitry which is responsive to a signal from the accelerator processor to direct the memory access request either via coherency control circuit or directly to the further memory.

Abstract: The present invention provides a cost effective method to improve the performance of communication appliances by retargeting the graphics processing unit as a coprocessor to accelerate networking operations. A system and method is disclosed for using a coprocessor on a standard personal computer to accelerate packet processing operations common to network appliances. The appliances include but are not limited to routers, switches, load balancers and Unified Threat Management appliances. More specifically, the method uses common advanced graphics processor engines to accelerate the packet processing tasks.

Abstract: The graphics co-processing technique includes loading a device specific kernel mode driver of a second graphics processing unit tagged as a non-graphics device. A device driver interface and a device specific kernel mode driver is loaded and initialized for a graphics processing unit on a primary adapter. A device driver interface and a device specific kernel mode driver for a graphics processing unit on the non-graphics tagged adapter is also loaded and initialized without the device driver interface talking back to a runtime application programming interface when a particular version of an operating system would not otherwise allow the device specific kernel mode driver for the second graphics processing unit to be loaded.

Abstract: The graphics co-processing technique includes loading and initializing a device driver interface and a device specific kernel mode driver for a graphics processing unit on a primary adapter. A device driver interface and a device specific kernel mode driver for a graphics processing unit on an unattached adapter is also loaded and initialized without the device driver interface talking back to a runtime application programming interface or a thunk layer when a particular versions of an operating system will not allow the device driver interface on the unattached adapter to be loaded.

Abstract: The current invention provides a virtual world simulation system capable of hosting with massive amount of concurrent players by integrating commodity parallel co-processors into servers. The current invention proposes novel parallel processing algorithms to make use of commodity parallel co-processors like a graphic processing unit (GPU) or any specialized hardware with parallel architecture design like a field-programmable gate array (FPGA), to accelerate virtual world simulation.

Abstract: Graphics rendering in a virtual machine system is accelerated by utilizing host graphics hardware. In one embodiment, the virtual machine system includes a server that hosts a plurality of virtual machines. The server includes one or more graphics processing units. Each graphics processing unit can be allocated to multiple virtual machines to render images. A hypervisor that runs on the server is extended to include a redirection module, which receives a rendering request from a virtual machine and redirects the rendering request to a graphics driver. The graphics driver can commands an allocated portion of a graphics processing unit to render an image on the server.

Abstract: Multiple graphics processors in a graphics processing system are interconnected in a unidirectional or bidirectional ring topology, allowing pixels to transferred from any one graphics processor to any other graphics processor. The system can automatically identify one or more “master” graphics processors to which one or more monitors are connected and configures the links of the ring such that one or more other graphics processors can deliver pixels to the master graphics processor, facilitating distributed rendering operations. The system can also automatically detect the connections or lack thereof between the graphics processors.

Abstract: An integrated circuit includes at least two different types of processors. At least one operation is supported by both types of processors, which permits a commonly supported operation to be scheduled on either processor.

Abstract: Provided is a three-dimensional (3D) graphic processing system and method capable of utilizing camera preview images in which the camera preview images are stored in a texture memory and then the stored camera preview images are used as a texture in a 3D graphic processor. The camera preview images are stored in a texture memory and then the stored camera preview images are used as a texture in a 3D graphic processor, in a manner that an extended function can be supported through a mutual operation of a preview processor and a graphic processor. The camera preview is displayed on the moving polygonal plane to which a near-and-far sense is applied, or the camera image is used as a background texture to then enable 3D objects to be drawn on the background texture. As a result, games with real feeling can be developed in a manner that 3D contents can be realized using real images as a background.

Abstract: An information processing device in which a data bus for establishing interconnection between a plurality of control operating units formed in a main processor is connected at one end to a graphic processor and at the other end to a main memory. Image frame data generated by the graphic processor is sequentially transferred through the data bus and stored into the main memory. The data bus satisfies R1?R2?R4 and R1?R3?R4, where R1 is the data transmission rate from the main processor to the graphic processor, R2 is the data transmission rate from the graphic processor to the main processor, R3 is the data transmission rate between the main processor and the main memory, and R4 is the rate to transmit a single image frame of data within a vertical blanking interval.

Abstract: The present invention is generally related to the field of image processing, and more specifically to an instruction set for processing images. Vector processing may involve rearranging vector operands in one or more source registers prior to performing vector operations. Typically, rearranging of operands in source registers is done by issuing a plurality of permute instructions that require excessive usage of temporary registers. Furthermore, the permute instructions may cause dependencies between instructions executing in a pipeline, thereby adversely affecting performance. Embodiments of the invention provide a level of muxing between a register file and a vector unit that allow for rearrangement of vector operands in source registers prior to providing the operands to the vector unit, thereby obviating the need for permute instructions.

Abstract: Methods, systems, apparatus, and computer-readable media are provided for utilizing an alternate video buffer for console redirection in a headless computer system. According to the method, a buffer is created in the main memory of the computer that is configured to store character and attribute data for a display of the computer. When a video services software interrupt is detected, the interrupt is trapped. A determination is then made as to whether a function associated with the interrupt is for writing to a video display memory. If the function is for writing, the contents of the buffer are updated with the character or attribute information specified by the function. Data representing the updated character or attribute is then redirected to the remote computing device. If a read function is encountered, character or attribute information is retrieved from the buffer at a specified location and is returned in response to the function call.

Abstract: A display processor includes an interface unit, an instruction processor, a synchronization unit, at least one processing unit, and a device buffer. The interface unit receives input image data (e.g., from a main memory) and provides output image data for a frame buffer. The instruction processor receives instructions (e.g., in a script or list) and directs the operation of the processing unit(s). The synchronization unit determines the location of a read pointer for the frame buffer and controls the writing of output image data to the frame buffer to avoid causing visual artifacts on an LCD screen. The processing unit(s) may perform various post-processing functions such as region flip, region rotation, color conversion between two video formats (e.g., from YCrCb to RGB), up/down image size rescaling, alpha-blending, transparency, text overlay, and so on.