Abstract: A driving method includes: generating and outputting a frame image signal to an organic light emitting device, wherein the frame image signal includes an active data region and a blank region based on a time sequence; in the active data region of the frame image signal, using a timing controller to write a data voltage into the gate of the thin film transistor, store it in a storage capacitor, and apply it to the organic light emitting device through the thin film transistor; and in response to reaching the blank region of the frame image signal as determined by the timing controller, changing the first voltage at the cathode of the organic light emitting device to compensate the operating current of the organic light emitting device.

Abstract: Apparatuses, systems, and techniques for performing nested kernel execution within a parallel processing subsystem. In at least one embodiment, a parent thread launches a nested child grid on the parallel processing subsystem, and enables the parent thread to perform a thread synchronization barrier on the child grid for proper execution semantics between the parent thread and the child grid.

Abstract: A system having a plurality of devices configured in a daisy chain network including a communication bus connecting the devices and adapted to exchange address-setting information. Each device includes an input pin adapted to receive via an input signal line different from the communication bus a signal comprising configuration information for configuring at least the device; a configuration handling unit adapted to detect a configuration mode and to configure the device according to the configuration information; an indicator adapted to indicate whether the configuration handling unit has finished configuring the device; an output pin adapted to forward the configuration information to the daisy chain network when the indicator indicates the configuration of the device is done; and a safety handling unit adapted to be operable in a safety handling mode when the indicator indicates the configuration of the device is done.

Abstract: A vehicle controller includes: an execution unit configured to execute a control program for controlling a vehicle; a storage unit having a first program storage area to store the control program and a second program storage area to store an update program that is an updated version of the control program and created based on update data acquired from a device located outside the vehicle through a network; and an update unit that stores the update program in the second program storage area based on the update data, regardless of whether the execution unit is executing the control program.

Abstract: A display system may include a bezel. The bezel may include a bezel light sensor. The display system may include a screen set within the bezel. The display system may include a controller coupled to the bezel light sensor. The controller may be configured to receive a flashing light signal via the bezel light sensor. The flashing light signal may include a set of coded information. The flashing light signal may be transmitted by a light generator. The controller may be configured to generate a response to the set of coded information. The controller may be configured to provide the response to the set of coded information via the screen.

Abstract: Multiple-thread processing apparatuses and methods are provided. The multiple-thread processing method may include searching for loops in a plurality of threads, calculating a number of repetitions of each of found loops in respective threads among the plurality of threads, determining one or more threads based on the calculated number of repetitions of each of the found loops, dividing at least one of the one or more determined threads into child threads, and processing the child threads separately from one another in the plurality of threads.

Abstract: Disclosed are various examples for differential staging of devices in bulk enrollment. In one example, a computing environment can detect a network connection event where a client device establishes a connection with a network device that is communicatively coupled to the computing environment. A configuration file can be copied from a data store of the at least one computing device to local memory of the client device. The configuration file can comprise one or more predefined configuration settings. A configuration of the at least one client device can be caused using the configuration file. The configuration can include automating user interface events on the client device to cause a setting of the client device to conform to the predefined configuration settings.

Abstract: The present invention relates to methods or system for the measurement of differential latency between displays located at endpoints of network, displays being driven by one or more rendering machines and having means for refreshing the images on different displays at the same point in time as well as means adapted so that the content of each displayed image can only change after the completion of previous displayed frame. For example the displays can be frame locked and have double buffered swap locked memory operation. The method or system is adapted to stream test images over the network to the displays of the different endpoints. The test images are displayed on the displays. The displayed images at the different endpoints with an image recording device such as a camera. Optionally the delays can be compensated, e.g. by delaying the streams with lower latency at the level of the frame buffer (FIFO) before or after decoding.

Abstract: A computer-implemented method may include receiving input to a vehicle-associated computing system (VACS) touch-sensitive display, requesting adjustment to a powered state of an accessory device connected to a switch module; providing, responsive to the input, a command from a vehicle computing system to the switch module, running on the VACS, to adjust a controlled output of the switch module; and updating the user interface to reflect a result of the command.

Abstract: An adaptable and extensible interface is described for connecting one or more point of sale (POS) applications to one or more at a wide variety of retail application is described. The interface may be embodied as a programmable state machine employing XML tiles to customize its operation reusable retail applications may be utilized as part of the interface approach.

Abstract: A texture processing pipeline can be configured to service memory access requests that represent texture data access operations or generic data access operations. When the texture processing pipeline receives a memory access request that represents a texture data access operation, the texture processing pipeline may retrieve texture data based on texture coordinates. When the memory access request represents a generic data access operation, the texture pipeline extracts a virtual address from the memory access request and then retrieves data based on the virtual address. The texture processing pipeline is also configured to cache generic data retrieved on behalf of a group of threads and to then invalidate that generic data when the group of threads exits.

Abstract: An apparatus having first, second and third processors of a multi-core processor is disclosed. The first processor is configured to perform one or more first operations in a decoding of a plurality of macroblocks of video in a bitstream. The second processor (i) operates as a slave to the first processor and (ii) is configured to perform one or more second operations in the decoding of the macroblocks. The third processor (i) operates as a slave to the second processor and (ii) is configured to perform one or more third operations in the decoding of the macroblocks.

Abstract: A liquid crystal display includes a liquid crystal panel and a first to nth control substrates (n is an integer which is 2 or greater) which control the liquid crystal panel. When the first control substrate enters an operable status, the first control substrate transmits a readiness signal to the second control substrate which is at a next stage, and when the nth control substrate determines that the nth control substrate receives a readiness signal from a control substrate at a previous stage and is in an operable status, the nth control substrate transmits a readiness signal to the first control substrate, thereby being able to suppress a synchronization failure between the plurality of control substrates which are provided in a liquid crystal display.

Abstract: Embodiments of the present invention provide a chip package structure and a chip packaging method, which is related to the field of electronic technologies, and can protect chips and effectively dissipate heat for chips. The chip package structure includes a substrate, chips, and a heat dissipating lid, where the chips include at least one master chip disposed on the substrate and at least one slave chip disposed on the substrate; the heat dissipating lid is bonded to the slave chip by using a heat conducting material, and the heat dissipating lid covers the at least one slave chip; and the heat dissipating lid includes a heat dissipating window at a position corresponding to the at least one master chip. The embodiments of the present invention are applicable to multi-chip packaging.

Abstract: There is provided an image processing apparatus including a graphics processing unit, a first computer that controls the graphics processing unit, an intermediate image storage unit that stores image data generated by the graphics processing unit, an image input unit that inputs a plurality of image data, an image switching unit that outputs a plurality of any image data among the plurality of image data input to the image input unit, an image combining unit that combines image data using the image data output from the image switching unit and the image data stored in the intermediate image storage unit, an image output unit that outputs the image data combined by the image combing unit, a second computer that controls the image switching unit and the image combining unit, and a connecting unit that connects the first computer and the second computer.

Abstract: A device may have a plurality of displays, such as a high-power display and a low-power display. The low-power display may be used to display various types of information. Some examples of information that may be displayed on the low-power display include personal customizations of the device (e.g., skins, tattoos, text or graphics, etc.), a battery meter, a signal strength meter, the date and time, or any other type of information. In one example, the device has a separate processor that drives the low-power display, so that the low-power display can be used while the device is in sleep mode or off. In another example, an application that runs on the device's regular processor uses the high- and low-power displays cooperatively to display output from an application. The low-power display can be wrapped around the edges and/or corners of the device, to make effective use of the device's surface area.

Abstract: A method of extending a processor system within an integrated circuit (IC) can include executing program code within the processor system implemented within the IC, wherein the IC includes a programmable fabric. The processor system further can be coupled to the programmable fabric. A process can be performed using a process-specific circuit implemented within the programmable fabric in lieu of using the processor system. A result of the process from the process-specific circuit can be made available to the processor system.

Abstract: An asymmetrically scaling multiple GPU graphics system wherein the multiple GPUs are asymmetric, meaning that their rendering capabilities and/or rendering power is not equal. The asymmetric scaling multiple GPU graphics system includes a plurality of GPUs configured to execute graphics instructions from a computer system. A GPU output multiplexer and a controller unit are coupled to the GPUs. The controller unit is configured to control the GPUs and the output multiplexer such that the GPUs cooperatively execute the graphics instructions from the computer system.

Abstract: In an embodiment, a processor that includes multiple cores may implement a power/performance-efficient stop mechanism for power gating. One or more first cores of the multiple cores may have a higher latency stop than one or more second cores of the multiple cores. The power control mechanism may permit continued dispatching of work to the second cores until the first cores have stopped. The power control mechanism may prevent dispatch of additional work once the first cores have stopped, and may power gate the processing in response to the stopping of the second cores. Stopping a core may include one or more of: requesting a context switch from the core or preventing additional work from being dispatched to the core and permitting current work to complete normally. In an embodiment, the processor may be a graphics processing unit (GPU).

Abstract: A software engine for decomposing work to be done into tasks, and distributing the tasks to multiple, independent CPUs for execution is described. The engine utilizes dynamic code generation, with run-time specialization of variables, to achieve high performance. Problems are decomposed according to methods that enhance parallel CPU operation, and provide better opportunities for specialization and optimization of dynamically generated code. A specific application of this engine, a software three dimensional (3D) graphical image renderer, is described.

Abstract: A display apparatus including a display panel for displaying image information and having edges, an edge-roll implementation unit at at least one edge of the display panel, the edge-roll implementation unit being configured to roll the at least one edge, a lighting unit at a surface of the at least one edge at which the edge-roll implementation unit is located, and a control unit for controlling the edge-roll implementation unit.

Abstract: An information processing apparatus includes a first graphics chip having a first drawing processing capacity and being capable of producing a first image signal; a second graphics chip having a second drawing processing capacity higher than the first drawing processing capacity and being capable of producing a second image signal; an output changeover section capable of selectively outputting one of the first or second image signals; an inputting section configured to input a user operation to select one of the first graphics chip or the second graphics chip; and a control section configured to control the output of the output changeover section in response to the inputted user operation.

Abstract: Concurrent display of graphic content on multiple displays is described. A frame of graphic content to be displayed on multiple displays can be written to a single memory location. Previously written graphic content can be read to multiple displays having misaligned synchronization signals and new graphic content can be written to a different memory location concurrently.

Abstract: An internal bus bridge architecture and method is described. Embodiments include a system with multiple bus endpoints coupled to a bus root via a host bus bridge that is internal to at least one bus endpoint. In addition, the bus endpoints are directly coupled to each other. Embodiments are usable with known bus protocols.

Abstract: A system is provided for rendering graphics. The system comprises a plurality or render nodes configured to collectively render a graphics image in response to graphics information supplied from a selected host, at least two hosts operatively coupled to the plurality of render nodes, the at least two hosts comprising the selected host, and logic for selectively configuring the plurality of render nodes to render a graphics image based on content supplied by the selected host.

Abstract: Parallel graphics-processing methods and mobile computing apparatus with parallel graphics-processing capabilities are disclosed. One exemplary embodiment of a mobile computing apparatus includes physical memory, at least two distinct graphics-processing devices, and a bus coupled to the physical memory and the at least two graphics-processing devices. A virtual graphics processing component enables each of at least two graphics-processing operations to be executed, in parallel, by a corresponding one of the at least two distinct graphics-processing devices, which operate in the same memory surface at the same time.

Abstract: Disclosed herein are an apparatus and method for displaying images. The apparatus includes a first image output unit, a second image output unit, an image signal selection unit, and an image display unit. The first image output unit is set to master operation mode, and outputs an image signal to be displayed. The second image output unit is set to slave operation mode, and, if the first image output unit has failed, is switched to master operation mode and then continuously outputs the image signal or a new image signal. The image signal selection unit compares the IP source address of a received master message with previously stored address information, and then selects the image signal that is received from the first image output unit or the second image output unit that has a matching address. The image display unit displays the selected image signal.

Abstract: A display device includes: a pixel array unit with pixel circuits disposed in matrix form, the pixel circuit including a driving transistor, an electro-optic element, a storage-capacitor, and a sampling transistor, with the electro-optic element emitting light by generating a driving current based on information stored in the storage-capacitor at the driving transistor to be applied to the electro-optic element; and a control unit, of which the output stage includes a buffer transistor, to output a pulse signal for driving the pixel array unit from the buffer transistor; wherein the pixel array unit and the control unit are formed with long laser beam irradiation to be scanned in the vertical direction; and with the control unit, buffer transistors for outputting a pulse signal for sampling to an input video signal to each signal line are arrayed in a column in the longitudinal direction of the laser beam irradiation.

Abstract: To power and control multiple different electronic circuit nodes, this document introduces a single-wire multiple-circuit power and control system. Specifically, individually controlled circuit node units are arranged in a series configuration that is driven by a power and control unit located at the head of the series. Each of the individually controlled circuit node units may comprise more than one output circuit that is also individually controllable. The head-end power and control unit provides both electrical power and control signals down a single wire to drive all of the individual circuit node units in the series in a manner that allows each individual circuit node unit to be controlled individually or in assigned groups.

Abstract: To realize effective load distribution and improve the performance in image formation processing, an image processing apparatus includes a first image processing unit configured to perform image processing on a drawing area, a second image processing unit configured to be differentiated from the first image processing unit, a load analysis unit configured to analyze a composition processing load of an object in the drawing area, a rotational angle analysis unit configured to analyze a rotational angle of the object in the drawing area, and a load distribution determination unit configured to determine whether to distribute a part of image formation processing to be applied on the drawing area from the first image processing unit to the second image processing unit based on the analyzed composition processing load of the object and the analyzed rotational angle of the object.

Abstract: An image data processing apparatus includes: a plurality of operational processing circuits each of which is configured to have a variable circuit configuration and to execute operational processing on image data; and a control section that controls each of the operational processing circuits such that each of the operational processing circuits executes one of a plurality of types of operational processing performed on image data in a predetermined order. The control section controls each of the operational processing circuits so that when image data to be newly given to one of the operational processing circuits is interrupted, said one of the operational processing circuits and another one of the operational processing circuits execute operational processing by taking partial charge of the operational processing.

Abstract: A number (n?1) of graphics processing units (GPUs) are serially connected in a sever. When an nth GPU is connected to an (n?1)th GPU of the server, a first control unit of the nth GPU is activated to send a predetermined signal to a master GPU which is connected to a motherboard of the server, to request a slave address for the nth GPU. A second control unit of the master GPU is activated to assign the slave address and send the slave address to the nth GPU, wherein the second control unit of the master GPU detects how many GPUs are connected with each other serially in the server, determines a percentage of operation loads of each of the GPUs to balance the operation loads of the GPUs, and assigns the operation loads between all the GPUs.

Abstract: The disclosed embodiments provide a system that facilitates seamlessly switching between graphics-processing units (GPUs) to drive a display. In one embodiment, the system receives a request to switch from using a first GPU to using a second GPU to drive the display. In response to this request, the system uses a kernel thread which operates in the background to configure the second GPU to prepare the second GPU to drive the display. While the kernel thread is configuring the second GPU, the system continues to drive the display with the first GPU and a user thread continues to execute a window manager which performs operations associated with servicing user requests. When configuration of the second GPU is complete, the system switches the signal source for the display from the first GPU to the second GPU.

Abstract: In a single-instruction-multiple-data (SIMD) processor having multiple lanes, and local memory dedicated to each lane, a method of processing an image is disclosed. The method comprises mapping consecutive rasters of the image to consecutive lanes such that groups of consecutive rasters form image strips, and vertical stacks of strips comprise strip columns. Local memory allocates memory to the image strips. A sequence of functions is processed for execution on the SIMD processor in a pipeline implementation, such that the pipeline loops over portions of the image in multiple iterations, and intermediate data processed during the functions is stored in the local memory. Data associated with the image is traversed by first processing image strips from top to bottom in a left-most strip column, then progressing to each adjacent unprocessed strip column.

Abstract: The present invention provides a method and system for coordinating graphics processing units in a single computing system. A method is disclosed which allows for the construction of a list of shared display modes that may be employed by both of the graphics processing units to render an output in a display device. By creating the list of shared commonly supportable display modes, the output displayed in the display device may advantageously provide a consistent graphical experience persisting through the use of alternate graphics processing units in the system. One method builds a list of shared display modes by compiling a list from a GPU specific base mode list and dynamic display modes acquired from an attached display device. Another method provides the ability to generate graphical output configurations according to a user-selected display mode that persists when alternate graphics processing units in the system are used to generate graphical output.

Abstract: An apparatus for 3D reconstruction based on multiple GPUs and a method thereof are disclosed. The 3D reconstruction apparatus according to the present invention includes a 3D reconstruction apparatus, comprising: a camera configured to generate depth data for 3D space; a first GPU configured to update first TSDF volume data with first depth data generated for a first area and predict a surface point of an object which is present in the space from the first updated TSDF volume data; a second GPU configured to update second TSDF volume data with second depth data generated for a second area and predict a surface point of an object which is present in the space from the second updated TSDF volume data; and a master GPU configured to combine a surface point predicted from the first TSDF volume data and a surface point estimated from the second TSDF volume data.

Abstract: A method of displaying graphics data is described. The method involves accessing the graphics data in a memory subsystem associated with one graphics subsystem. The graphics data is transmitted to a second graphics subsystem, where it is displayed on a monitor coupled to the second graphics subsystem.

Abstract: Systems and methods include an electronic device having multiple GPUs and a GPU power control process that controls switching between a first GPU and a second GPU, such as a high performance GPU. The electronic device may be coupled to an external display by a passive adapter or an active adapter. The GPU power control process may determine if the second GPU is active and switch to the second GPU upon connection of the external display through either the passive adapter or the active adapter. Upon connection of an active adapter, the GPU power control process may use hot plug functionality to determine connection of the external display to the active adapter and provide appropriate switching in response thereto.

Abstract: There is provided a video signal processing method for performing predetermined signal processing on an input video signal to transmit an output video signal in a form of a specified transmission format through a video signal line including invalid bit polarity setting processing to be performed by an invalid bit polarity setting unit, wherein, when there exists an invalid bit having no data corresponding to data making up the input video signal in the specified transmission format of the output video signal, to count the number of low and high levels of gray-level data of the input video signal to compare a numerical size between the number of low levels and the number of high levels for judgment and to set a polarity of the invalid bit based on the judgment result.

Abstract: Embodiments are disclosed for a system and method for parallel processing of video signals. A multi-core processor is used to establish a master-slave relationship between a first processing core and a plurality of individual processing cores. Shared memory is used to store data and control messages. A plurality of individual private memories are associated with each of the individual processing cores; and control logic is used to establish a master-slave protocol for using the plurality of individual cores to process video data. The master processing core is operable to balance the video data processing load among the individual slave processing cores.

Abstract: Multiple graphics processors in a graphics processing system are interconnected in a unidirectional or bidirectional ring topology, allowing pixels to transferred from any one graphics processor to any other graphics processor. The system can automatically identify one or more “master” graphics processors to which one or more monitors are connected and configures the links of the ring such that one or more other graphics processors can deliver pixels to the master graphics processor, facilitating distributed rendering operations. The system can also automatically detect the connections or lack thereof between the graphics processors.

Abstract: A system and method for facilitating increased graphics processing without deadlock. Embodiments of the present invention provide storage for execution unit pipeline results (e.g., texture pipeline results). The storage allows increased processing of multiple threads as a texture unit may be used to store information while corresponding locations of the register file are available for reallocation to other threads. Embodiments further provide for preventing deadlock by limiting the number of requests and ensuring that a set of requests is not issued unless there are resources available to complete each request of the set of requests. Embodiments of the present invention thus provide for deadlock free increased performance.

Abstract: Systems and methods for layering multiple graphics planes on top of a compressed video signal are disclosed herein. A processed video stream is received from a video processing path, wherein the processed video stream comprises a stream of video macroblocks. A composite graphics plane is received from a graphics processing path, wherein the composite graphics plane comprises a set of graphics macroblocks. The composite graphics plane comprises a plurality of layered graphics planes. The composite graphics plane is layered on top of the processed video stream to generate an output video stream. Layering comprises blending a video macroblock from the stream of video macroblocks with a graphics macroblock from the set of graphics macroblocks. By layering one macroblock at time, graphics overlay can occur in real time or faster than real time as the compressed input stream is received.

Abstract: A video processor for executing video processing operations. The video processor includes a host interface for implementing communication between the video processor and a host CPU. A memory interface is included for implementing communication between the video processor and a frame buffer memory. A scalar execution unit is coupled to the host interface and the memory interface and is configured to execute scalar video processing operations. A vector execution unit is coupled to the host interface and the memory interface and is configured to execute vector video processing operations.

Abstract: A main processor collects the edge information and color information of the pixels of a rendering target image using a rendering command, and sends the collected edge information and color information of the pixels to a sub-processor of the succeeding stage. The sub-processor sends the edge information and color information of a left rectangular region to a sub-processor, and also renders a right rectangular region and, upon receiving a process wait signal from the sub-processor, sends the rendering result to the sub-processor. The sub-processor renders the left rectangular region and sends the rendering result to the outside, and also sends, to the outside, the rendering result of the right rectangular region acquired by sending a process wait signal to the sub-processor.

Abstract: The present invention extends to methods, systems, and computer program products for providing asymmetric Graphical Processing Unit (“GPU”) processors in a para-virtualized environment. A virtual GPU (“vGPU”) within a child partition of the para-virtualized environment includes a kernel-mode driver (“KMD”) and a user-mode driver (“UMD”). The KMD includes a plurality of virtual nodes. Each virtual node performs a different type of operation in parallel with other types of operations. The KMD is declared as a multi-engine GPU. The UMD schedules operations for parallel execution on the virtual nodes. A render component within a root partition of the para-virtualized environment executes GPU commands received from the vGPU at the physical GPU. A plurality of memory access channels established between the KMD and the render component communicate GPU commands between a corresponding virtual node at the KMD and the render component.

Abstract: A method for implementing multi context execution on a video processor having a scalar execution unit and a vector execution unit. The method includes allocating a first task to a vector execution unit and allocating a second task to the vector execution unit. The first task is from a first context in the second task is from a second context. The method further includes interleaving a plurality of work packages comprising the first task and the second task to generate a combined work package stream. The combined work package stream is subsequently executed on the vector execution unit.

Abstract: Systems and methods are provided for processing data. The systems and methods include multiple processors that each couple to receive commands and data, where the commands and/or data correspond to frames of video that include multiple pixels. Additionally, an interlink module is coupled to receive processed data corresponding to the frames from each of the multiple processors. The interlink module controls a phase alignment between the processors. The interlink module selects pixels of the frames from the processed data of one of the processors based on a predetermined pixel characteristic and outputs the frames that include the selected pixels.

Abstract: A medical device and a method for displaying medical data by the medical device are disclosed. In one aspect of the disclosure, a method for displaying medical data by a medical device having a display device and one or more processors is disclosed. The method includes monitoring a condition of the display device and determining, at the medical device, whether the display device is in a failure state based on the monitoring, the failure state being indicative of a malfunction of the display device. When the display device is a failure state, the method includes commanding a slave device to display the medical data and providing the medical data from the medical device to the slave device for display by the mobile device.

Abstract: An information processing apparatus includes a first graphics chip having a first drawing processing capacity and being capable of producing a first image signal; a second graphics chip having a second drawing processing capacity higher than the first drawing processing capacity and being capable of producing a second image signal; an output changeover section capable of selectively outputting one of the first or second image signals; an inputting section configured to input a user operation to select one of the first graphics chip or the second graphics chip; and a control section configured to control the output of the output changeover section in response to the inputted user operation.