Abstract: A parallel graphics rendering system is embodied within a host computing system and includes a plurality of graphic processing pipelines (GPPLs) and graphics processing modules. The parallel graphics rendering system supports one or more modes of parallel operation selected from the group consisting of object division, image division, and time division. a plurality of graphic processing pipelines The GPPLs support a parallel graphics rendering process that employs one or more of the object division, image division and/or time division modes of parallel operation in order to execute graphic commands and process graphics data, and render pixel-composited images containing graphics for display on a display device during the run-time of the graphics-based application. An automatic mode control module automatically controls the mode of parallel operation of the parallel graphics rendering system during the run-time of the graphics-based application.

Abstract: One embodiment of the invention sets forth a computing system for performing cryptographic computations. The computing system comprises a central processing unit, a graphics processing unit, and a driver. The central processing requests a cryptographic computation. In response, the driver downloads microcode to perform the cryptographic computation to the graphics processing unit and the graphics processing unit executes microcode. This offloads cryptographic computations from the CPU. As a result, cryptographic computations are performed faster and more efficiently on the GPU, freeing resources on the CPU for other tasks.

Abstract: Systems and techniques for processing sequences of video images involve receiving, on a computer, data corresponding to a sequence of video images detected by an image sensor. The received data is processed using a graphics processor to adjust one or more visual characteristics of the video images corresponding to the received data. The received data can include video data defining pixel values and ancillary data relating to settings on the image sensor. The video data can be processed in accordance with ancillary data to adjust the visual characteristics, which can include filtering the images, blending images, and/or other processing operations.

Abstract: A multi-mode parallel 3-D graphics system having multiple graphics processing pipelines with multiple GPUs supporting a parallel graphics rendering process having time, frame and object division modes of operation, wherein each GPU comprises video memory, a geometry processing subsystem and a pixel processing subsystem, and wherein 3D scene profiling is performed in real-time, and the parallelization state/modes of the system are dynamically controlled to meet graphics application requirements. The multiple modes of parallel graphics rendering use real-time graphics application profiling, and dynamic control over time-division, frame-division, and object-division modes of parallel operation, within the same parallel graphics platform, which can be realized on PC-based computing system architectures.

Abstract: An information processing apparatus performs switching between an exception handler and normal processing. The information processing apparatus includes a processor; a data processing unit that performs particular processing upon receiving a processing request from the processor; an interrupt controller that issues an interrupt request to the processor; and an exception control unit that controls the interrupt controller, wherein the data processing unit is connected with the exception control unit via a dedicated line. The data processing unit includes a notification unit that notifies, via the dedicated line, the exception control unit of status information indicating current status of the data processing unit, and based on the notified status information and setup information set by the processor, the exception control unit judges whether to cause the interrupt controller to issue an interrupt request to execute an exception handler to the processor.

Abstract: A hardware engine control apparatus includes: a plurality of hardware engines (HWEs) connected by a control bus, each of the hardware engines executing a series of different kinds of processing; a host control device that outputs control commands for controlling operation of the HWEs to a subordinate control device; and the subordinate control device that has a register, in which the control commands from the host control device is sequentially set, and outputs the control commands set in the register to the control bus at timing based on a clock signal. The HWEs operate according to the control commands output from the subordinate control device.

Abstract: Multichip graphics processing subsystems include at least three distinct graphics devices (e.g., expansion cards) coupled to a high-speed bus (e.g., a PCI Express bus) and operable in a distributed rendering mode. One of the graphics devices provides pixel data to a display device, and at least one of the other graphics devices transfers the pixel data it generates to another of the devices via the bus to be displayed. Where the high-speed bus provides data transfer lanes, allocation of lanes among the graphics devices can be optimized.

Abstract: A drawing apparatus includes a reception unit, a first holding unit and a drawing processing unit. The reception unit receives graphic information. The first holding unit holds a plurality of first data which is a part of the graphic information received by the reception unit, in association with identification numbers assigned to the first data. The drawing processing unit draws a graphic on the basis of the first data held in the first holding unit. The drawing processing unit uses the plurality of the first data in a same task to draw the graphic. The reception unit records the identification numbers of the first data and a synchronization flag in order of reception. The synchronization flag is set for the first data received first among the plurality of first data processed by the same task in the drawing processing unit.

Abstract: An arithmetic processing unit in a graphics processor alternately executes a process of a first image processing which generates a main image of an application, i.e., a base image and a process of a second image processing which generates a display image eventually displayed by performing a desired processing of the base image. Processing time for the process of the first image processing is designated by a first process executing unit in a main processor which requests execution of the process of the first image processing. Processing time for the process of the second image processing is predetermined. The first process executing unit further determines an address of storage area in a frame buffer storing the base image and, upon determination, transmits to the second process executing unit which requests execution of the process of the second image processing.

Abstract: This invention relates to an information-signal-processing apparatus etc. for performing a series of processing pieces by using plural functional blocks in response to any information signals, in which functions can be easily upgraded through version upgrading of the functional blocks. Control block 110 issues a common command and transmits it to a control block 120 via a control bus 111. Control I/F 120 of the functional block 120 converts this common command into an intra-functional-block command if the common command is the common command related to its own functional block, and supplies the functional section 120e with it. This enables the functional block 120 to operate adaptively in accordance with the common command. When performing upgrade of the functions by the version updating of a predetermined function block, the common command need not be changed.

Abstract: The present invention provides a PoC portable terminal capable of performing edit and information addition on a display screen on which screen information relating to a group telephone conversation is displayed. When a push button of a key operation part 15 is pushed down, a portable terminal 1 becomes a master side. The portable terminal 1 displays pointer information of a marker, which is outputted by a pointing device part 18, on a display part 16. The portable terminal 1 transmits the pointer information from a radio part 14 to a PoC server. The PoC server sends the pointer information from the portable terminal 1 to other users' portable terminals in a group. If the pointer is moved, then the portable terminal 1 as a master side repeats the aforementioned processes.

Abstract: An information processor for information registration, capturing means captures a graphics processing command, and database registering means registers, as information about completed work in the database, information about a series of graphics processing commands concerning completed works out of the captured graphics processing commands. In an information processor for information retrieval, proceeding work detecting means detects a work in progress as a proceeding work based on the captured graphics processing command, and information acquiring means searches a database for the information about the work in progress which has been done before based on the graphics processing command concerning the proceeding work and acquires the information about the work in progress which has been done before.

Abstract: A method of operating a Linear Complementarity Problem (LCP) solver is disclosed, where the LCP solver is characterized by multiple execution units operating in parallel to implement a competent computational method adapted to resolve physics-based LCPs in real-time.

Abstract: An information processing apparatus performs switching between an exception handler and normal processing. The information processing apparatus includes a processor a data processing unit that performs a particular processing upon receiving a processing request from the processor; an interrupt controller that issues an interrupt request to the processor; and an exception control unit that controls the interrupt controller, wherein the data processing unit is connected with the exception control unit via a dedicated line. The data processing unit includes a notification unit that notifies, via the dedicated line, the exception control unit of status information indicating current status of the data processing unit, and based on the notified status information and setup information set by the processor, the exception control unit judges whether to cause the interrupt controller to issue to the processor an interrupt request to execute an exception handler.

Abstract: A method of managing resources is provided. The method includes identifying a resource associated with a processor responsive to an impending transition, and copying the identified resource from a memory associated with the GPU or to the memory associated with the GPU.

Abstract: Multiple graphics processors in a graphics processing system are interconnected in a unidirectional or bidirectional ring topology, allowing pixels to transferred from any one graphics processor to any other graphics processor. The system can automatically identify one or more “master” graphics processors to which one or more monitors are connected and configures the links of the ring such that one or more other graphics processors can deliver pixels to the master graphics processor, facilitating distributed rendering operations. The system can also automatically detect the connections or lack thereof between the graphics processors.

Abstract: The present invention is generally related to the field of image processing, and more specifically to an instruction set for processing images. Vector processing may involve rearranging vector operands in one or more source registers prior to performing vector operations. Typically, rearranging of operands in source registers is done by issuing a plurality of permute instructions that require excessive usage of temporary registers. Furthermore, the permute instructions may cause dependencies between instructions executing in a pipeline, thereby adversely affecting performance. Embodiments of the invention provide a level of muxing between a register file and a vector unit that allow for rearrangement of vector operands in source registers prior to providing the operands to the vector unit, thereby obviating the need for permute instructions.

Abstract: A method for synchronizing two of more graphics processing units. The method includes the steps of determining whether the phase of a first timing signal of a first graphics processing unit and the phase of a second timing signal of a second graphics processing unit are synchronized, and adjusting the frequency of the first timing signal to the frequency of the second timing signal if the first timing signal and the second timing signal are not synchronized.

Abstract: One embodiment of a video processor includes a first media processing device coupled to a first memory and a second media processing device coupled to a second memory. The second media processing device is coupled to the first media processing device via a scalable bus. A software driver configures the media processing devices to provide video processing functionality. The scalable bus carries video data processed by the second media processing device to the first media processing device where the data is combined with video data processed by the first media processing device to produce a processed video frame. The first media processing device transmits the combined video data to a display device. Each media processing device is configured to process separate portions of the video data, thereby enabling the video processor to process video data more quickly than a single-GPU video processor.

Abstract: A computing device includes first and second graphics adapters. A graphics processor of the first graphics adapter acts as a master graphics processor, while a second graphics adapter acts as a slave. The master graphics processor renders graphics to be displayed on multiple separate displays within memory of the first graphics adapter. Images to be displayed on one of the displays are transferred to memory used by the second graphics adapter. The display interface of the second graphics adapter presents images within the memory of the second graphics adapter on at least one of the multiple displays. In this way, device electronics forming the display interface, as well as ports of the second adapter, acting as a slave, may be utilized. In one embodiment, an application creates a single larger image, rendered within the memory of the first graphics adapter. The larger image is then presented as the first and second smaller images on the multiple displays.

Abstract: A distributed resource system comprises a plurality of compute resource units operable to execute graphics applications and generate graphics data, and a plurality of visualization resource units communicatively coupled to the plurality of compute resource units and operable to render pixel data from the graphics data. A first network couples a network compositor to the plurality of visualization resource units. The network compositor is operable to synchronize the received pixel data from the plurality of visualization resource units and receive the pixel data from the visualization resource units and to composite the synchronized pixel data into at least one image. A plurality of display devices, at least one of which is located remotely from the plurality of compute resource units, are coupled to the network compositor and operable to display the at least one image.

Abstract: A PC-based computing system employing a silicon chip having a routing unit, a control unit and profiling unit for parallelizing multiple GPU-driven pipeline cores according to the object division mode of parallelization operation, during a graphics application. The PC-based computing system includes system memory for storing software graphics applications, software drivers and graphics libraries, and an operating system (OS), stored in the system memory, and a central processing unit (CPU), for executing the OS, graphics applications, drivers and graphics libraries. The system also includes a CPU/memory interface module and a CPU bus. The routing unit (i) routes the stream of geometrical data and graphic commands from the graphics application to one or more of the GPU-driven pipeline cores, and (ii) routes pixel data output from one or more of GPU-driven pipeline cores during the composition of frames of pixel data corresponding to final images for display on the display surface.

Abstract: A method and system are disclosed for synchronizing graphics processing events in a multi-GPU computer system. A master GPU renders a first image into a first portion of a master buffer associated with a display interface, and then writes a first predetermined value corresponding to the first image in a first memory unit. A slave GPU renders a second image into a slave buffer, and then transfers the second image to a second portion of the master buffer, and writes a second predetermined value corresponding to the second image in the first memory unit. The first and second predetermined values represent a queuing sequence of the rendered images. The master GPU flips the first image to display only after examining the first predetermined value in the first memory unit, and flips the second image to display only after examining the second predetermined value in the first memory unit.

Abstract: A plurality of sub-processors and a management processor process the first task. A graphic processor unit executes image processing corresponding to the first task processed by the management processor. One of the sub-processors performs a second task different from the first task. An image process related to the first task and originated in the sub-processor is accepted by the graphic processor unit and associated first rendering data is transferred to the graphic processor unit. Meanwhile, when the need arises in the one of the sub-processors for a second image process related to the second task, the one of the sub-processor saves second rendering data for the second image process in a main memory. Subsequently, when the graphic processor unit starts the second image process corresponding to the second task, the second rendering data is transferred from the main memory to a graphic memory.

Abstract: According to one embodiment, an information processing apparatus includes: a plurality of graphics processing units (GPUs) having different characteristics; a memory configured to store information on association between one of the plurality of GPUs and an application program; and a drawing control unit configured to control the GPU associated with the application program to perform drawing processing when the application program is run.

Abstract: A garbage collection system and method in a multiprocessor environment having a shared memory wherein two or more processing units participate in the reclamation of garbage memory objects. The shared memory is divided into regions or heaps and all heaps are dedicated to one of the participating processing units. The processing units generally perform garbage collection operations, i.e., a thread on the heap or heaps that are dedicated to that processing unit. However, the processing units are also allowed to access and modify other memory objects, in other heaps when those objects are referenced by and therefore may be traced back to memory objects within the processing units dedicated heap. The processors are synchronized at rendezvous points to prevent reclamation of used memory objects.

Abstract: An enhanced graphics pipeline is provided that enables common core hardware to perform as different components of the graphics pipeline, programmability of primitives including lines and triangles by a component in the pipeline, and a stream output before or simultaneously with the rendering a graphical display with the data in the pipeline. The programmer does not have to optimize the code, as the common core will balance the load of functions necessary and dynamically allocate those instructions on the common core hardware. The programmer may program primitives using algorithms to simplify all vertex calculations by substituting with topology made with lines and triangles. The programmer takes the calculated output data and can read it before or while it is being rendered. Thus, a programmer has greater flexibility in programming.

Abstract: Multiple Video Graphic Adapters (VGAs) are used to render video data to a common port. In one embodiment, each VGA will render an entire frame of video and provide it to the output port through a switch. The next adjacent frame will be calculated by a separate VGA and provided to an output port through the switch. A voltage adjustment is made to a digital-to-analog converter (DAC) of at least one of the VGAs in order to correlate the video-out voltages being provided by the VGAs. This correlation assures that the color being viewed on the screen is uniform regardless of which VGA is providing the signal. When a VGA is not providing information to the output port, a dummy switch can be selected to provide the video-output of the selected VGA a resistance path which matches the resistance at the video port.

Abstract: A dynamically scheduled parallel graphics processor comprises a spreader that creates graphic objects for processing and assigns and distributes the created objects for processing to one or more execution blocks. Each execution block is coupled to the spreader and receives an assignment for processing a graphics object. The execution block pushes the object through each processing stage by scheduling the processing of the graphics object and executing instruction operations on the graphics object. The dynamically scheduled parallel graphics processor includes one or more fixed function units coupled to the spreader that are configured to execute one or more predetermined operations on a graphics object. An input/output unit is coupled to the spreader, the one or more fixed function units, and the plurality of execution blocks and is configured to provide access to memory external to the dynamically scheduled parallel graphics processor.

Abstract: Systems and methods are provided for processing data. The systems and methods include multiple processors that each couple to receive commands and data, where the commands and/or data correspond to frames of video that include multiple pixels. An interlink module is coupled to receive processed data corresponding to the frames from each of the processors. The interlink module divides a first frame into multiple frame portions by dividing pixels of the first frame using at least one balance point. The interlink module dynamically determines a position for the balance point that minimizes differences between the workload of the processors during processing of commands and/or data of one or more subsequent frames.

Abstract: A multi-chip graphics system includes a master chip and a slave chip coupled by an interlink. The slave chip performs pixel processing in parallel with the master chip, improving the performance of the master chip. In one embodiment, an individual graphics processing unit (GPU) chip includes a normal operational mode, a master mode, and a slave mode to permit an individual GPU chip to be used as individual processor or to be utilized as part of a master/slave pair.

Abstract: A methods and system for utilizing memory interface bandwidth to connect multiple graphics processing units are disclosed. According to one embodiment of the present invention, a first graphics processing unit is configured to allocate a portion of an initial memory interface supported by both the first graphics processing unit and a first video memory for a private connection. This private connection enables this first graphics processing unit to directly communicate with a second graphics processing unit and also access resources of the second graphics processing unit.

Abstract: Multichip graphics processing subsystems include at least three distinct graphics devices (e.g., expansion cards) coupled to a high-speed bus (e.g., a PCI Express bus) and operable in a distributed rendering mode. One of the graphics devices provides pixel data to a display device, and at least one of the other graphics devices transfers the pixel data it generates to another of the devices via the bus to be displayed. Where the high-speed bus provides data transfer lanes, allocation of lanes among the graphics devices can be optimized.

Abstract: Multiple graphics processors in a graphics processing system are interconnected in a unidirectional or bidirectional ring topology, allowing pixels to transferred from any one graphics processor to any other graphics processor. The system can automatically identify one or more “master” graphics processors to which one or more monitors are connected and configures the links of the ring such that one or more other graphics processors can deliver pixels to the master graphics processor, facilitating distributed rendering operations. The system can also automatically detect the connections or lack thereof between the graphics processors.

Abstract: A method for rendering a real-time conformal view of terrestrial body's terrain being traversed by a mobile platform includes storing digital terrain elevation data (DTED) tiles for at least a portion of the terrain of a terrestrial body into an external removable mass data storage device (ERMDSD). The ERMDSD is connectable to an onboard computer system (OCS) comprising embedded mobile platform components that include at least one processing card, at least random access memory (RAM) device and at least one graphics card. The method additionally includes executing a real-time rendering assist application (RTRAA) stored in the processing card to dynamically repackage the DTED tiles into DTED chunks being representative of an area of the terrestrial body to be traversed (ATBT) by the mobile platform. The method further includes executing the RTRAA to create a base mesh of root diamonds representative of the ATBT and tessellate the root diamonds to create a plurality of leaf diamonds.

Abstract: A method and apparatus for performing multisampling-based antialiasing in a system that includes first and second graphics processing unit (GPUs) that reduces the amount of data transferred between the GPUs and improves the efficiency with which such data is transferred. The first GPU renders a first version of a frame using a first multisampling pattern and the second GPU renders a second version of a frame in the second GPU using a second multisampling pattern. The second GPU identifies non-edge pixels in the second version of the frame. The pixels in the first version of the frame are then combined with only those pixels in the second version of the frame that have not been identified as non-edge pixels to generate a combined frame.

Abstract: A multi-chip graphics system includes a master chip and a slave chip coupled by an interlink. The slave chip performs a graphics processing operation in parallel with the master chip, improving the performance of the master chip. In one embodiment, an individual graphics processing unit (GPU) chip includes a normal operational mode, a master mode, and a slave mode to permit an individual GPU chip to be used as individual processor or to be packaged as part of a master/slave pair.

Abstract: A system, method, and computer program product are provided for offloading application tasks in a multi-processor environment. In use, an application is executed utilizing a first processor. Such application performs a plurality of tasks. A driver is provided for determining at least a subset of the tasks. To this end, the subset of tasks may be executed utilizing a second processor.

Abstract: In order to render a primitive, the primitive is subdivided into trapezoids and triangles. The subdivision occurs using scanline-aligned lines. These simple scanline-aligned regions are further subdivided so that the primitive is divided into simple scanline-boundaried trapezoids and other complex scan shapes. The simple scanline-boundaried trapezoids are rasterized. One rasterization method uses a texture map containing slope-based coverage information to edge areas. Gouraud shading may be used to provide the anti-aliasing effects on the scanline-boundaried trapezoids. The simple scanline-boundaried trapezoids may also be rasterized using a software rasterizer. Complex scans are rasterized using a software rasterizer. As data is already rasterized, it is thereby efficiently transferred to the GPU.

Abstract: A system and method are disclosed for improving the remote display of graphics images by the redirection of rendering and the optional use of image data compression. Instead of sending graphics commands over a network and rendering on a remote computer system, graphics commands may be automatically redirected by modified OpenGL functions to local graphics devices without explicit involvement by the graphics application. The modifications to a set of the OpenGL functions on the local system are transparent in the normal mode of rendering and displaying locally. After an image is rendered locally, it may be read back and sent across the network. A standard X Server on the remote system may be sufficient to support this methodology. An X Extension for data decompression on the remote system, however, may allow for more efficient image transmission through the use of image data compression.

Abstract: Multiple graphics processors in a graphics processing system are interconnected in a unidirectional or bidirectional ring topology, allowing pixels to transferred from any one graphics processor to any other graphics processor. The system can automatically identify one or more “master” graphics processors to which one or more monitors are connected and configures the links of the ring such that one or more other graphics processors can deliver pixels to the master graphics processor, facilitating distributed rendering operations. The system can also automatically detect the connections or lack thereof between the graphics processors.

Abstract: One embodiment of a video processor includes a first media processing device coupled to a first memory and a second media processing device coupled to a second memory. The second media processing device is coupled to the first media processing device via a scalable bus. A software driver configures the media processing devices to provide video processing functionality. The scalable bus carries video data processed by the second media processing device to the first media processing device where the data is combined with video data processed by the first media processing device to produce a processed video frame. The first media processing device transmits the combined video data to a display device. Each media processing device is configured to process separate portions of the video data, thereby enabling the video processor to process video data more quickly than a single-GPU video processor.

Abstract: A method for synchronizing two of more graphics processing units. The method includes the steps of determining whether the phase of a first timing signal of a first graphics processing unit and the phase of a second timing signal of a second graphics processing unit are synchronized, and adjusting the frequency of the first timing signal to the frequency of the second timing signal if the first timing signal and the second timing signal are not synchronized.

Abstract: A system and method for providing a dedicated digital interface between multiple graphics devices. The dedicated interface provides a point-to-point connection between each of the multiple graphics devices for the transfer of digital pixel data and synchronization signals. Graphics processing, including combining of portions of a displayable image, is distributed between the multiple graphics devices. One of the multiple graphics devices, a master graphics device converts the combined portions of the displayable image as needed for a specific display device.

Abstract: An integrated circuit includes at least two different types of processors, such as a graphics processor and a video processor. At least one operation is commonly by supported by two different types of processors. For each commonly supported operation that is scheduled, a decision is made to determine which type of processor will be selected to implement the operation.

Abstract: An integrated multimedia system having a multimedia processor is disposed in an integrated circuit having a first host processor system coupled to the multimedia processor and a second local processor disposed within the multimedia processor for controlling the operation of the multimedia processor. A data transfer switch is coupled to the second processor for transferring data to various modules of the processor, at least one of which is a data cache. The data transfer switch transfers data in either direction between the cache and a module within the processor. A data streamer schedules simultaneous data transfers among the various-modules disposed within the multimedia processor in accordance with corresponding channel allocations. An interface unit is coupled to the data streamer and has a plurality of input/output (I/O) device driver units. A plurality of external I/O devices are coupled to the plurality of I/O device driver units via a multiplexer.

Abstract: Disclosed is a processing on a host side and a panel side, thus optimizing a work load of the whole of a system including a graphics chip. Provided is an image display system which comprises a host side for executing an application and a panel side connected to the host side, and displaying an image on the panel side, the host side transferring undeveloped image data to the panel side when an image display is requested of the panel side having a panel memory for developing the image, the panel side developing the image in the panel memory based on the image data transferred from the host side and displaying the image developed in the panel memory on the panel.

Abstract: A guidance information setting apparatus for setting guidance information, comprising: a means for transmitting the unique information about a terminal to a server when the terminal is connected to a network; a means for receiving guidance information or the number (e.g., floor number) corresponding to the guidance information in response to transmitting said unique information to the server; a means for indicating the guidance information for a user based on said received guidance information or the guidance information extracted from a company-wide information based on the number corresponding to the guidance information. The guidance information setting apparatus has a function of turning on or turning off the power to each of the terminals through the server.

Abstract: An integrated circuit includes at least two different types of processors. The integrated circuit includes an integrated host and associated scheduler. At least one operation is supported by two or more different types of processors. The scheduler schedules operations on the different types of processors.

Abstract: A method of assembling a composite image comprising generating three-dimensional data defining a non-stereo image, assigning a first screen portion to a first rendering node, assigning a second screen portion to a second rendering node, rendering, by the first rendering node, a left image portion from the three-dimensional data, rendering, by the second rendering node, a right image portion from the three-dimensional data, and sequentially assembling the left image portion and the right image portion into the composite image is provided.