Abstract: A master-slave network control system and method of operation wherein the master node element has substantially absolute invasive control over functions and capabilities of slave node elements which are logged onto the network and wherein the master node element can exercise latent control over slave node elements when not logged on to the network by controlling reacceptance onto the network in order to promote selected pedagogical and like functions facilitated through networked communication between the master node elements and the slave node elements.

Abstract: In a method of processing figure arrays in a figure processing apparatus, first and second figure arrays are sequentially inputted. A fractionalizing process is selectively performed to divide each of figure elements of the second figure array into a plurality of types of fractions based on presence/non-presence of an overlapping portion between the first and second figure arrays and an array data of the second figure array. The array data indicates an array pitch in each of horizontal and vertical directions and a number of figures in the direction. A figure array of fractions is produced for each type and the produced figure arrays is registered in chain groups which includes a chain group of the first figure array, such that the registered figure arrays have the same array data. Then, a figure operating process is performed to the chain group.

Abstract: A method for controlling physical security of a computer removably coupled to a network wherein a security administrator associated with a server invokes a timer in a client computer and disables the client computer if the computer is not operated within the network with a frequency preset by the security administrator. Techniques are provided in the client computer to inhibit breach of the security of the timer.

Abstract: Synchronization of frame buffer swapping among computer graphics pipelines in a multi-pipeline display system: The pipelines are arranged in a closed daisy chain loop. One pipeline is configured as master; the others are configured as slaves. The master swaps its frame buffers and propagates a master swap signal through the daisy chain. As each slave recognizes the signal, it swaps its own buffers. Each slave propagates a feedback signal back to the master to indicate whether the slave is ready to swap its buffers again. The master waits until the feedback signal indicates that all slaves are ready to swap their buffers before the master will swap its own buffers a second time. The process repeats when the master swaps its buffers a second time.A first synchronization control system is coupled to a first pipeline and has a first daisy chain input and a first daisy chain output.

Abstract: A method of controlling users in a multi-user virtual space and a system for controlling users in a multi-user virtual space. The method includes the steps of: a) connecting lines formed by vertically and equally dividing lines obtained by connecting fixed points, which are center points of fixed objects in a three-dimensional virtual space, to partition the space into sub-spaces; b) calculating the distance between the position of a new user and fixed points of each partitioned sub-space and distributing the new user to the partitioned sub-space having the shortest distance; c) checking and controlling positions, movement and rotation information of each user; and d) repeatedly checking whether there is a new user, and repeating steps b) and c) when there is a new user. Accordingly, the three-dimensional virtual space is partitioned around a fixed point irregularly arranged in the virtual space, and users are assigned to a sub-space and a server according to the distance between the fixed point and the user.

Abstract: A multiple embedded memory frame buffer system includes a master graphics subsystem and a plurality of slave graphics subsystems. Each subsystem includes a frame buffer and a color palette for decompressing data in the frame buffer. The master subsystem further includes a digital to analog converter coupled to receive the decompressed digital data from the palette of each subsystem and outputting analog versions of the digital data to an output device. The system further includes a timing system for determining which outputs of the subsystems are to to be converted by the digital to analog converter at a given time.

Abstract: A processing unit (11) for a printer system. The processing unit (11) is comprised of a master processor (21) and multiple parallel processors (22). The master processor (21) builds a display list and partitions it into sublists, which it distributes to the parallel processors (22). The parallel processors (22) interpret the sublists, thereby rendering the image as bitmapped data. Interpretation of a sublist is performed by reading its operation codes and calling rasterizing primitives represented by the operation codes. (FIG. 3). During execution of a rasterizing primitive, a parallel processor (22) determines whether the next operation code in the sublist will call the same primitive. If so, execution of the current primitive is repeated.

Abstract: In a multiprocessor system, such as a graphics data processing system, a method is disclosed for processing input data in a data processor pipeline. The method includes steps of operating a main thread to store input data in an input buffer until the input buffer is full or the input data ends. If a child thread does not exist, the method creates a child thread and assigns the input buffer to the child thread for processing. If a child thread already exists, the method determines if the child thread can be assigned the input buffer and, if so, then assigns the input buffer to the child thread for processing. If the child thread cannot be assigned the input buffer for processing, the main thread assigns the input buffer to itself for processing in parallel with processing being performed by the child thread. The steps of assigning and determining employ local variables that are accessible to both the main thread and the child thread, and that do not require an operating system call to change and/or test.

Abstract: A method of synchronizing, at a system frame display rate, a first set of frames displayed by a first monitor with a second set of frames by a second monitor, utilizes frame production rates of the two sets of frames to set the system frame display rate. More particularly, the first set of frames are produced at a first frame production rate by a first graphics engine, and the second set of frames are produced at a second frame production rate by a second graphics engine. The first frame production rate and second frame production rate first are compared to determine which frame production rate is slower. The system frame display rate then is set to be no greater than the slower of the two frame production rates.

Abstract: A computer is provided having a bus interface unit which is coupled between a peripheral bus and a dedicated graphics bus. The graphics bus can be linked to the bus interface unit by an AGP, while the peripheral bus can be linked to the bus interface unit by a PCI. Arbitration for the AGP bus can determine when mastership is granted to an AGP master (i.e., graphics accelerator/controller). Until mastership is granted, the AGP target is powered down to a low power state where power consumption within the bus interface unit is minimal. It is not until the AGP master achieves mastership that the graphics target (core logic and memory controller) within the bus interface unit is placed in an operational (fully powered) state. The computer therefore employs a bus interface unit which can be dynamically switched from a high power state to a low power state and vice versa, depending upon accesses to the graphics target.

Abstract: A multiple embedded memory frame buffer system includes a master graphics subsystem and a plurality of slave graphics subsystems. Each subsystem includes a frame buffer and a color palette for decompressing data in the frame buffer. The master subsystem further includes a digital to analog converter coupled to receive the decompressed digital data from the palette of each subsystem and outputting analog versions of the digital data to an output device. The system further includes a timing system for determining which outputs of the subsystems are to to be converted by the digital to analog converter at a given time.

Abstract: A method and apparatus for synchronizing the vertical blanking of multiple frame buffers which may exist on the same computer or separate computers for certain applications including stereo display, virtual reality and video recording, which require such synchronization. To obtain the required synchronization one frame buffer is designation as the master. It provides a signal called FIELD that changes state (0 to 1 or 1 to 0) at the start of every vertical sync event on the master frame buffer. All other frame buffers are set to be slaves. Their timing generators sample the master's FIELD signal. When they detect the master's FIELD signal changing state, they set their own internal timing to match to thereby achieve frame synchronization.

Abstract: A graphic processing system for accomplishing high-speed processing of data conversion processing by effectively utilizing file information of input graphic data to improve processing efficiency of data processing inside blocks, and by optimizing block division.

Abstract: A laptop computer 53 has an LCD display 542 which is used to display images represented by data-reduced video signals supplied to it from a buffer 52 of a video signal processor (50, 51, 52, 56, 57). The processor is connected to the computer 53 via an SCSI interface having a test adaptor 55, a bus 556 and a device controller 56. The computer is not synchronised with the video. It processes a frame of image data to display the frame, and then requests another frame asynchronously with the video sync. The video signal processor (50, 51, 52, 56, 57) responds to the request by disconnecting from the bus (556) processing the next frame, and reconnecting to the bus to provide the frame synchronously with video frame sync F. Thus the computer becomes effectively synchronised to the video.

Abstract: An improved graphical manipulation technique for a home communication terminal (HCT) includes a linked-list of commands controlling various video operations in an application specific integrated circuit (ASIC). After each command has been implemented by the ASIC, the ASIC proceeds to the next command without interrupting a host processor. Accordingly, the linked-list eliminates the need of the host processor to continually process interrupts at the completion of each instruction. The linked-list command structure aids in intensive video operations including bit block transfers, video capture, and video display.

Abstract: An image processing apparatus is disclosed which is connected to external machines for inputting data therefrom to a plurality of image memories and outputting data from the plurality of image memories thereto. The image processing apparatus includes a plurality of memory access controllers connected to the plurality of image memories, and a control device for selecting, a first mode for the plurality of memory access controllers to access the image memories separately, or a second mode for a master controller, which is one of the memory access controllers, to access the plurality of image memories as one image memory space so a to control the plurality of memory access controllers.

Abstract: A computer network system repetitively distributes messages including uniquely identified blocks of real time data containing a current data image over a broadcast communications network to all real time stations for storage of each repetition of each entire block of data directly in station memory at a unique address space assigned to that uniquely identified block of data. The real time stations receive the blocks of data and alternatively receive other messages from the real time stations. The other messages have a recognized standard protocol, such as the TCP/IP or UDP/IP protocol of the Internet Protocol Suite.

Abstract: A remote operation apparatus comprises a MA term having a video display, an operation data generator, and a parameter data generator and at least a slave term, coupled to the MA term through at least a network, including operation data receiver, a video data generator and a display, a screen parameter receiver, and a video data acquiring portion. The operation data generator generates and transmits operation data to the video data generator of the slave term to generate and display video data. The screen parameter data generator generates screen parameter data indicating required video data and quality and transmits it to a video data acquiring portion acquiring the generated video data in the required region and quality and transmits it to the display of the MA term. A resource data of the networks and interface ckts is held by the slave term and is transmitted to the screen parameter data generator to utilize the resource data for generation of the screen parameter.

Abstract: A process control method for a multiprocessing computer system is performed by executing a display process to display an initial state of general processes on a display terminal of the multiprocessing computer system. The general processes are then executed under the control of a control process. The display process transmits a state information inquiring message to the control process. A confirmation message indicating reception of the state information inquiring message is transmitted to the display process by the control process when the control process receives the state information inquiring message. A process state request message is transmitted to the general processes by the control process, so that only the general processes that are operating normally receive the process state request message. An answer message is transmitted to the control process by each of the general processes that are operating normally.

Abstract: A system for communicating data between two control units each capable of executing independent operations and having a memory for operations, the system is provided with a new data generator on one control unit. The new data generator generates new data for a selected item of the other control unit. The new data is combined with address data corresponding to the selected item of the memory of the other control unit to generate transmission data. The transmission data is sent to the other control unit and the new item data is written on the memory at the address specified by the transmission data. The data communication system communicates between the two control units data for a first kind of operations and data for a second kind of operations selectively. The first kind data is communicated repeatedly while the second kind data is communicated a single time.