Abstract: One embodiment of the present invention sets forth a graphics pipeline architecture for optimizing graphics rendering efficiency by advancing the Z-test operation prior to shading operations whenever possible, as determined by an upstream pipeline configuration unit. Each processing engine within the graphics pipeline maintains independent state for both early Z-mode and late Z-mode operations and also may maintain state common to both modes. The processing engines receive work transactions that include a Z-mode flag indicating whether the work transaction should be processed in late Z-mode or early Z-mode. The Z-mode flag is also used to dynamically route any resulting outbound data, so that the appropriate data flow for either early Z or late Z processing is dynamically constructed for each work transaction.

Abstract: An apparatus includes a plurality of image processing circuits. Each image processing circuit generates an image frame corresponding to a single large surface. The first image processing circuit provides a portion of the generated image frame for a first display or plurality of displays and provides a remaining portion of the image frame to the remaining image processing circuits. The next image processing circuits provides the remaining portion of the image frame for the next plurality of displays.

Abstract: A data processing device connected with a data supply device for performing predetermined data processing includes: a communication control unit for controlling communication with the data supply device; a data processing unit for performing the data processing based on input data received from the data supply device; and a device control unit for performing predetermined processing in correspondence with command data received from the data supply device based on the command data. The communication control unit receives the input data and the command data each of which is contained in a packet having a common fixed length from the data supply device. When an identification part at a predetermined position in the reception packet received from the data supply device is set at a predetermined command identification value indicating the command data, the communication control unit supplies data contained in the reception packet to the device control unit.

Abstract: Registers 32a-32d hold data for pixels interleaved. An operator 34 reads the pixel data from the registers and processes the pixel data in accordance with a program code. The operator 34 writes the result of the process back to the registers via a cache 38 or writes it in a memory. Program counters PC0-PC3 provided in association with the number of pixels interleaved store the addresses of instructions in a program for the respective pixels. An instruction loader 76 alternately reads from the program counters. An incrementer 74 increments the count of the program counters. The instructions in the program for the pixels are alternately loaded and interleaved on a pixel by pixel basis, before being supplied to the operator 34 and the like.

Abstract: Some embodiments provide a method of performing several shading operations for a graphic object in a scene that is displayed on a device. The device includes several processing units. The method receives a set of criteria that can define a set of parameters that relate to the shading operations. The method determines an allocation of the shading operations to the processing units based on the received criteria. The method allocates the shading operations to the processing units based on the determined allocations. The method renders the graphic object based on several instructions that comprise the shading operations. In some embodiments, the set of criteria is received during execution of the operations.

Abstract: Techniques for supporting both 2-D and 3-D graphics are described. A graphics processing unit (GPU) may perform 3-D graphics processing in accordance with a 3-D graphics pipeline to render 3-D images and may also perform 2-D graphics processing in accordance with a 2-D graphics pipeline to render 2-D images. Each stage of the 2-D graphics pipeline may be mapped to at least one stage of the 3-D graphics pipeline. For example, a clipping, masking and scissoring stage in 2-D graphics may be mapped to a depth test stage in 3-D graphics. Coverage values for pixels within paths in 2-D graphics may be determined using rasterization and depth test stages in 3-D graphics. A paint generation stage and an image interpolation stage in 2-D graphics may be mapped to a fragment shader stage in 3-D graphics. A blending stage in 2-D graphics may be mapped to a blending stage in 3-D graphics.

Abstract: A technique for encoding and decoding video information uses a plurality of video processing modules (VPMs), whereby each video processing module is dedicated to a particular video processing function, such as filtering, matrix arithmetic operations, and the like. Information is transferred between the video processing modules using a set of first-in first-out (FIFO) buffers. For example, to transfer pixel information from a first VPM to a second VPM, the first VPM stores the pixel information at the head of a FIFO buffer, while the second VPM retrieves information from the tail of the FIFO buffer. The FIFO buffer thus permits transfer of information between the VPMs without storage of the information to a cache or other techniques that can reduce video processing speed.

Abstract: This disclosure is directed to improving a user experience when operating a mobile device that includes a display. In one example, a mobile device is configured to render an image via a display of the mobile device. The image includes one or more properties. The mobile device may identify, using one or more sensors, one or more characteristics of a relationship between the mobile device and an optical environment of the mobile device. One or more indications of the identified characteristics may be provided to a graphics processing pipeline of the mobile device configured to present images via the display. The graphics processing pipeline may modify the one or more properties of the image to reflect the identified characteristic.

Abstract: A graphics engine and related method of operation are disclosed in which a pixel distributor distributes pixel data across a plurality of pixel shaders using a first approach when the presence of one or more rendering features is indicated, else using a second approach different from the first approach.

Abstract: In one aspect, the invention provides improvements in a digital data processor of the type that renders a three-dimensional (3D) volume image data into a two-dimensional (2D) image suitable for display. The improvements include a graphics processing unit (GPU) that comprises a plurality of programmable vertex shaders that are coupled to a plurality of programmable pixel shaders, where one or more of the vertex and pixel shaders are adapted to determine intensities of a plurality of pixels in the 2D image as an iterative function of intensities of sample points in the 3D image through which a plurality viewing rays associated with those pixels are passed. The pixel shaders compute, for each ray, multiple iteration steps of the iterative function prior to computing respective steps for a subsequent ray.

Abstract: A video and graphics system processes video data including both analog video, e.g., NTSC/PAL/SECAM/S-video, and digital video, e.g., MPEG-2 video in SDTV or HDTV format. The video and graphics system includes a video decoder, which is capable of concurrently decoding multiple SLICEs of MPEG-2 video data. The video decoder includes multiple row decoding engines for decoding the MPEG-2 video data. Each row decoding engine concurrently decodes two or more rows of the MPEG-2 video data. The row decoding engines have a pipelined architecture for concurrently decoding multiple rows of MPEG-2 video data. The video decoder may be integrated on an integrated circuit chip with other video and graphics system components such as transport processors for receiving one or more compressed data streams and for extracting video data, and a video compositor for blending processed video data with graphics.

Abstract: The present invention contemplates a variety of improved methods and systems for distributing different processing aspects of layered application, and distributing a processing pipeline among a variety of different computer devices. The system uses multiple devices resources to speed up or enhance applications. In one embodiment, application layers can be distributed among different devices for execution or rendering. The teaching further expands on this distribution of processing aspects by considering a processing pipeline such as that found in a graphics processing unit (GPU), where execution of parallelized operations and/or different stages of the processing pipeline can be distributed among different devices. There are many suitable ways of describing, characterizing and implementing the methods and systems contemplated herein.

Abstract: Described are a video graphics system, graphics processor, and methods for rendering three-dimensional objects. A buffer is partitioned into tiles of pixels. Each pixel of each tile includes at least one sample. A primitive is received and determined to cover fully one of the tiles. A section of the primitive that maps to the fully covered tile is tested to determine if every sample within the fully covered tile is to undergo the same stencil operation. The stencil operation is performed on the fully covered tile in the buffer if every sample within the fully covered tile is to undergo the same stencil operation.

Abstract: A processing unit includes multiple execution pipelines, each of which is coupled to a first input section for receiving input data for pixel processing and a second input section for receiving input data for vertex processing and to a first output section for storing processed pixel data and a second output section for storing processed vertex data. The processed vertex data is rasterized and scan converted into pixel data that is used as the input data for pixel processing. The processed pixel data is output to a raster analyzer.

Abstract: A graphic system having a central processing unit; a system memory coupled to the central processing unit; a display unit provided with a corresponding screen; a graphic module coupled to and controlled by the central processing unit to render an image on the screen of the display unit, the graphic module including a fragment graphic module having a depth test buffer for storing a current depth value; a depth test stage coupled to the depth test buffer for comparing the current depth value with a depth coordinate associated with an incoming fragment and defining a resulting fragment; a test stage for testing the resulting fragment and defining a retained fragment; a buffer writing stage operatively associated with the test stage for receiving the retained fragment, the buffer writing stage coupled to the depth test buffer for updating the current depth value with a depth value of the retained fragment.

Abstract: Methods and apparatus for subdividing a shader program into regions or “phases” of instructions identifiable by phase identifiers (IDs) inserted into the shader program are provided. The phase IDs may be used to constrain execution of the shader program to prohibit texture fetches in later phases from being executed before a texture fetch in a current phase has completed. Other operations (e.g., math operations) within the current phase, however, may be allowed to execute while waiting for the current phase texture fetch to complete.

Abstract: A floating point rasterization and frame buffer in a computer system graphics program. The rasterization, fog, lighting, texturing, blending, and antialiasing processes operate on floating point values. In one embodiment, a 16-bit floating point format consisting of one sign bit, ten mantissa bits, and five exponent bits (s10e5), is used to optimize the range and precision afforded by the 16 available bits of information. In other embodiments, the floating point format can be defined in the manner preferred in order to achieve a desired range and precision of the data stored in the frame buffer. The final floating point values corresponding to pixel attributes are stored in a frame buffer and eventually read and drawn for display. The graphics program can operate directly on the data in the frame buffer without losing any of the desired range and precision of the data.

Abstract: The present disclosure is directed to novel methods and apparatus for managing or performing the dynamic allocation or reallocation of processing resources among a vertex shader, a geometry shader, and pixel shader of a graphics processing unit. In one embodiment a method for graphics processing comprises assigning at least one execution unit to each of a plurality of shader units, the plurality of shader units comprising a vertex shader, a geometry shader, and a pixel shader, wherein an execution unit assigned to a given shader unit performs processing tasks for only that shader unit, determining that one of the plurality of shader units is bottlenecked, and reassigning at least one execution unit from a non-bottlenecked shader unit to the shader unit determined to be bottlenecked.

Abstract: In accordance with one embodiment a graphics processing system is configured to switch from a processing of a primitive associated with a first context to a processing of a command list associated with a second context where the primitive includes a plurality of regions. The system includes a plurality of processing modules and at least one module of the plurality of processing modules is configured to receive a request to switch to the second context.

Abstract: An example embodiment disclosed is a system for automated model extraction of documents containing flow diagrams. An extractor is configured to extract from the flow diagrams flow graphs. The extractor further extracts nodes and edges, and relational, geometric and textual features for the extracted nodes and edges. A classifier is configured to recognize process semantics based on the extracted nodes and edges, and the relational, geometric and textual features of the extracted nodes and edges. A process modeling language code is generated based on the recognized process semantics. Rules to recognize patterns in process diagrams may be determined using supervised learning and/or unsupervised learning. During supervised learning, an expert labels example flow diagrams so that a classifier can derive the classification rules. During unsupervised learning flow diagrams are clustered based on relational, geometric and textual features of nodes and edges.

Abstract: A system, method and computer program product are provided for packing graphics attributes. In use, a plurality of graphics attributes is identified. Such graphics attributes are packed, such that the packed graphics attributes are capable of being processed utilizing a pixel shader.

Abstract: A parallel graphics rendering system is embodied within a host computing system and includes a plurality of graphic processing pipelines (GPPLs) and graphics processing modules. The parallel graphics rendering system supports one or more modes of parallel operation selected from the group consisting of object division, image division, and time division. a plurality of graphic processing pipelines The GPPLs support a parallel graphics rendering process that employs one or more of the object division, image division and/or time division modes of parallel operation in order to execute graphic commands and process graphics data, and render pixel-composited images containing graphics for display on a display device during the run-time of the graphics-based application. An automatic mode control module automatically controls the mode of parallel operation of the parallel graphics rendering system during the run-time of the graphics-based application.

Abstract: A game console system capable of parallelizing the operation of multiple graphics processing units (GPUs) supported on game console board, using a graphics hub device, and a multi-mode parallel graphics rendering subsystem supporting multiple modes of parallel operation and having software and hardware implemented components. The game console system includes (i) CPU memory space for storing one or more graphics-based applications, (ii) one or more CPUs for executing the graphics-based applications, (iii) a plurality of graphic processing pipelines (GPPLs), implemented using the GPUs, and (iv) an automatic mode control module. During the run-time of the graphics-based application, the automatic mode control module automatically controls the mode of parallel operation of the multi-mode parallel graphics rendering subsystem so that the GPUs are driven in a parallelized manner.

Abstract: A processing pipeline employs one or more bypass caches to allow a transaction that is dependent on the results of a prior transaction to be processed before the prior transaction has completed processing. Each bypass cache is coupled to the input and the output of one of the sections of the processing pipeline so that results of a transaction from that section can be written into or read from the bypass cache as soon as that transaction has been completely processed through that section. With such a configuration, more transactions can be processed by the processing pipeline in a shorter amount of time. This is especially true for very deep pipelines.

Abstract: A functional unit is added to a graphics processor to provide direct support for double-precision arithmetic, in addition to the single-precision functional units used for rendering. The double-precision functional unit can execute a number of different operations, including fused multiply-add, on double-precision inputs using data paths and/or logic circuits that are at least double-precision width. The double-precision and single-precision functional units can be controlled by a shared instruction issue circuit, and the number of copies of the double-precision functional unit included in a core can be less than the number of copies of the single-precision functional units, thereby reducing the effect of adding support for double-precision on chip area.

Abstract: One embodiment of the present invention sets forth a technique for performing dual depth peeling, which is useful for order-independent transparency blending. Multiple rendering passes are performed on a graphics scene. After each rendering pass, the front-most and back-most layer of pixels are peeled away by computing a reference window. In subsequent rendering passes, only pixels within the reference window survive depth sorting. In each subsequent rendering pass, the reference window is narrowed by the front most and back most surviving pixels. By performing depth peeling in two directions simultaneously, the number of rendering passes needed to generate a completed graphics image is reduced from L to 1+L/2, which results in improved rendering performance.

Abstract: A 3D graphics pipeline includes a prefetch mechanism that feeds a cache of depth tiles. The prefetch mechanism may be predictive, using triangle geometry information from previous pipeline stages to pre-charge the cache, thereby allowing for an increase in memory bandwidth efficiency. A z-value compression technique may be optionally utilized to allow for a further reduction in power consumption and memory bandwidth.

Abstract: A multithreaded rendering software pipeline architecture dynamically reallocates regions of an image space to raster threads based upon performance data collected by the raster threads. The reallocation of the regions typically includes resizing the regions assigned to particular raster threads and/or reassigning regions to different raster threads to better balance the relative workloads of the raster threads.

Abstract: A multi-mode parallel 3-D graphics system having multiple graphics processing pipelines with multiple GPUs supporting a parallel graphics rendering process having time, frame and object division modes of operation, wherein each GPU comprises video memory, a geometry processing subsystem and a pixel processing subsystem, and wherein 3D scene profiling is performed in real-time, and the parallelization state/modes of the system are dynamically controlled to meet graphics application requirements. The multiple modes of parallel graphics rendering use real-time graphics application profiling, and dynamic control over time-division, frame-division, and object-division modes of parallel operation, within the same parallel graphics platform, which can be realized on PC-based computing system architectures.

Abstract: A method for multiple queue output buffering in a raster stage of a graphics processor. The method includes receiving a graphics primitive for rasterization in a raster stage of a graphics processor. The graphics primitive is rasterized at a first level to generate a plurality of tiles of pixels related to the graphics primitive. Each tile is then rasterized to determine related sub-portions of each tile. The related sub-portions are transferred to a plurality of output queues. The related sub-portions are subsequently output on a per queue basis and on a per clock cycle basis.

Abstract: Systems and methods for assembling pixel shader program threads for execution based on resource limitations of a multithreaded processor may improve processing throughput. Pixels to be processed by the pixel shader program are assembled into a launch group for processing by the multithreaded processor as multiple shader program threads. The pixels are assembled based on parameter storage resource limitations of the multithreaded processor so that common parameters shared by multiple pixels are not stored separately for each pixel. Therefore, the limited parameter storage resources are efficiently used, allowing more shader program threads to execute simultaneously.

Abstract: Apparatuses and methods are presented for a hierarchical processor. The processor comprises, at a first level of hierarchy, a plurality of similarly structured first level components, wherein each of the plurality of similarly structured first level components includes at least one combined function module capable of performing multiple classes of graphics operations, each of the multiple classes of graphics operations being associated with a different stage of graphics processing.

Abstract: The time needed for back-end work can be estimated without actually doing the back-end work. Front-end counters record information for a cost model and heuristics may be used for when to split a tile and ordering work dispatch for cores. A special rasterizer discards triangles and fragments outside a sub-tile.

Abstract: A multithreaded rendering software pipeline architecture utilizes a rolling texture context data structure to store multiple texture contexts that are associated with different textures that are being processed in the software pipeline. Each texture context stores state data for a particular texture, and facilitates the access to texture data by multiple, parallel stages in a software pipeline. In addition, texture contexts are capable of being “rolled”, or copied to enable different stages of a rendering pipeline that require different state data for a particular texture to separately access the texture data independently from one another, and without the necessity for stalling the pipeline to ensure synchronization of shared texture data among the stages of the pipeline.

Abstract: The present disclosure provides embodiments of guard band clipping systems and methods. One guard band clipping system embodiment, among others, includes a vertex processor configured to convert transformed vertex data to integer screen space data and pass the transformed vertex data downstream in a graphics hardware pipeline, and a guard band clipping module coupled to the vertex processor and a guard band arithmetic logic unit coupled to the guard band clipping module, the guard band clipping module configured to determine whether a primitive corresponding to the transformed vertex data is to be clipped and, based on that determination, forward the primitive to the guard band arithmetic logic unit to perform guard band clipping.

Abstract: In accordance with at least some embodiments of the present disclosure, a processor for performing stereo matching of a first image and a second image is described. The processor may include a first pipeline stage configured to generate data costs associated with a first tile selected from the first image, wherein the data costs is generated based on pixels in the first tile and corresponding pixels in the second image. The processor may include a second pipeline stage configured to generate disparity values associated with the first tile and an outbound message from the first tile to one of neighboring tiles in the first image, wherein the disparity values and the outbound message are generated based on the data costs and inbound messages from the neighboring tiles to the first tile.

Abstract: The edge evaluation technique, in accordance with one embodiment of the present technology, includes determining a number of edges of a given primitive to be evaluated. The technique also includes sequencing evaluation of a first edge by a first edge evaluation circuit and a second edge by a second edge evaluation circuit during a first clock cycle. The technique further includes sequencing evaluation of a third edge by the first edge evaluation circuit and a fourth edge by the second edge evaluation circuit during a second clock cycle if three or more edges are to be evaluated.

Abstract: A method detects border tiles or border pixels of a primitive corresponding to an object to be displayed on a display screen. The detecting includes: calculating the number of border tiles or pixels covered by an edge of the primitive; identifying a plurality of vertices that divide the edge in a plurality of segments of equal length; calculating coordinates of the vertices; and associating a tile or pixel with the coordinates of each vertex. The number of vertices for the edge is greater than or equal to the number of border tiles or pixels.

Abstract: A method includes performing a task in response to a request of a secondary user interface of a secondary device. The method also includes calculating a utilization of a graphics processing unit of a machine based on the task performed by the graphics processing unit. The method further includes determining the utilization, through a processor, based on a comparison of a consumption of a computing resource of the graphics processing unit and a sum of the computing resource available. The method furthermore includes performing another task in response to the request of another secondary user interface of another secondary device. The method furthermore includes calculating another utilization of another graphics processing unit based on the another task performed by the another graphics processing unit. The method furthermore includes determining the another utilization based on the comparison of a consumption of the computing resource of the another graphics processing unit.

Abstract: Multichip graphics processing subsystems include at least three distinct graphics devices (e.g., expansion cards) coupled to a high-speed bus (e.g., a PCI Express bus) and operable in a distributed rendering mode. One of the graphics devices provides pixel data to a display device, and at least one of the other graphics devices transfers the pixel data it generates to another of the devices via the bus to be displayed. Where the high-speed bus provides data transfer lanes, allocation of lanes among the graphics devices can be optimized.

Abstract: A drawing apparatus includes a reception unit, a first holding unit and a drawing processing unit. The reception unit receives graphic information. The first holding unit holds a plurality of first data which is a part of the graphic information received by the reception unit, in association with identification numbers assigned to the first data. The drawing processing unit draws a graphic on the basis of the first data held in the first holding unit. The drawing processing unit uses the plurality of the first data in a same task to draw the graphic. The reception unit records the identification numbers of the first data and a synchronization flag in order of reception. The synchronization flag is set for the first data received first among the plurality of first data processed by the same task in the drawing processing unit.

Abstract: An apparatus and method to dynamically regulate system bandwidth in a graphics system includes receiving vertex data from an application by way of an application programming interface. The rate that the vertex data is received from the application is then determined. In the event the rate is greater than a selected threshold, the graphics system is configured to operate in immediate mode, wherein vertex data is rendered immediately upon reception. In the event the rate is less than the selected threshold, the graphics system is configured to operate in retained mode, wherein vertex data is stored prior to being rendered. The apparatus and method switches between each of the modes on-the-fly in a manner that is transparent to the application.

Abstract: An enhanced graphics pipeline is provided that enables common core hardware to perform as different components of the graphics pipeline, programmability of primitives including lines and triangles by a component in the pipeline, and a stream output before or simultaneously with the rendering a graphical display with the data in the pipeline. The programmer does not have to optimize the code, as the common core will balance the load of functions necessary and dynamically allocate those instructions on the common core hardware. The programmer may program primitives using algorithms to simplify all vertex calculations by substituting with topology made with lines and triangles. The programmer takes the calculated output data and can read it before or while it is being rendered. Thus, a programmer has greater flexibility in programming.

Abstract: An apparatus and method for rasterizing a primitive in a graphics system is disclosed in one example of the invention as including scanning a first row of tiles, one tile at a time, starting from a first point and scanning in a first direction. Immediately after scanning the first row of tiles, the method includes moving from the first point to a second point in an orthogonal direction relative to the first row. Immediately after moving from the first point to the second point, the method includes scanning a second row of tiles, one tile at a time, starting from the second point and scanning in the first direction. By scanning rows in the same direction immediately prior to and after moving from one row to another, cache utilization is improved.

Abstract: This disclosure describes a graphics processing unit (GPU) pipeline that uses one or more shared arithmetic logic units (ALUs). In order to facilitate such sharing of ALUs, the stages of the disclosed GPU pipeline may be rearranged relative to conventional GPU pipelines. In addition, by rearranging the stages of the GPU pipeline, efficiencies may be achieved in the image processing. Unlike conventional GPU pipelines, for example, an attribute gradient setup stage can be located much later in the pipeline, and the attribute interpolator stage may immediately follow the attribute gradient setup stage. This allows sharing of an ALU by the attribute gradient setup and attribute interpolator stages. Several other techniques and features for the GPU pipeline are also described, which may improve performance and possibly achieve additional processing efficiencies.

Abstract: A command parser in a GPU is configured to schedule execution of received commands and includes a first input coupled to a scheduler. The first command parser input is configured to communicate bus interface commands to the command parser for execution. A second command parser input is coupled to a controller that receives ring buffer commands from the scheduler in association with a new or previously-partially executed ring buffer, or context, which are executed by the command parser. A third command parser input coupled to a command DMA component that receives DMA commands from the controller that are also contained in the new or previously-partially executed ring buffer, which are forwarded to the command parser for execution. The command parser forwards data corresponding to commands received on one or more the first, second, and third inputs via one or more outputs.

Abstract: An arithmetic processing unit in a graphics processor alternately executes a process of a first image processing which generates a main image of an application, i.e., a base image and a process of a second image processing which generates a display image eventually displayed by performing a desired processing of the base image. Processing time for the process of the first image processing is designated by a first process executing unit in a main processor which requests execution of the process of the first image processing. Processing time for the process of the second image processing is predetermined. The first process executing unit further determines an address of storage area in a frame buffer storing the base image and, upon determination, transmits to the second process executing unit which requests execution of the process of the second image processing.

Abstract: Circuits, methods, and apparatus that provide texture caches and related circuits that store and retrieve texels in an efficient manner. One such texture circuit can provide a configurable number of texel quads for a configurable number of pixels. For bilinear filtering, texels for a comparatively greater number of pixels can be retrieved. For trilinear filtering, texels in a first LOD are retrieved for a number of pixels during a first clock cycle, during a second clock cycle, texels in a second LOD are retrieved. When aniso filtering is needed, a greater number of texels can be retrieved for a comparatively lower number of pixels.

Abstract: Systems and methods are disclosed for performing multiple processing of data in a network. In one embodiment, the network comprises a first display pipeline that is formed in real time from a plurality of possible display pipelines and that performs at least a first processing step on received data. A buffer stores the processed data and a second display pipeline that is formed in real time from a plurality of possible display pipelines performs at least a second processing step on stored data.

Abstract: One embodiment of the present invention sets forth a technique for improving the flexibility and programmability of a graphics pipeline by enabling full access to integer texture maps within a graphics processing unit (GPU). A new mechanism for loading and unloading integer texture images is disclosed that enables the shader units within the GPU to have full access to integer values stored within an integer image buffer in a GPU local memory. New integer formats are added to the graphics API that indicate that data should be loaded and processed without the prior art conversion to a floating-point representation, thereby enabling the use of these new integer data types.