Abstract: In at least some embodiments, an apparatus includes a hardware accelerator subsystem with a pipeline. The hardware accelerator subsystem is configured to perform error recovery operations in response to a bit stream error. The error recovery operations comprise a pipe-down process to completely decode a data block that is already in the pipeline, an overwrite process to overwrite commands in the hardware accelerator subsystem with null operations (NOPs) once the pipe-down process is complete, and a pipe-up process to restart decoding operations of the pipeline at a next synchronization point.

Abstract: A rendering method and apparatus capable of allowing power to be efficiently used and rendering to be quickly completed. The rendering method includes: performing texture mapping of a transparency value of a fragment; testing whether or not the fragment can be expressed as a pixel after the performing of the texture mapping; and selectively performing texture mapping of the color value of the fragment according to the test result.

Abstract: A video processing system, method, and computer program product are provided for encrypting communications between a plurality of graphics processors. A first graphics processor is provided. Additionally, a second graphics processor in communication with the first graphics processor is provided for collaboratively processing video data. Furthermore, such communication is encrypted.

Abstract: A method of managing multiple contexts for a single mode display includes receiving a plurality of tasks from one or more applications and determining respective contexts for each task, each context having a range of memory addresses.

Abstract: Systems and methods are disclosed for video processing modules. More specifically a network is disclosed for processing data. The network comprises a register DMA controller adapted to support register access and at least one node adapted to the data. At least one link communicates with the node, and is adapted to transmit data and at least one network module communicates with at least the link, and is adapted to route data to at least the link.

Abstract: Included are embodiments of systems and methods for processing metacommands. In at least one exemplary embodiment a Graphics Processing Unit (GPU) includes a metaprocessor configured to process at least one context register, the metaprocessor including context management logic and a metaprocessor control register block coupled to the metaprocessor, the metaprocessor control register block configured to receive metaprocessor configuration data, the metaprocessor control register block further configured to define metacommand execution logic block behavior. Some embodiments include a Bus Interface Unit (BIU) configured to provide the access from a system processor to the metaprocessor and a GPU command stream processor configured to fetch a current context command stream and send commands for execution to a GPU pipeline and metaprocessor.

Abstract: Example embodiments of the present invention include systems and methods for the efficient rendering of multiple light sources, each controlled individually, in a single pass. An example embodiment encodes the light sources in a texture map, such as DXT. Each channel of the multi-channel texture map encodes data associated with a light source. The pixel shader then renders multiple light sources according to the multiple channels of the texture. Additionally, the pixel shader may render multiple textures, and thus render an even greater number of individual light sources. In a further embodiment, the rendering of a plurality of individually controlled light sources is accomplished in a single pass.

Abstract: A three-dimensional computer graphics rendering system allows a tile-based rendering system to operate with a reduced amount of storage required for tiled screen space geometry by using an untransformed display list to represent the screen's geometry.

Abstract: Methods and apparatus for utilizing coefficient compression in graphics decoding are provided. In one example, a computer processing unit (CPU) is interfaced with a graphic processing unit (GPU) where the CPU extracts coefficients and passes compressed coefficient data, preferably in uniformly sized data packets, to the GPU for decoding and coefficient processing. Preferably the extracted coefficients are inverse transform (iT) coefficients and CPU includes an encoder control component configured to adaptively select a coefficient encoding process for performing the iT coefficient data compression based on the data content of the iT coefficients such that data packets are generated that include data that indentifies the selected coefficient encoding process used for encoding the compressed iT coefficient data contained in the data packet.

Abstract: Systems and methods are disclosed for performing multiple processing of data in a network. In one embodiment, the network comprises a first display pipeline that is formed in real time from a plurality of possible display pipelines and that performs at least a first processing step on received data. A buffer stores the processed data and a second display pipeline that is formed in real time from a plurality of possible display pipelines performs at least a second processing step on stored data.

Abstract: Methods and systems may include a computing system having a graphics processor with a three-dimensional (3D) pipeline, one or more processing units, and compute kernel logic to process two-dimensional (2D) command. A graphics processing unit (GPU) scheduler may dispatch the 2D command directly to the one or more processing units. In one example, the 2D command includes at least one of a render target clear command, a depth-stencil clear command, a resource resolving command and a resource copy command.

Abstract: A tile-based graphics system, and method of operation of such a system, are provided for generating graphics data for a frame comprising a plurality of tiles. Graphics processing circuitry is provided which is arranged to be switched between a first mode of operation and a second mode of operation. In the first mode of operation, the graphics processing circuitry receives the plurality of graphics primitives for the frame, and performs a binning operation to determine, for each of the plurality of tiles, a tile list identifying the graphics primitives which intersect that tile. In the second mode of operation, the graphics processing circuitry receives the tile list for an allocated tile, and performs a rasterization operation to generate the graphics data for the allocated tile dependent on the tile list.

Abstract: The present invention relates to machine vision computing environments, and more specifically relates to a system and method for selectively accelerating the execution of image processing applications using a multi-core processor system. To this extent, a multi-core processor system is generally defined as one that is multi-platform, and potentially distributed via a network or other connection. The invention provides a machine vision system and method for executing image processing applications referred to herein as an image co-processor that comprises (among other things) a plurality of multi-core processors (MCPs) that work to process multiple images in an accelerated fashion.

Abstract: Configuration information is used to make a determination to bypass fragment shading by a shader unit of a graphics processing unit, the shader unit capable of performing both vertex shading and fragment shader. Based on the determination, the shader unit performs vertex shading and bypasses fragment shading. A processing element other than the shader unit, such as a pixel blender, can be used to perform some fragment shading. Power is managed to “turn off” power to unused components in a case that fragment shading is bypassed. For example, power can be turned off to a number of arithmetic logic units, the shader unit using the reduced number of arithmetic logic unit to perform vertex shading. At least one register bank of the shader unit can be used as a FIFO buffer storing pixel attribute data for use, with texture data, to fragment shading operations by another processing element.

Abstract: A method for high-speed image processing based on graphic processing unit includes processing an input image for the image processing in a texture format of a 32 bit floating point, and performing a predetermined algorithm for the image processing on the input image through at least one or more Framebuffer Object (FOB) and outputting the result as texture data.

Abstract: The invention provides, in some aspects, a system for rendering images, the system having one or more client digital data processors and a server digital data processor in communications coupling with the one or more client digital data processors, the server digital data processor having one or more graphics processing units. The system additionally comprises a render server module executing on the server digital data processor and in communications coupling with the graphics processing units, where the render server module issues a command in response to a request from a first client digital data processor.

Abstract: An arithmetic logic stage in a graphics processor unit pipeline includes a number of arithmetic logic units (ALUs) and at least one buffer that stores pixel data for a group of pixels. Each clock cycle, the buffer stores one row of a series of rows of pixel data. A deserializer deserializes the rows of pixel data before the pixel data is placed in the buffer. After the buffer accumulates all rows of pixel data for a pixel, then the pixel data for the pixel can be operated on by the ALUs.

Abstract: A method and an apparatus are provided for combining multiple independent tile based graphic cores. An incoming geometry stream is split into a plurality of streams and sent to respective tile based graphics processing cores. Each one generates a separate tiled geometry lists. These may be combined into a master tiling unit or, alternatively, markers may be inserted into the tiled geometry lists which are used in the rasterization phase to switch between tiling lists from different geometry processing cores.

Abstract: An apparatus and methods for scheduling and executing commands issued by a first processor, such as a CPU, on a second processor, such as a GPU, are disclosed. In one embodiment, a method of executing processes on a graphics processing unit (GPU) includes monitoring one or more buffers in a memory, selecting a first subset from the one or more buffers for execution on the GPU based on a workload profile of the GPU, and executing the first subset on the GPU. The GPU may also receive a priority ordering of the one or more buffers, where the selecting is further based on the received priority ordering. By performing prioritization and scheduling of commands in the GPU, system performance is enhanced.

Abstract: A method and electronic device employing the method of processing a frame of graphics for display is provided that includes developing a frame in a first software frame processing stage following a first vertical blanking (VBL) heartbeat, issuing a command indicating the first stage is complete, and performing a final software frame processing stage without waiting for a subsequent VBL heartbeat. The method may alternatively include performing the final software frame processing stage regardless as to whether a target framebuffer is available, performing all but final hardware frame processing stages regardless as to whether the target framebuffer is in use, and performing the final hardware processing stage if the target framebuffer is not in use.

Abstract: A floating point rasterization and frame buffer in a computer system graphics program. The rasterization, fog, lighting, texturing, blending, and antialiasing processes operate on floating point values. In one embodiment, a 16-bit floating point format consisting of one sign bit, ten mantissa bits, and five exponent bits (s10e5), is used to optimize the range and precision afforded by the 16 available bits of information. In other embodiments, the floating point format can be defined in the manner preferred in order to achieve a desired range and precision of the data stored in the frame buffer. The final floating point values corresponding to pixel attributes are stored in a frame buffer and eventually read and drawn for display. The graphics program can operate directly on the data in the frame buffer without losing any of the desired range and precision of the data.

Abstract: An apparatus for rendering an image includes a command binning module. The command binning module generates binned image information by classifying command information into bins that each correspond to a display tile of an image to be rendered. The command binning module generates image depth information for each display tile based on the binned command information.

Abstract: A method of managing multiple contexts for a single mode display includes receiving a plurality of tasks from one or more applications and determining respective contexts for each task, each context having a range of memory addresses. The method also includes selecting one context for output to the single mode display and loading the selected context into a graphics processor for the display.

Abstract: A multi-pass method of generating an image frame of a 3D scene while eliminating the overdrawing of objects within the multiple graphics processing pipelines (GPPLs) supported on a parallel graphics processing system The GPPLs include a primary GPPL, and each GPPL, includes a color frame buffer and Z depth buffer. The GPPLs support an object-division based parallel graphics rendering process, in which the 3D scene is decomposed into objects that are assigned to particular GPPLs for processing. The multi-pass method involves, during a first pass, locally a Global Depth Map (GDM) which is provided to the Z depth buffer of each GPPL. This step involves the transmission of graphics commands and data for all objects in the image frame, to all GPPLs to be rendered. Then, during subsequent passes, a complementary-type partial image consisting of visible pixels only is generated within the color buffer of each GPPL using the GDM and a Z test filter supported by the Z depth buffer.

Abstract: According to embodiments of the invention, a data structure may be created which may be used by both a ray tracing unit and by a rendering engine. The data structure may have an initial or upper portion representing bounding volumes which partition a three-dimensional scene and a second or lower portion representing objects within the three-dimensional scene. The integrated acceleration data structure may be used by a rendering engine to render a two-dimensional image from a three-dimensional scene, and by a ray tracing unit to perform intersection tests.

Abstract: Disclosed is a wireless remote network management system for interfacing a series of remote devices (e.g., computers, servers, networking equipment, etc.) to one or more user workstations. The system is multifunctional to allow multiple users to control remote devices through serial access or keyboard, video, and cursor control device access via wireless and hard-wired connections. The remote devices are preferably coupled to a wireless-enabled remote management unit through a chain of computer interface modules, and each user workstation includes a wireless user station coupled to a keyboard, a video monitor and a cursor control device. The remote management unit and user stations preferably communicate via a wireless network, which enables a user workstation to access, monitor and control any of the remote devices.

Abstract: A system for processing graphics data. The graphics processing system includes an embedded memory array having at least three separate banks of single-ported memory in which graphics data are stored. A memory controller coupled to the banks of memory writes post-processed data to a first bank of memory while reading data from a second bank of memory. A synchronous graphics processing pipeline processes the data read from the second bank of memory and provides the post-processed graphics data to the memory controller to be written back to a bank of memory. The processing pipeline concurrently processes an amount of graphics data at least equal to that included in a page of memory. A third bank of memory is precharged concurrently with writing data to the first bank and reading data from the second bank in preparation for access when reading data from the second bank of memory is completed.

Abstract: A system, method and article of manufacture are provided for programmable processing in a computer graphics pipeline. Initially, data is received from a source buffer. Thereafter, programmable operations are performed on the data in order to generate output. The operations are programmable in that a user may utilize instructions from a predetermined instruction set for generating the same. Such output is stored in a register. During operation, the output stored in the register is used in performing the programmable operations on the data.

Abstract: Systems and methods are disclosed for video processing modules. More specifically a network is disclosed for processing data. The network comprises a register DMA controller adapted to support register access and at least one node adapted to the data. At least one link communicates with the node, and is adapted to transmit data and at least one network module communicates with at least the link, and is adapted to route data to at least the link.

Abstract: A method, computer program product, and system are provided for processing data in a graphics pipeline. An embodiment of the method includes processing one or more vertices of a geometric primitive with a vertex shader function and generating new primitive information for the one or more processed vertices with a geometry shader function. The geometry shader function receives one or more processed vertices from the vertex shader function and emits a single vertex associated with the new primitive information. Each emitted vertex from the geometry shader function can be stored in a memory device. Unlike conventional graphic pipelines that require a memory device for data storage during the vertex and geometry shading processes, the present invention increases efficiency in the graphics pipeline by eliminating the need to access memory when the vertex and geometry shaders process vertex information.

Abstract: A system, method and article of manufacture are provided for programmable processing in a computer graphics pipeline. Initially, data is received from a source buffer. Thereafter, programmable operations are performed on the data in order to generate output. The operations are programmable in that a user may utilize instructions from a predetermined instruction set for generating the same. Such output is stored in a register. During operation, the output stored in the register is used in performing the programmable operations on the data.

Abstract: A processing unit includes multiple execution pipelines, each of which is coupled to a first input section for receiving input data for pixel processing and a second input section for receiving input data for vertex processing and to a first output section for storing processed pixel data and a second output section for storing processed vertex data. The processed vertex data is rasterized and scan converted into pixel data that is used as the input data for pixel processing. The processed pixel data is output to a raster analyzer.

Abstract: A media processing framework includes multiple media processing paths. At least one of the media processing paths includes a media processing pipeline which is in-process with respect to an application which interacts with the media processing pipeline. At least one other of the media processing paths includes a media processing pipeline which is out-of-process with respect to the application. The application can specify a custom plug-in presenter module to be set in either the in-process media processing pipeline or the out-of-process media processing pipeline. The application need not be “aware” of the pipeline that is being used, whether the pipeline is in-process or out-of-process, or the security level that is applied to the media processing pipeline. Both the in-process and the out-of-process media processing pipelines can supply media information to a presentation processor, such as a compositing engine.

Abstract: A system, method, and computer program product are provided for converting a scan algorithm to a segmented scan algorithm in an operator independent manner. In operation, a scan algorithm and a limit index data structure are identified. Utilizing the limit index data structure, the scan algorithm is converted to a segmented scan algorithm in an operator-independent manner. Additionally, the segmented scan algorithm is performed to produce an output.

Abstract: Where each of m and n are any natural number: a drawing region subdivider 5 for subdividing a drawing region into an m×n matrix of drawing subregions having m rows and n columns,; a target vector data selector 6 for discriminating, for each of the drawing subregions, vector data necessary for drawing the drawing subregion from vector data of an image; and a subdivisional drawer 7 for drawing, for each of the drawing subregions after the subdivision by the drawing region subdivider 5, an image based on a drawing subregion target vector data 23 discriminated by the target vector data selector 6 are provided as necessary for drawing the drawing subregion. Preferably, a curve vector data replacer 71 of the subdivisional drawer 7, for each of the drawing subregions, replaces curve vector data outside of the drawing subregion from vector data configuring a figure to be subdivisionally drawn with straight-line vector data and performs a fill processing.

Abstract: Apparatuses and methods are presented for a hierarchical processor. The processor comprises, at a first level of hierarchy, a plurality of similarly structured first level components, wherein each of the plurality of similarly structured first level components includes at least one combined function module capable of performing multiple classes of graphics operations, each of the multiple classes of graphics operations being associated with a different stage of graphics processing.

Abstract: A method and system for programmable breakpoints in an integrated embedded image and video accelerator are described. Aspects of the system may include circuitry that enables generation of control signals for pipeline processing of video data within a single chip by at least selecting a target location of the video data and generating an interrupt at a time instant corresponding to the pipeline processing of the target location. The system may enable programmable breakpoints to be set and/or triggered based on policies determined in executable software. The ability to set programmable breakpoints may enable flexible utilization of system memory resources.

Abstract: Embodiments described herein provide a method of arbitrating a processing resource. The method includes receiving a command to preempt a task and preventing additional wavefronts associated with the task from being processed.

Abstract: What is provided are a system and method for print/copy job environments utilizing a page description language (PDL). In one embodiment, an input PDL stream describing embedded objects in a job is received and parsed. Reusable document components (RDCs) are identified. A determination is made as to how many placements are in the PDL for each identified RDC. If no RDCs are placed more than once, caching is disabled. If it is not efficient to split the PDL stream into smaller tasks, page parallel rip (PPR) is disabled. The embedded objects are analyzed to determine a number of PPRs for the job based on system resources. A raster image processing (RIP) time is projected for each path in the job based on the determined number of placements and the determined number of PPRs. A job processing path is prescribed for the job based on the most efficient projected RIP time.

Abstract: Provided is an image display apparatus that includes a display unit that displays a series of images obtained by imaging an inside of a subject in time sequence, and displays a time bar indicating imaging periods of the series of images so that areas of the time bar are identified by different colors corresponding respectively to regions of the inside of the subject. The apparatus also includes a control unit that identifies the respective regions of the inside of the subject, which are displayed on the series of images, and controls the display unit so that, for each of the regions identified, an area of the time bar corresponding to a period when a series of images of the region are displayed is colored with a substitute color identifying the region.

Abstract: The present approach increases bandwidth by performing at least two functions at the pre-processing level. Specifically, under the present approach, program code is structured so that the segmentation and binarization functions/modules (and optionally a blob analysis function/module) are merged into a single module to reduce memory bandwidth. In addition, each image frame is segmented into a plurality of partitions (e.g., vertical strips) to enhance the reusability of the image data in LS already fetched from main memory. Each partition is then processed by a separate one of a plurality of processing engines, thereby increasing the utilization of all processing engines and allowing the processing engines to maintain good bandwidth.

Abstract: One embodiment of the present invention sets forth a system configured for transferring data between independent application programming interface (API) contexts on one or more graphics processing units (GPUs). Each API context may derive from an arbitrary API. Data is pushed from one API context to another API context using a peer-to-peer buffer “blit” operation executed between buffers allocated in the source and target API context memory spaces. The source and target API context memory spaces may be located within the frame buffers of the source and target GPUs, respectively, or located within the frame buffer of a single GPU. The data transfers between the API contexts are synchronized using semaphore operator pairs inserted in push buffer commands that are executed by the one or more GPUs.

Abstract: A system renders a primitive of an image to be displayed, for instance in a mobile 3D graphic pipeline, the primitive including a set of pixels. The system locates the pixels in the area of the primitive, generates, for each pixel located in the area, a set of associated sub-pixels, borrows a set of sub-pixels from neighboring pixels, subjects the set of associated sub-pixels and the borrowed set of pixels to adaptive filtering to create an adaptively filtered set of sub-pixels, and further filters the adaptively filtered set of sub-pixels to compute a final pixel for display. Preferably, the set of associated sub-pixels fulfills at least one of the following: the set includes two associated sub-pixels and the set includes associated sub-pixels placed on pixel edges.

Abstract: A method and system for connecting multiple shaders are disclosed. Specifically, one embodiment of the present invention sets forth a method, which includes the steps of configuring a set of shaders in a user-defined sequence within a modular pipeline (MPipe), allocating resources to execute the programming instructions of each of the set of shaders in the user-defined sequence to operate on the data unit, and directing the output of the MPipe to an external sink.

Abstract: A processing unit, method, and graphics processing system are provided for processing a plurality of frames of graphics data. For instance, the processing unit can include a first plurality of graphics processing units (GPUs), a second plurality of GPUs, and a plurality of compositors. The first plurality of GPUs can be configured to process a first frame of graphics data. Likewise, the second plurality of GPUs can be configured to process a second frame of graphics data. Further, each compositor in the plurality of compositors can be coupled to a respective GPU from the first and second pluralities of GPUs, where the plurality of compositors is configured to sequentially pass the first and second frames of graphics data to a display module.

Abstract: Circuits, methods, and apparatus that provide texture caches and related circuits that store and retrieve texels in an efficient manner. One such texture circuit can provide a configurable number of texel quads for a configurable number of pixels. For bilinear filtering, texels for a comparatively greater number of pixels can be retrieved. For trilinear filtering, texels in a first LOD are retrieved for a number of pixels during a first clock cycle, during a second clock cycle, texels in a second LOD are retrieved. When aniso filtering is needed, a greater number of texels can be retrieved for a comparatively lower number of pixels.

Abstract: Embodiments of the invention provide a method for extending a graphics rendering framework. A rendering application locates a first file that includes a first implementation involving a first graphics material and compares data associated with the first file to data associated with a second file that includes a second implementation involving a second graphics material. The rendering application compares data associated with the first and second files, determines that the first graphics material matches the second graphics material, and determines that the first implementation is different from the second implementation. The data associated with the first file and the data associated with the second file are then combined into a data structure.

Abstract: Each unit among a pipeline of image processing units receives a new configuration vector (update), and the received new vector is only applied in sync with the Timing-derived trigger signal within a hardware-enabled time period. A hardware enable signal is logically combined with a Timing-derived triggering event signal to control a switch that applies the new received vector to the processing unit. This ensures that each image processing unit (stage) in the chain of image processing units is updated in sequence even if the CPU has output the updated configuration vectors independently of the Timing of the Data and without regard for the delay through each of the processing units. The Timing-derived triggering event is used to synchronize the application of a received configuration vector update with the receipt by the unit of a new frame of image DATA.

Abstract: One embodiment of the present invention sets forth a graphics pipeline architecture for optimizing graphics rendering efficiency by advancing the Z-test operation prior to shading operations whenever possible, as determined by an upstream pipeline configuration unit. Each processing engine within the graphics pipeline maintains independent state for both early Z-mode and late Z-mode operations and also may maintain state common to both modes. The processing engines receive work transactions that include a Z-mode flag indicating whether the work transaction should be processed in late Z-mode or early Z-mode. The Z-mode flag is also used to dynamically route any resulting outbound data, so that the appropriate data flow for either early Z or late Z processing is dynamically constructed for each work transaction.

Abstract: An apparatus includes a plurality of image processing circuits. Each image processing circuit generates an image frame corresponding to a single large surface. The first image processing circuit provides a portion of the generated image frame for a first display or plurality of displays and provides a remaining portion of the image frame to the remaining image processing circuits. The next image processing circuits provides the remaining portion of the image frame for the next plurality of displays.