Abstract: Disclosed are methods, circuits and systems for wireless transmission of a video signal from a computing platform. There is provided a video and/or audio signal source device such as a laptop computer. The video and/or audio signal source device may include a Display Mini Card (DMC) System Connector. The video and/or audio signal source device may include a Mini Card (HMC or FMC) System Connector, and/or a Display Port (DP) connector. There may be provided a Display Mini Card (DMC) or a Mini Card (FMC or HMC) which may include electrical circuits adapted to receive video and/or audio signals from the DMC System Connector or the DP connector of the video and/or audio signal source device. Received video and/or audio signals may be transmitted to a functionally associated video/audio receiver. The electrical circuits of the Display Mini Card (DMC) or the Mini Card (FMC or HMC) may be adapted to transmit a video and/or audio signal using a video link such as WHDI, WIFI DIRECT or WIFI DISPLAY.

Abstract: Apparatus and methods for reducing power consumption of a data transfer interface in a computer system are disclosed. In one embodiment, a method for reducing power consumption of a data transfer interface between a first device and a second device, includes, identifying a free interval between a first data and a second data, disabling the data transfer interface during the free interval, enabling the data transfer interface at the end of the free interval, and transmitting the second data. The method may also include a step of notifying the second device that the data transfer interface is being temporarily disabled. Another embodiment, for example, includes the transfer of display data (or video frames) over an interface, such as, a DisplayPort interface, between a graphics controller device and a timing controller device in a computer system.

Abstract: A scaling engine, blending mechanism, memory controller, frame buffer and video driver are included within a semiconductor, such as a Field Programmable Gate Array (FPGA), to provide broadcasting of signals at a high resolution format by combining two or more low resolution video signals to create a high resolution signal in real-time High Definition format, such as 1080p. The high resolution signals can be concurrently displayed as one or more image areas on a display device in any contemplated size, number and arrangement.

Abstract: The semiconductor IC device for display control disclosed herein aims to achieve a higher rate of memory access cycles without enhancing the current carrying capability of the memory device. The IC device is provided with a memory cell array capable to store display data, peripheral circuits to enable writing and reading of display data, and a control circuit which is able to control read and write operations from/to the memory cell array. The memory cell array comprises a plurality of memory blocks. The control circuit comprises a control logic which enables parallel processing of write operations in such a manner that, before completion of writing of data to one of the memory blocks, writing of data to another memory block is started. Write cycles are shortened by the parallel processing of write operations.

Abstract: A current detection unit that monitors changes in two types of voltage produced by the voltage control unit, and detects and abnormal current flowing due to a potential between the two types of the voltages at both ends of the voltage control unit and an HPG control that receives a control signal of a constant voltage supplied from the information processing device, and transmits a HPG signal to the information processing device based on the abnormal current detected by the current detection unit and the control signal, wherein the HPG signal is a signal indicating a supply state of the direct current power voltage.

Abstract: An controlled LED lighting system that operates using a single conductor to power and control LED nodes is disclosed. The controlled LED lighting system modulates control data onto a nominally constant DC signal transmitted down a single conductor serial line. Nodes coupled the serial line draw power into a local capacitor and demodulate the data signal. Each node shunts the serial line when additional power is not required such that the data signal is received by every node on the serial line.

Abstract: Light Emitting Diodes (LEDs) are increasingly used in illumination applications. To control multiple Light Emitting Diodes (LEDs), or any other controllable light source, this document introduces a single-wire multiple-LED power and control system. Specifically, individually controlled LED units are arranged in a series configuration that is driven by a control unit located at the head of the series. Each of the individually controlled LED units may comprise more than one LED that is also individually controllable. The head-end control unit provides both electrical power and control signals down a single wire to drive all of the LED units in the series in a manner that allows each LED unit to be controlled individually or in assigned groups.

Abstract: A computer, a graphic card, a display apparatus and a method of updating information is described, wherein, the computer has a first status and a second status, and the system power consumption of computer in the first status is larger than the system power consumption of computer in the second status. The computer includes a graphic card having display memory and a display apparatus connected to the graphic card, and further includes an input processing module for acquiring input information when the computer is in the second status, and updating first display information stored in the display memory outputted to the display apparatus according to the input information to obtain second display information. The graphic card outputs the second display information to the display apparatus when the computer is in the second status.

Abstract: A method is provided for updating a data-rendering device connected to a communications network by an intermediate device. A specific electronic address is assigned to the data-rendering device. The method includes associating at least one identifier, preliminarily assigned to the intermediate device, with the electronic address. The at least one identifier belongs to the group including at least: one dynamic connection identifier of the intermediate device and one user account identifier (AID).

Abstract: Light Emitting Diodes (LEDs) are increasingly used in illumination applications. To control multiple Light Emitting Diodes (LEDs), or any other controllable light source, this document introduces a single-wire multiple-LED power and control system. Specifically, individually controlled LED units are arranged in a series configuration that is driven by a control unit located at the head of the series. Each of the individually controlled LED units may comprise more than one LED that is also individually controllable. The head-end control unit provides both electrical power and control signals down a single wire to drive all of the LED units in the series in a manner that allows each LED unit to be controlled individually or in assigned groups.

Abstract: Disclosed are an apparatus and a method for processing data, capable of controlling the use of a graphic controller based on data usage in a memory, a variation speed of a memory data value, and/or operating states/conditions of a system.

Abstract: A system for controlling signal skew between adjacent transmission lines is disclosed. In one embodiment, the system includes a plurality of transmission lines, each of which is physically adjacent to at least one other one of the plurality of transmission lines. The system further includes a plurality of transmission units, wherein each of the plurality of transmission units is coupled to a corresponding one of the plurality of transmission lines. Each of the plurality of transmission units is configured to transmit, in accordance with a respectively received one of a plurality of clock signals, a respective signal on its corresponding one of the plurality of transmission lines such that the respective signal is skewed by a predetermined amount with respect to signals transmitted on each adjacent one of the plurality of transmission lines.

Abstract: Wireless communication of display information between an information handling system and display is supported by a direct connection between a graphics system of the information handling system and a transceiver of the information handling system. For example, the graphics system outputs pixel level display information through a cable directly to the transceiver. A converter on the transceiver converts the display information to network information, such as from a DisplayPort format to a PCI Express format, so the transceiver can send the display information through a wireless network, such as a personal area network, to the display. A display module located at the transceiver coordinates initiation of communication of display information from the graphics system to the display.

Abstract: One embodiment of the invention sets forth a control crossbar unit that is designed to transmit control information from control information generators to destination components within the computer system. The control information may belong to various traffic paradigms, such as short-latency data traffic, narrow-width data traffic or broadcast data traffic. The physical connections within the control crossbar unit are categorized based on the different types of control information being transmitted through the control crossbar unit. The physical connections belong to the following categories: one-to-one (OTO) connections, one-to-many (OTM) connections, valid-to-one (VTO) connections, valid-to-many (VTM) connections wire-to-one (WTO) connections and wire-to-many (WTM) connections.

Abstract: A computer motherboard includes a display controller, a digital visual interface integrated (DVI-I) connector, and a switching unit. The switching unit includes four first terminals, two second terminals, and a control terminal. Two of the first terminals are respectively connected to clock and data pins of a first display data channel (DDC) of the display controller, the other two first terminals are respectively connected to clock and data pins of a second DDC of the display controller, and the second terminals are respectively connected to DDC clock and DDC data pins of the DVI-I connector. The control terminal is connected to a hot plug detect pin of the DVI-I connector to detect a voltage and correspondingly control the second terminals to be respectively connected to the two first terminals connected to the clock and data pins of the first DDC or the second DDC.

Abstract: The invention provides, in some aspects, a system for rendering images, the system having one or more client digital data processors and a server digital data processor in communications coupling with the one or more client digital data processors, the server digital data processor having one or more graphics processing units. The system additionally comprises a render server module executing on the server digital data processor and in communications coupling with the graphics processing units, where the render server module issues a command in response to a request from a first client digital data processor.

Abstract: Systems and methods for providing scalability of multiple graphic processor units (GPU) that work together in a multi-coprocessor fashion to provide parallel graphics rendering methodology for an information handling system. The total number of active GPUs working together to provide parallel graphics rendering methodology for a given information handling system may be increased in a modular manner beyond one or two GPUs, e.g., so as allow as many GPUs as desired to be attached to a given information handling system such as a desktop computer or notebook computer.

Abstract: The present invention provides a control method for switching display between a plurality of OSs as well as a computer system. The method comprises: detecting that the currently displayed guest operating system (GOS) is required to be switched from a first GOS to a second GOS; determining whether the first GOS satisfies a preset switching condition, and switching the currently displayed GOS to the second GOS if the preset switching condition is satisfied, and otherwise, prohibiting the switching from the currently displayed GOS. With the method and the computer system, it is possible to avoid picture distortion or blurring or system collapse in switching display between a plurality of OSs.

Abstract: A display interface circuit includes a physical layer circuit for receiving and modulating an original data signal and an original clock signal, a frame buffer for storing and outputting the data signal according to the clock signal and a command signal, a display serial interface for transmitting the data signal and the clock signal through packetization, a configuration register for generating the command signal according to an asynchronous clock signal and the data signal, and an asynchronous delay circuit for adjusting a clock latency that the clock signal takes to be sent to the configuration register to generate the asynchronous clock signal.

Abstract: One embodiment of the present invention sets forth a technique for generating and transmitting video frame data from a graphics processing unit (GPU) to a color field sequential display device. A frame buffer image comprising per-pixel packed color channels is transformed to a frame buffer image comprising regions corresponding to the color channels with vertical blanking regions inserted between color sub-field regions. Each region of the transformed frame buffer image is sequentially transmitted to the color field sequential display device for display of the corresponding color channel. Backlight illumination for each color channel is controlled by the GPU for temporal alignment with display of each color channel during a vertical blanking interval. The GPU may compensate an individual pixel's color channel value based on a corresponding previous color channel value in order to minimize crosstalk between neighboring color fields.

Abstract: A computer memory system (20) which comprises a media module (22); a host computer (24) configured to accommodate the media module (22) in removable fashion; and a display unit (26). The media module (22) is configured to store electronic data. The host computer (24) comprises a docking station (30) configured to accommodate the media module (22); an interface (32) through which electronic signals representing the electronic data are transmitted between the host computer (24) and the media module (22); an optical indicator (34); and a host processor (36). The host processor (36) is configured to control a read/write operation over the interface between the host computer (24) and the media module (22) and to activate the optical indicator (34) whereby the optical indicator (34) provides a first optical signal depicting transmission of electronic signals over the interface in the read/write operation.

Abstract: A gate driving circuit having improved driving capability and maintaining reliability even after a prolonged period of use includes a shift register having a plurality of stages cascaded to one another, each of the plurality of stages including a pull-up unit, a pull-down unit, a discharging unit, and a holding unit, wherein at least one of the discharging unit and the holding unit includes an amorphous silicon thin film transistor and a polysilicon thin film transistor connected in parallel to each other.

Abstract: Systems and methods for downloading algorithmic elements to a coprocessor and corresponding processing and communication techniques are provided. For an improved graphics pipeline, the invention provides a class of co-processing device, such as a graphics processor unit (GPU), providing improved capabilities for an abstract or virtual machine for performing graphics calculations and rendering.

Abstract: An interface apparatus and method are provided. The interface apparatus includes a level detecting unit detecting a level of an inputted control signal, a counter unit increasing or decreasing a count value according to the level detected in the level detecting unit, and a driving control unit outputting a driving control information mapped into a count value of the counter unit.

Abstract: A digital audio signal, a channel clock, and a bit clock are transmitted to the receiving apparatus via a pair of signal lines. The digital audio signal is input to a D/A converter via a first comparator. The channel clock and the bit clock are received, separated with first and second separation circuits, and input to the D/A converter via the second and third comparators. A reference electrical potential of the second comparator is corrected such that it becomes half or approximately half of an amplitude of the channel clock depending on an electrical potential change of the output of a second differential signal receiving circuit. A system clock is generated based on the bit clock. The digital audio signal is converted into the analog audio signal based on the channel clock, the bit clock, and the system clock, and then the converted analog audio signal is output.

Abstract: In general, aspects of this disclosure describe example techniques for efficient usage of the fixed data rate processing of a graphics processing unit (GPU) for a variable data rate processing. For example, the GPU may be coupled to a pixel value processing unit that receives pixel values for pixels in an image processed by the GPU. The pixel value processing unit may determine whether the pixel values are for pixels that require further processing, and store the pixel values for the pixels that are required for further processing in a buffer.

Abstract: Systems, processes and apparatus are described through which signals are modified within a system. A signal conditioning module is configured for insertion into the system and provides capability for expansion of information exchange capabilities between system elements responsive to modification of the system. The signal conditioning module includes a first link for supplying coordinated information to multiple display elements to synchronize information displayed by each of the multiple display elements, a second link for supplying coordinating data internal to a control system for a nondestructive imaging system to synchronize the internal data with the information displayed by each of the multiple elements and a third link for supplying coordination descriptions relevant to a nondestructive imaging task performed by the system to a memory, including an image and data relevant to that image.

Abstract: A method and apparatus for supporting a self-refreshing display device coupled to a graphics controller are disclosed. A self-refreshing display device has a capability to drive the display based on video signals generated from a local frame buffer. A graphics controller coupled to the display device may optimally be placed in one or more power saving states when the display device is operating in a panel self-refresh mode. Data objects stored in a memory associated with the graphics controller may be aliased in another memory subsystem accessible to the operating system, graphical user interface, or applications executing in the system while the graphics controller is in a deep sleep state. The disclosed technique utilizes a virtual memory pointer, that may be updated in one or more virtual memory page tables to point to either the memory associated with the graphics controller or an alternate memory alias.

Abstract: Methods and apparatus for determining the state of a tile based deferred rendering processor are described. The method and apparatus include generating information indicating the state of the tile based deferred rendering processor when processing a unit of data during the geometry phase; generating an identifier that identifies the unit of data being processed during the geometry phase; storing the identifier identifying the unit of data processed during the geometry phase in association with the state of the tile based deferred rendering processor when processing the identified unit of data; generating information indicating the state of the tile based deferred rendering processor when processing the identified unit of data during the rasterisation phase; and outputting the stored identifier and the stored state information relating to the processing of the unit of data when the state of the tile based deferred rendering processor meets a condition.

Abstract: A method and a device for displaying an application image are provided, and the method includes the following steps: receiving a display request from a second operating system, and reading the application image stored in a storage area; judging whether it is required to process the application image through a window manager according to the configuration of the local image display system, and if required, sending the application image to the window manager, and sending the application image processed by the window manager to a display graphics library for processing; if not, directly sending the application image to the display graphics library for processing; and acquiring the location of the display memory through a display driver, sending the application image processed by the display graphics library to the display memory, and displaying the application image through the display memory.

Abstract: A method and system for converting the output of a communications port (e.g., a serial port or a USB port) into video signals representing the output of a terminal using a KVM switch. Upon receiving characters from the communications port, the system interprets the characters as terminal emulation commands and internally generates a representation of what a resulting terminal screen would look like. From that internal (digital) representation, the system produces analog outputs representing the terminal screen. The analog outputs are output on the monitor attached to the KVM switch.

Abstract: The current invention allows the connection of a plurality of monitors to a single host computer, allowing the use by a plurality of users without the additional cost and complexity of a terminal server, local area network and thin clients or additional computers for each user. The host computer includes a video card having at least two separate video outputs, each connected to a monitor. Alternatively or additionally, the host includes a plurality of video cards. Each user interacts with a unique session that executes the user's application and displays its results on one of the monitors. The invention disclosed methods for enabling use of one or more physical graphics cards for one or more user sessions within a single computer. The invention disclosed methods to allow the assignment of a separate video output to each user by using video a plurality of drivers.

Abstract: In accordance with some embodiments, a graphics process frame generation frame rate may be monitored in combination with a utilization or work load metric for the graphics process in order to allocate performance resources to the graphics process and in some cases, between the graphics process and a central processing unit.

Abstract: A display list with slot instructions is provided to interface between platform software and a display engine. A display list interface is created for each frame of image data that is to be updated and displayed on a display. In some circumstances, the display list may be reused for subsequent frames, for example, when generating a stream of video images for a video mode display showing a static image. A display list may be part of the interface between a software driver and a scalable display engine architecture that has multiple repetitive processing blocks enabling the same or multiple frames to be processed in parallel to produce update frames for one or more display devices.

Abstract: A multi-functional display device and method for displaying content on the same are disclosed herein. The method may include displaying broadcast content on a first multi-functional display device, transmitting a request to display the content on a second multi-functional display device. The second multi-functional display device may accept the request and display the content on the second multi-functional display device. The first and second multi-functional display devices may display the content at the same time. The first multi-functional display device may be associated with a first social network service (SNS) account of a first individual and the second multi-functional display device may be associated with a second SNS account of a second individual. The request to concurrently view the content may be generated using account information of the SNS accounts.

Abstract: Briefly, in accordance with one or more embodiments, a reconfigurable 3D graphics processor includes a pipeline configuration manager, a rasterizer, and a memory coupled to the triangle rasterizer. The pipeline configuration manager is capable of configuring the graphics processor to operate in a direct rasterizing mode or a tiling mode to process a sequence of drawing commands received from a processing unit.

Abstract: A method of providing information for display includes receiving primary, secondary, and tertiary information for display at an information handling system. The tertiary information is communicated to a display interface after the primary and secondary information during a time period otherwise assigned to the communication of dummy information. This allows more information to be communicated via a communication channel.

Abstract: Systems, methods, and articles of manufacture for optimizing task scheduling on an accelerated processing device (APD) device are provided. In an embodiment, a method comprises: enqueuing, using the APD, one or more tasks in a memory storage; and dequeuing, using the APD, the one or more tasks from the memory storage using a hardware-based command processor, wherein the command processor forwards the one or more tasks to a shader core.

Abstract: An interface card comprising a graphic unit, an outputting interface, an inputting interface, an assigning processor and a card body is disclosed. The inputting interface is used for receiving a PCIE inputting signal. When the inputting interface is electrically connected to a CPU via a connector, the PCIE inputting signal is inputted to the assigning processor via an inputting interface. The assigning processor assigns a PCIE outputting signal to a graphic unit according to the PCIE inputting signal, and further assigns another PCIE outputting signal to another graphic unit according to the PCIE inputting signal when the outputting interface is externally connected to another graphic unit. The card body is used for placing the graphic unit, the outputting interface, the assigning processor and the inputting interface.

Abstract: Embodiments described herein provide a method of arbitrating a processing resource. The method includes receiving a command to preempt a task and preventing additional wavefronts associated with the task from being processed.

Abstract: A method and system for overriding state information programmed into a processor using an application programming interface (API) avoids introducing error conditions in the processor. An override monitor unit within the processor stores the programmed state for any setting that is overridden so that the programmed state can be restored when the error condition no longer exists. The override monitor unit overrides the programmed state by forcing the setting to a legal value that does not cause an error condition. The processor is able to continue operating without notifying a device driver that an error condition has occurred since the error condition is avoided.

Abstract: One embodiment of the present invention sets forth a system configured for transferring data between independent application programming interface (API) contexts on one or more graphics processing units (GPUs). Each API context may derive from an arbitrary API. Data is pushed from one API context to another API context using a peer-to-peer buffer “blit” operation executed between buffers allocated in the source and target API context memory spaces. The source and target API context memory spaces may be located within the frame buffers of the source and target GPUs, respectively, or located within the frame buffer of a single GPU. The data transfers between the API contexts are synchronized using semaphore operator pairs inserted in push buffer commands that are executed by the one or more GPUs.

Abstract: Techniques for hardware accelerated caret rendering are described in which a system based caret is emulated using hardware acceleration technology. The hardware accelerated caret can be rendered using dedicated graphics processing hardware to look and feel like a system caret. This can involve using pixel shaders to produce the hardware accelerated caret and a employing a back-up texture to remove the caret after it is drawn and cause the caret to blink. In addition, rendering of the caret can be coordinated with other animations and/or other presentations of a frame buffer to piggy back drawing of the caret onto other drawing operations. This can reduce the number of times the frame buffer is presented and therefore improve performance.

Abstract: Systems, methods, and computer readable storage mediums for arbitrating the sending of display data to a plurality of displays that are coupled to a controller are disclosed. A method for arbitrating display data requests for a plurality of displays coupled to a controller includes, providing display data to a display in the plurality of displays based upon a relative priority of the display amongst the plurality of displays.

Abstract: Systems and methods of adjusting a frequency of a graphics controller may include a logic to determine a metric associated with an input/output (I/O) queue. The metric may be used to determine whether an I/O limited condition exists. The I/O limited condition may be associated with a graphics controller. There may be a logic to cause a frequency of the graphics controller to be decreased when the I/O limited condition exists, and a logic to cause the frequency of the graphics controller to be increased when the I/O limited condition does not exist. The I/O limited condition may exist when a magnitude of the metric is equal to or greater than a first threshold. The I/O limited condition may not exist when the magnitude of the metric is equal to or less than a second threshold.

Abstract: Mode conversion methods and display apparatuses thereof are provided. The method converts to a second mode in which the display apparatus displays an image inputted from a second source, if there is no input of an image signal from a first source during the display apparatus operates in a first mode in which the display apparatus displays the image inputted from the first source. According to the present invention, it is possible to convert a mode automatically based on the external input status. A user may be provided two modes conveniently using the conversion method.

Abstract: Disclosed are an apparatus, a computer device, a system, computer readable media and a method for using graphics processing unit (“GPU”)-generated data to characterize, in-situ, the ability of a cable to reliably carry digitized video, among other things. In one embodiment, a computing device includes a processor coupled via a system bus to a graphics engine and a video cable-testing apparatus. This apparatus has an input port configured to couple to the digitized video cable to receive pixel data generated by the graphics engine. It also has a signal integrity evaluator (“SIE”) configured to identify the digitized video cable as the source an amount of data corruption, the amount of data corruption being a function of the pixel data. The signal integrity evaluator includes a classifier to classify the amount of data corruption into classes that each represents various degrees of degradation of the computer-generated video images.

Abstract: According to one embodiment, an information processing apparatus includes a connector, a graphics controller, a port setting module, a selector and a selector controller. The port setting module sets a first port used to output a video signal generated by the graphics controller as a data transmission port compliant with a first interface standard, and sets a second port used to output the video signal as a data transmission port compliant with a second interface standard. The selector connects one of the first port and the second port to the connector. The selector controller supplies a first signal to the selector in order to connect the first port to the connector when a first external unit is connected to the connector, and supplies a second signal to the selector in order to connect the second port to the connector when a second external unit is connected to the connector.

Abstract: An apparatus and method for processing a frame in consideration of processing capability and power consumption for each core in a multi-core system are provided. To perform a user interface drawing in a multi-core environment, an optimum combination of hardware components capable of operating with the minimum of power consumption while satisfying a requirement of a user may be obtained and a parallel user interface drawing may be performed by use of the optimum combination of hardware components.

Abstract: A computer-implemented system and method for off-line delivery of content through an active screen display are provided. A processor includes an encoding application to assemble and encode digitally-stored content into encoded content, and to interleave the encoded content with a signal conveying a live screen representation. The live screen representation includes output of a user interface for applications executing on the processor. An active screen display is coupled to the processor over a physical display interface connection. The active screen display includes a runtime application to identify the encoded content within the signal on the active screen display and to decode the encoded content into decoded content. The active screen display further includes an offline application to unilaterally display the decoded content on the active screen display without use of the processor and in an absence of the live screen presentation.