Abstract: An apparatus of an embodiment may include a network equipment chassis shield comprising a rectangular planar surface for mounting in front of a face of an equipment chassis, at least one supporting bracket for mounting the rectangular planar surface, and two or more fasteners for securing the rectangular planar surface to an anchoring structure. A first fastener may secure the rectangular planar surface to the at least one supporting bracket and a second fastener may secure the at least one supporting bracket to the anchoring structure.

Abstract: A method for transmitting image data through reduced swing differential signaling (RSDS) transmission interfaces to a driver in a display is provided, in which the image data include a number of pixel values each represented by a number of bits. The method includes the step of: simultaneously transmitting at least two bits of one of the pixel values by a single timing controller in one time period, in which each of the simultaneously transmitted bits is transmitted through a respective data line of the RSDS transmission interfaces.

Abstract: An information processing device in which a data bus for establishing interconnection between a plurality of control operating units formed in a main processor is connected at one end to a graphic processor and at the other end to a main memory. Image frame data generated by the graphic processor is sequentially transferred through the data bus and stored into the main memory. The data bus satisfies R1?R2?R4 and R1?R3?R4, where R1 is the data transmission rate from the main processor to the graphic processor, R2 is the data transmission rate from the graphic processor to the main processor, R3 is the data transmission rate between the main processor and the main memory, and R4 is the rate to transmit a single image frame of data within a vertical blanking interval.

Abstract: An embodiment of the present invention is directed to a circuit including a data relay stage configurable to receive primary data via a primary data interface, a primary clock having a frequency FP and a secondary clock having a frequency FS?. The primary data is received over a fixed periodic interval TI and at a rate substantially equal to FP. The amount of primary data received over TI is known to be N. The data relay stage is further configurable to provide secondary data via a secondary data interface based on the primary data and the secondary clock. The circuit also includes a phase-locked loop (PLL) circuit configurable to receive an interval reference signal having a frequency FI substantially equal to 1/TI. The PLL circuit is also configurable to provide the secondary clock based on the interval reference signal.

Abstract: A 3-dimensional image providing and receiving apparatus, 3-dimensional image providing and receiving methods using the same, and a 3-dimensional image system are provided. A 3-dimensional image receiving apparatus includes a phase conversion unit which converts phases of alternately output image signals, and a control unit which alternately blocks the image signals having the converted phases. Therefore, a viewer can view a 3-dimensional image output by a display apparatus having a polarization property without inconvenience in any positions.

Abstract: A display processor includes an interface unit, an instruction processor, a synchronization unit, at least one processing unit, and a device buffer. The interface unit receives input image data (e.g., from a main memory) and provides output image data for a frame buffer. The instruction processor receives instructions (e.g., in a script or list) and directs the operation of the processing unit(s). The synchronization unit determines the location of a read pointer for the frame buffer and controls the writing of output image data to the frame buffer to avoid causing visual artifacts on an LCD screen. The processing unit(s) may perform various post-processing functions such as region flip, region rotation, color conversion between two video formats (e.g., from YCrCb to RGB), up/down image size rescaling, alpha-blending, transparency, text overlay, and so on.

Abstract: An object of the present invention is to improve efficiency of transfer of control information, graphic data, and the like for drawing and display control in a graphic data processor. A graphic data processor includes: a CPU; a first bus coupled to the CPU; a DMAC for controlling a data transfer using the first bus; a bus bridge circuit for transmitting/receiving data to/from the first bus; a three-dimensional graphics module for receiving a command from the CPU via the first bus and performing a three-dimensional graphic process; a second bus coupled to the bus bridge circuit and a plurality of first circuit modules; a third bus coupled to the bus bridge circuit and second circuit modules; and a memory interface circuit coupled to the first and second buses and the three-dimensional graphic module and connectable to an external memory, wherein the bus bridge circuit can control a direct memory access transfer between an external circuit and the second bus.

Abstract: A graphics system includes a graphics memory. The graphics system includes a high performance mode and at least one power savings mode. A termination impedance and switching threshold of the graphics memory are selected based on an operating mode of the graphics system.

Abstract: To render graphics on multiple display devices, multiple computing platforms are networked and each computing platform separately executes an application to render graphics for a display device. A client computing platform adds an orientation offset to view state information received from a server computing platform to coordinate the graphics rendered by the server and client into a representation of the same world scene.

Abstract: Systems and methods for automatically switching scene modes of a monitor may comprise processes and corresponding modules for sending a request to a driver to activate hardware modules of a graphics processing unit (GPU) based on a requirement of a launched application program and then recording identifiers of the activated hardware modules on a list. A record of a scene mode associated with one or more activated hardware modules on the list is located within a scene mode profile table and then the corresponding monitor parameters previously associated with the scene mode are read. The monitor is then automatically adjusted according to the monitor parameters read.

Abstract: A computer implemented method, apparatus, and computer usable program code are provided for managing dual active controllers in a high availability storage configuration. Redundant dual active controllers in high availability storage configurations are made to appear as individual storage target devices to a host system. Each controller owns certain volumes of data storage. When a host system sends a request to identify available data volumes, the controller that owns certain volumes provides preferred paths to those owned volumes. The host system may also send an inquiry to a controller that asks the controller about data volumes not owned by the controller. For such inquiries, no paths to the non-owned data volumes are returned to the host system.

Abstract: A computer memory system (20) which comprises a media module (22); a host computer (24) configured to accommodate the media module (22) in removable fashion; and a display unit (26). The media module (22) is configured to store electronic data. The host computer (24) comprises a docking station (30) configured to accommodate the media module (22); an interface (32) through which electronic signals representing the electronic data are transmitted between the host computer (24) and the media module (22); an optical indicator (34); and a host processor (36). The host processor (36) is configured to control a read/write operation over the interface between the host computer (24) and the media module (22) and to activate the optical indicator (34) whereby the optical indicator (34) provides a first optical signal depicting transmission of electronic signals over the interface in the read/write operation.

Abstract: Systems, methods and computer readable media are disclosed for sending a client graphics data across a remote session for an application, where the application makes fixed function pipeline API calls and the client and server support shader pipeline API calls for the remote session. fixed function pipeline graphics calls from sent from the application are intercepted, wrapped, converted into their fixed function pipeline equivalent graphics call or calls and then sent across the communications network to the client according to a protocol of the remote session.

Abstract: Circuits, methods, and apparatus that are capable of processing graphics information and wirelessly transmitting processed graphics information to a monitor. In order to achieve a high bandwidth, one embodiment of the present invention provides a graphics processor chip that includes multiple RF transmitters such that processed graphics information can be transmitted using the cumulative bandwidth of multiple wireless channels. These transmitters can use one or more RF standards or proprietary signaling schemes.

Abstract: A PC-based computing system employing a bridge chip with a routing unit to distribute geometrical data and graphics commands to multiple GPU-driven pipeline cores supported on a plurality of graphics cards and the bridge chip. The PC-based computing system includes system memory for storing software graphics applications, software drivers and graphics libraries, and an operating system (OS), stored in the system memory, and a central processing unit (CPU) supported on a motherboard, for executing the OS, graphics applications, drivers and graphics libraries. The routing unit in the bridge chip interfaces with the CPU and the GPU-driven pipeline cores.

Abstract: A graphics processor is provided. The graphics processor includes a memory storing image data for presentation and a display memory region in communication with the memory, the display memory region supplying image data to a display panel for presentation. The graphics processor includes bandwidth control logic configured to monitor a lag between an output from the display memory region and an input into the display memory region. The bandwidth control logic is further configured to prevent a level of the display memory from decrementing when the lag between the output and the input is capable of causing corruption on the display panel due to a lack of data from the display memory region. A method for avoiding a buffer under run and a device are included.

Abstract: In a VESA standard compliant display controller having a processor arranged to process executable instructions and associated data, a memory device arranged to store EDID and the executable instructions and associated data, a number of data ports coupled to the memory device by way of an I2C data bus each coupled to a host device, a method of transferring EDID from the memory device over the I2C data bus to a requesting one of the data ports while servicing a processor memory access request without clock stretching.

Abstract: A transmission system for an image display device has a first circuit board and a second circuit board, a flexible member for connecting the first circuit board and the second circuit board, an image display driver IC mounted on the first circuit board or the flexible member, an image processing IC mounted on the second circuit board, and an optical transmission path. At least part of signals to be transmitted between the image display driver IC and the image processing IC is transmitted as an optical signal.

Abstract: A system and method for providing an Application Programming Interface (API) that allows users to write complex graphics and visualization applications with little knowledge of how to parallelize or distribute the application across a graphics cluster. The interface enables users to develop an application program using a common programming paradigm (e.g., scene graph) in a manner that accommodates handling parallel rendering tasks and rendering environments. The visualization applications written by developers take better advantage of the aggregate resources of a cluster. The programming model provided by APT function calls handles scene-graph(s) data in a manner such that the scene and data management are decoupled from the rendering, compositing, and display. As a result, the system and method is not beholden to one particular graphics rendering API (e.g. OpenGL, Direct X, etc.) and provides the ability to switch between these APIs even during runtime.

Abstract: A high performance graphics processing and display system architecture supporting a cluster of multiple cores of graphic processing units (GPUs) that cooperate to provide a powerful and highly scalable visualization solution supporting photo-realistic graphics capabilities for diverse applications. The present invention eliminates rendering bottlenecks along the graphics pipeline by dynamically managing various parallel rendering techniques and enabling adaptive handling of diverse graphics applications.

Abstract: Multiple systems and methods for accurately regenerating interlaced video signals that are transmitted using DSI is provided. In some embodiments, multiple types of VSYNC packets may be defined and used in encoding packets depending when the edge of a VSYNC pulse does or does not coincide with the start of a HSYNC pulse. These types of VSYNC packets may be distinguished in some embodiments by either create new VSYNC packet types, or encoding unused bits in existing DSI packets. In other embodiments, a filter may be used to detect and correct HSYNC frequency distortions caused during the regeneration of interlaced video signals decoded from DSI packets.

Abstract: A user interface includes at least one application element on a display of a device and at least indicative element associated with the at least one application element. The at least one indicative element is configured to vary at least one attribute in relation to a parameter of the at least one application element in order to reflect a degree of activity associated with an application linked to the at least one application element.

Abstract: A system and method for rendering a graphical setup display. A computer system comprises a first non-volatile storage device and a second non-volatile storage device. The first non-volatile storage device comprises a Basic Input/Output System (“BIOS”). The BIOS further comprises a BIOS graphical setup engine. The second non-volatile storage device comprises a setup image file containing a non-critical graphical setup image. The BIOS graphical setup engine selectively renders a basic graphical setup display omitting the non-critical image by using a set of pre-defined parameters stored in the first non-volatile storage device in place of the non-critical image if the non-critical image is not available, and renders an enhanced graphical setup display comprising the non-critical image contained in the setup image file stored in the second non-volatile storage device if the non-critical image is available.

Abstract: A repeater comprises an EDID memory to store a control data and a memory control unit. The memory control unit is configured to make access to the EDID memory to read the control data therefrom, store the read control data into the EDID memory and, when access is made to the EDID memory by the set-top box, transfer the control data stored in the EDID memory to the set-top box. In this case, the memory control unit outputs an inhibiting signal to a set-top box to inhibit it from making access to the EDID memory until the completion of an operation of storing the control data from the EDID memory in the set-top box into the EDID memory in the repeater.

Abstract: A repeater comprises an EDID memory to store a control data and a memory control unit. The memory control unit is configured to make access to the EDID memory to read the control data therefrom, store the read control data into the EDID memory and, when access is made to the EDID memory by the set-top box, transfer the control data stored in the EDID memory to the set-top box. In this case, the memory control unit outputs an inhibiting signal to a set-top box to inhibit it from making access to the EDID memory until the completion of an operation of storing the control data from the EDID memory in the set-top box into the EDID memory in the repeater.

Abstract: A method and apparatus are provided for providing a cockpit display in an aircraft. The method includes the steps of receiving a plurality of independent signals formatted for generating a cockpit image on a cathode ray tube of the aircraft, converting the received plurality of analog signals into an equivalent low voltage digital signal and displaying the cockpit image on a flat panel display of the aircraft using the equivalent low voltage digital signal.

Abstract: Disclosed is a wireless remote network management system for interfacing a series of remote devices (e.g., computers, servers, networking equipment, etc.) to one or more user workstations. The system is multifunctional to allow multiple users to control remote devices through serial access or keyboard, video, and cursor control device access via wireless and hard-wired connections. The remote devices are preferably coupled to a wireless-enabled remote management unit through a chain of computer interface modules, and each user workstation includes a wireless user station coupled to a keyboard, a video monitor and a cursor control device. The remote management unit and user stations preferably communicate via a wireless network, which enables a user workstation to access, monitor and control any of the remote devices.

Abstract: A PC-based computing system employing a silicon chip having a routing unit, a control unit and profiling unit for parallelizing multiple GPU-driven pipeline cores according to the object division mode of parallelization operation, during a graphics application. The PC-based computing system includes system memory for storing software graphics applications, software drivers and graphics libraries, and an operating system (OS), stored in the system memory, and a central processing unit (CPU), for executing the OS, graphics applications, drivers and graphics libraries. The system also includes a CPU/memory interface module and a CPU bus. The routing unit (i) routes the stream of geometrical data and graphic commands from the graphics application to one or more of the GPU-driven pipeline cores, and (ii) routes pixel data output from one or more of GPU-driven pipeline cores during the composition of frames of pixel data corresponding to final images for display on the display surface.

Abstract: A display is capable of displaying images in response to signals of a plurality of signal formats. The display includes a controller that is coupled to a plurality of image data interfaces. When the plurality of image data interfaces are simultaneously operating, the controller selects one of the plurality of image data interfaces according to preference variables associated with each of the plurality of image data interfaces. Each of the preference variables may indicate a relative priority of an image data signal format associated with the corresponding image data interface. In addition, each of the preference variables may indicate one or more performance metrics associated with the quality of image data signals received from the corresponding image data interface.

Abstract: The present invention sets forth an apparatus for supporting multiple digital display interface standards. In one embodiment, the apparatus includes a graphics processing unit (GPU) configured to determine a display device type of a display device that is in connection with a digital display interconnect, receive a display device information associated with the display device, and output a first data signal to the display device. The display device is of display port (DP) digital display interface standard and the digital display interconnect is of digital visual interface (DVI) digital display interface standard. The apparatus further includes a removable adaptor circuitry between the display device and the digital display interconnect.

Abstract: A high-speed ring topology. In one embodiment, two base chip types are required: a “drawing” chip, LoopDraw, and an “interface” chip, LoopInterface. Each of these chips have a set of pins that supports an identical high speed point to point unidirectional input and output ring interconnect interface: the LoopLink. The LoopDraw chip uses additional pins to connect to several standard memories that form a high bandwidth local memory sub-system. The LoopInterface chip uses additional pins to support a high speed host computer host interface, at least one video output interface, and possibly also additional non-local interconnects to other LoopInterface chip(s).

Abstract: PC-based computing system having an integrated graphics subsystem supporting parallel graphics processing operations across a plurality of different graphics processing units (GPUs) supplied from the same or different vendors. The graphics subsystem include a graphics controller hub (GCH) chip located on a CPU bus, and having Multi-Pipeline Core Logic (MP-CL) circuitry including a routing unit and a control unit. The plurality of different GPUs are interfaced with the GCH chip. Each different GPU supports a GPU-driven pipeline core having a frame buffer (FB) for storing a fragment of pixel data. The GPU-driven pipeline cores are arranged in a parallel architecture and operated according to a parallelization mode of operation, so that said GPU-driven pipeline cores process data in a parallel manner.

Abstract: A PC-based computing system capable of displaying images of 3-D objects during an interactive process between said computing system and a user thereof. The PC-based computing system includes a system memory for storing software graphics applications, software drivers and graphics libraries, and an operating system (OS), stored in the system memory, and a central processing unit (CPU), for executing the OS, graphics applications, drivers. and graphics libraries. The system also includes an CPU interface module, a PC bus, a graphics processing subsystem interfaced with the CPU interface module by way of the PC bus, and a display surface for displaying said images by graphically displaying frames of pixel data produced by the graphics processing subsystem. The graphics processing subsystem includes a plurality of GPUs arranged in a parallel architecture and operating according to a parallelization mode of operation so that the GPUs support multiple graphics pipelines and process data in a parallel manner.

Abstract: Methods and device for in-system firmware update in an information output device are provided. In one aspect, a method of firmware update in a display device receives a set of data in an image format through a video signal input channel of an input port of the display device. The set of data is converted from the image format to an instruction set format that is different from the image format. A first set of instructions that is used to operate the display device is updated with the set of data in the instruction set format.

Abstract: A graphics hub subsystem for interfacing parallelized graphics processing units (GPUs) with the CPU of a PC-based computing system having a CPU interface module and a PC bus. The PC-based computing system includes system memory for storing software graphics applications, software drivers and graphics libraries, and an operating system (OS), stored in the system memory, and a central processing unit (CPU), for executing the OS, graphics applications, drivers. and graphics libraries. The graphics hub subsystem includes a hardware hub having a hub router for interfacing with the CPU interface module and the GPUs by way of the PC bus, distributing the stream of geometrical data and graphic commands among the GPUs, and transferring pixel data output from one or more of the GPUs during the composition of frames of pixel data corresponding to final images for display on the display surface. The subsystem also includes one or more software hub drivers, stored in the system memory.

Abstract: Apparatus and methods are disclosed for controlling the memory controller and, in particular, controlling signaling of the memory controller to a memory via memory interface during a static screen condition. An apparatus includes static image detection logic that is configured to detect when image data being displayed by a display controller is static and to communication detection of static image data to the display controller. The apparatus also includes control logic within the display controller responsive to the static image detection logic, where the control logic is configured to detect a level of a line buffer within the display controller and to send a signal to a memory controller directing the memory controller to issue a signal to a memory to enter a self-refresh mode, thereby turning off at least one memory clocking circuit within the memory controller. A corresponding method is also disclosed.

Abstract: An improved graphics processing system and method are described for magnifying visual output information for printing, display, or other output. A graphics engine transforms display information so as to magnify one or more components or areas of an output image for display via output hardware such as a screen or printer. Magnification parameters are supplied to the graphics engine by one or more magnification applications. In an embodiment of the invention, the graphics engine performs compositing of magnified and unmagnified content for display. In an alternative embodiment, the graphics engine outputs corresponding scaled image material to the appropriate magnification application for rendering. In a further embodiment, the graphics engine may operate in both modes.

Abstract: A PC-based computing system capable of displaying images of 3-D objects during an interactive process between said computing system and a user thereof. The PC-based computing system includes system memory for storing software graphics applications, software drivers and graphics libraries, and an operating system (OS), stored in the system memory, and a central processing unit (CPU), for executing the OS, graphics applications, drivers. and graphics libraries. The system also includes an CPU interface module and a PC bus, a graphics processing subsystem interfaced with the CPU interface module by way of the PC bus, and a display surface for displaying said images by graphically displaying frames of pixel data produced by the graphics processing subsystem.

Abstract: A method of providing a PC-based computing system with parallel graphics processing capabilities, wherein the PC-based computing system includes (i) system memory (ii) an operating system (OS, (iii) one or more graphics applications, stored in said system memory, (iv) one or more graphic libraries, (v) a central processing unit (CPU) for executing the OS, graphics applications, drivers and graphics libraries, (vi) an CPU interface module for interfacing with the CPU, (vii) a PC bus, and (viii) a display surface for displaying images of 3D objects. The method involves interfacing a hardware hub having a hub router, with the CPU interface module using the PC bus. The hardware hub is interfaced with a plurality of graphic processing units (GPUs), using the PC bus, so that the GPUs are arranged in a parallel architecture and operating according to a parallelization mode of operation so that the GPUs support multiple graphics pipelines and process data in a parallel manner.

Abstract: A PC-based computing system capable of displaying images of 3-D objects during an interactive process between said computing system and a user thereof. The PC-based computing system includes a graphics processing subsystem having a plurality of GPUs arranged in a parallel architecture and operating according to an object division mode of parallel operation so that each GPU supports a graphics pipeline for processing data in a parallel manner according to the object division mode. A hardware hub, interfaces with a CPU interface module and the GPUs, and has a hub router for (i) distributing the stream of geometrical data and graphic commands among the GPUs, and (ii) transferring pixel data output from one or more of GPUs during the composition of frames of pixel data corresponding to final images for display on the display surface. A CPU interface module provides an interface between one or more software hub drivers and the hardware hub.

Abstract: A multi-GPU graphics processing subsystem for installation in a PC-based computing system having a CPU and a CPU interface module including a PC bus. The graphics processing subsystem interfaced with the CPU interface module by way of the PC bus, and a display surface for displaying said images by graphically displaying frames of pixel data produced by the graphics processing subsystem. The graphics processing subsystem includes a plurality of GPUs arranged in a parallel architecture and operating according to a parallelization mode of operation so that each GPU supports a graphics pipeline and is allowed to process data in a parallel manner.

Abstract: An information notification method includes coding information by a first information processing apparatus, displaying the coded information on a screen of the first information processing apparatus, obtaining displayed coded information as image information by a second information processing apparatus having an image-capturing unit, transmitting the obtained image information to a third information processing apparatus from the second information processing apparatus, receiving at the third information processing apparatus the image information transmitted from the second information processing apparatus, and decoding by the third information processing apparatus the received image information so as to obtain the coded information.

Abstract: The present invention is directed to improvements on display hardware and/or user presentation interface systems for audience gathering places, such as theatres, stadiums, cinemas and auditoriums. The display hardware relates to the equipment used to distribute communications (such as advertising and audience feedback) throughout the audience gathering place and to (at least some of) the individual members of the audience. The user presentation interface systems involve the substance of the communications that are actually made to and/or from audience members. In this document the focus will be on theatre applications.

Abstract: A method and apparatus for combining video graphics processing and audio processing onto the same single chip and/or printed circuit board includes a graphics processing circuit, an audio processing circuit, a local bus, and a bus arbitrator. The local bus couples both the graphics processing circuit and audio processing circuit to the system bus such that each of the circuits may transceive data with the system bus. The bus arbitrator arbitrates access to the local bus between the graphics processing circuit and audio processing circuit. Such arbitration is based on incoming data, which is interpreted and, based on the interpretation, the bus arbitrator routes the incoming data to either the graphics processing circuit or the audio processing circuit. In addition, the bus arbitrator arbitrates outputting data from the graphics processing circuit and the audio processing circuit based on commands received from the CPU.

Abstract: A remote unit includes: a receiving part that receives image signals superimposed on other signals via a first network; an outputting part that outputs the image signals to a second network; a separating part that separates the image signals from the other signals; and an adjusting part that adjusts delays of the image signals.

Abstract: The invention provides a motherboard that uses a high-speed, scalable system bus such as PCI Express® to support two or more high bandwidth graphics slots. The lanes from the motherboard chipset may be directly routed to two or more graphics slots. For instance, the chipset may route (1) thirty-two lanes into two ×16 graphics slots; (2) twenty-four lanes into one ×16 graphics slot and one ×8 graphics slot (the ×8 slot using the same physical connector as a ×16 graphics slot but with only eight active lanes); or (3) sixteen lanes into two ×8 graphics slots (again, physically similar to a ×16 graphics slot but with only eight active lanes). Alternatively, a switch can convert sixteen lanes coming from the chipset root complex into two ×16 links that connect to two ×16 graphics slots. The system according to the invention is agnostic to a specific chipset.

Abstract: An image display system with one or more client computers in selective communication with a visual server having image processing capabilities. The client computer generates image modifying data corresponding to a generated image, and transmits the data to the visual server. The visual server receives the image-modifying data, generates a modified image based upon the image-modifying data, and transmits the modified image as compressed data to the client. The client decompresses the modified image data and displays the modified image. In the system, the visual server and client can provide a sequential display of modified frames on client to support animation with complex 3-dimensional graphics.

Abstract: An image display apparatus includes: an external apparatus connecting unit that is connected with a plurality of image supply apparatuses and receives a plurality of data transmitted from the image supply apparatuses; an output unit that outputs an image based on the data to a display unit; an operation unit that accepts an input operated by a user; and a control unit that outputs, when an instruction to designate the image supply apparatus that outputs the data to be displayed in the display unit is input by the user via the operation unit, a suspension request signal requesting the suspension of supply of the data to the image supply apparatuses other than the image supply apparatus designated by the user.

Abstract: An information processing apparatus includes a storage unit configured to store information representing a plurality of screens in each of a plurality of groups to which priorities are previously set, a determination unit configured to determine a group which is assigned the highest priority, and a control unit configured to display on a display unit a representative screen of the group assigned the highest priority.

Abstract: A display having data lines that can be configured between a display mode and a touch mode is disclosed. The display can have sense regions for sensing a touch or near touch on the display during the touch mode. These same regions can display graphics or data on the display during the display mode. During display mode, the data lines in the sense regions can be configured to couple to display circuitry in order to receive data signals from the circuitry for displaying. During touch mode, the data lines in the sense regions can be configured to couple to corresponding sense lines in the regions, which in turn can couple to touch circuitry, in order to transmit touch signals to the circuitry for sensing a touch or near touch. Alternatively, during touch mode, the data lines in the sense regions can be configured to couple to ground in order to transmit residual data signals to ground for discarding.