Abstract: One embodiment of a connector for a stand-alone graphics module is adapted for coupling a computing device to the stand-alone graphics module, which is external to the computing device. The connector is adapted for receiving a PCI express signal from the computing device and for delivering the PCI express signal to the stand-alone graphics module. The connector is further adapted for receiving display output signals from the stand-alone graphics module and delivering the display output signals to the computing system, e.g., for use in accordance with one or more output display panels coupled to said computing device.

Abstract: A graphic card includes a graphic chip, an output port and a transforming apparatus. The graphic chip outputs an image signal. The transforming apparatus receives the image signal and an audio signal provided by an external source and integrates them into a video signal. And then the transforming apparatus transmits the video signal to the output port.

Abstract: An apparatus for image data computation and for synchronous data output. An arrangement for producing and reproducing two partial light images which together can be perceived as a light image having a three-dimensional effect. A method of synchronous reproduction of time image sequences by at least two image reproduction devices. The apparatus according to an embodiment of the present invention has a master-client structure. A graphics master unit and at least two graphics clients are connected together by way of a first message channel and by way thereof exchange first messages, such that computation and projection of the partial images is synchronized.

Abstract: A method and system for converting the output of a communications port (e.g., a serial port or a USB port) into video signals representing the output of a terminal using a KVM switch. Upon receiving characters from the communications port, the system interprets the characters as terminal emulation commands and internally generates a representation of what a resulting terminal screen would look like. From that internal (digital) representation, the system produces analog outputS representing the terminal screen. The analog outputs are output on the monitor attached to the KVM switch.

Abstract: A video output system with co-layout structure includes an internal video graphics array (VGA) interface, an external VGA interface and a video output interface. The two VGA interfaces are connected to a connection point through individual leads respectively, then to the video output interface at the connection point through a common lead. The video output system further includes two switches disposed between the internal VGA interface and the connection point and between the external VGA interface and the connection point respectively for blocking the signal stub from flowing to the two VGA interfaces, thereby enhancing the signal quality.

Abstract: According to one embodiment, an information processing apparatus including a connector, a determination unit configured to determine whether a display device, which is connected via the connector, is adaptive to an underscan display scheme or an overscan display scheme, and a setting unit configured to set one of underscan and overscan as an output scheme of display data to the display device, based on a determination result by the determination unit.

Abstract: A method for detecting an inappropriate video connection in an information handling system (“IHS”) that includes an integrated video controller, the integrated video controller operable to be coupled to a display device, is provided. The method includes determining if an add-in video controller is coupled to the IHS, the add-in video controller operable to be coupled to the display device. The method also includes determining whether the display device is coupled to the integrated video controller or the add-in video controller. The method further includes providing a notification that the display device is inappropriately coupled to the IHS if it was determined that both the add-in video controller is coupled to the IHS and the display device is coupled to the integrated video controller.

Abstract: A network switch for network communications includes a first data port interface, wherein the first data port interface supports a plurality of data ports for transmitting and receiving data at a first data rate. The network switch also includes a second data port interface, wherein the second data port interface supports a plurality of data ports for transmitting and receiving data at a second data rate, along with a third data port interface for transmitting and receiving data at a third data rate. A CPU interface is provided and configured to communicate with a CPU. The switch includes a first, second and third internal memory communicating with the first, second and third data port interface. A first and second memory management unit for communicating data and to control access to and from the second internal memory, are also provided. A communication channel is provided for communicating data and messaging information.

Abstract: Multiple data streams are distributed using conventional data cables and multiplexing circuits by taking advantage of a technique that allows reliable high speed transmission of digital data. In one example, a number of parallel data streams (e.g., video data streams) are serialized to allow them to be economically and reliably transmitted over conventional data cables (e.g., category 5 or category 6 twisted pair cables, and automotive data transmission cables) over long distance. The parallel data streams are recovered by deserializing from the transmitted signal using a data recovery technique that recovers a clocking signal from the transmitted signal. In another example, multiple data streams from multiple asynchronous sources are multiplexed to provide an input data stream to a display device. The multiple data stream may be provided through, for example, conventional connection cables (e.g., DVI, LEONI, CATS or CAT6 cables).

Abstract: A graphical user interface (GUI) for medical instruments for a Renal Replacement Therapy that enables an operator to select and review a series of settings for an extracorporeal pump console and implement the settings in batch manner. The GUI automatically adjusts or recommends dependent settings, e.g. filtration rate, as the user adjusts primary settings, e.g. blood flow rate.

Abstract: An interface unit, a device with the interface unit and a process for generating an image signal containing color image data is provided for activating a color monitor from an image signal containing monochrome image data. The interface unit has an input terminal (16), an output terminal (17) and a processor (18) coupled between the input terminal (16) and the output terminal (17). This processor (18) is set up to receive, via the input terminal (16), a first image signal issued by a monitor activating device (1) of an apparatus for activating a monochrome monitor. The signal contains monochrome image data, at least a part of which represents a number of graphic objects (9, 10), and which is set up to activate a monochrome monitor, such that the graphic objects (9, 10) are displayed on this monitor. One or more colors are assigned to each graphic object (9, 10) by the processor (18) on the basis of a predetermined dependence stored in this processor (18).

Abstract: A digital visual interface apparatus includes a digital visual interface, a first memory, a second memory, and a switch unit. A transmission mode of the digital visual interface apparatus includes a digital mode and an analog mode. The first memory and the second memory are respectively used for storing the extended display identification data (EDID) in the digital mode and the analog mode. Wherein, the switch unit provides an operating voltage to the first memory when the transmission mode of the digital visual interface apparatus is in the digital mode, and the switch unit provides an operating voltage to the second memory when the transmission mode of the digital visual interface apparatus is in the analog mode.

Abstract: A display control device includes a controller, a scaling engine, a timing controller, a selector and an interface circuit. The controller is for providing a mode-control signal. The scaling engine is for producing a first interface signal. The timing controller is for converting the first interface signal into a second interface signal. The selector selects either the first interface signal or the second interface signal to serve as a reference signal according to the mode-control signal. The interface circuit converts the reference signal into an output signal according to the mode-control signal. When the mode-control signal is under a first mode, the output signal is virtually the first interface signal. When the mode-control signal is under a second mode, the output signal is virtually the second interface signal. When the mode-control signal is under a third mode, the interface circuit converts the first interface signal into a third interface signal to serve as the output signal.

Abstract: One embodiment of a field changeable rendering system includes an output device interfaced to a motherboard, a fixed rendering device mounted to the motherboard for generating information to be output on said output device, a connector for attaching a field-changeable rendering card to the motherboard, said field-changeable rendering card capable of housing a discrete rendering device for generating information to be output on said output device and detection circuitry for detecting that a field-changeable rendering card housing a discrete rendering device is coupled to said connector and causing information from said field-changeable rendering card housing a discrete rendering device to be output on said output device. One advantage of the disclosed edge connector is that it is compatible with a plurality of graphics cards and systems, thereby enabling a computing device user to upgrade the existing device's graphics system.

Abstract: In some embodiments, a device includes a bus, a parallel source, and a parallel sink. The parallel source is to provide parallel groups of signals including video signals to the bus, wherein the bus has a number of lanes that is fewer than a number of signals used to represent a pixel such that pixels are represented in more than one of the parallel groups. The parallel sink is to receive the parallel groups of signals from the bus, wherein the parallel sink includes a signal extractor to separate at least a portion of the groups of signals into multiple channels, and encoder and serializer circuits to encode and serialize the separated signals. Other embodiments are described and claimed.

Abstract: The subject invention relates to a Universal Graphics Adapter (UGA) that is a hardware-independent design that encapsulates and abstracts low-level graphics hardware in a standard manner through firmware. UGA is a firmware standard, intended to wrap existing or planned hardware, including VGA. UGA does not require the use of real-mode assembly language, direct hardware register, or frame buffer access to program, thus providing advantages over conventional systems. UGA supports basic drawing operations, continuous display modes, and power management. As a firmware-based standard, UGA facilitates updating a system to support both evolving and new hardware features.

Abstract: A portable computer including a display unit, and a video processor generating and supplying a first video signal to the display unit, includes a video adaptor outputting the first video signal to the outside, and receiving a second video signal from an external input source, and a control unit for supplying the second video signal to the display unit when the external input source is connected to the video adaptor. Thus, the present invention provides a portable computer and a control method, which can receive a video signal from an external input source through one existing output port for outputting a video signal without adding a separate input port.

Abstract: A controller for switching the operation state of a transmitter portion sets a transmitter portion in which the data amount to be transmitted is larger than a predetermined amount to a high speed mode, sets a transmitter portion in which the data amount to be transmitted is below a predetermined amount and larger than zero to a low speed mode, and sets a transmitter portion in which the data amount to be transmitted is equal to zero to a sleep mode. The power consumption in the transmitter portion in which the data amount to be transmitted is small and the transmitter portion in which the data amount to be transmitted is equal to zero can be suppressed and thus the power consumption can be reduced.

Abstract: An image forming apparatus having an operation improved in view of use of normal healthy persons and handicapped persons. The image forming apparatus comprising an operation panel having a display and an input section, has: a specifying section for specifying whether a user is a normal healthy person or a handicapped person; a storage for storing an operation function when the normal healthy person uses the apparatus, and an operation function when the handicapped person uses the apparatus; and an operation function changing section for reading a corresponding operation function out of the storage, and changing an operation function of the operation panel according as the normal healthy person or the handicapped person is specified by the specifying section.

Abstract: One embodiment of an edge connector for a field changeable graphics system includes a right angle edge connector having a plurality of contact pins adapted to engage contacts on a graphics card. The edge connector is adapted to interface the graphics card with the motherboard of a computing device, without directly mounting the graphics card to the motherboard. One advantage of the disclosed edge connector is that it is compatible with a plurality of graphics cards and systems, thereby enabling a computing device user to upgrade the existing device's graphics system. Thus, the user is not forced to purchase an entirely new computing device in order to take advantage of graphics innovations. A further advantage of the disclosed edge connector is that it enables upgrades to low voltage differential signaling (LVDS) features, without the need for additional costly devices capable of operating at LVDS data rates.

Abstract: A video signal circuit of a notebook computer includes a north bridge chipset, a control module, a VGA port, an A/D converter, a selection module, and a control unit. The north bridge chipset is coupled to the control module and the selection module. The VGA port is coupled between the control module and a display device and a processing device. The A/D converter is coupled between the control module and the selection module. The selection module is coupled to an LCD of the notebook computer. The control unit is coupled to the selection module and the control module. The video signal circuit can be controlled to send a first analog and digital video signals generated by the north bridge chipset to the displaying device and the LCD respectively, or receive a second analog video signal from the processing device and display it on the LCD.

Abstract: An improved raster engine adapted to render video data from a frame buffer to one of a plurality of disparate displays is disclosed which comprises apparatus for detecting one or more video underflow conditions. The raster engine includes a first in first out (FIFO) memory, which obtains video data from a frame buffer and provides video data to a video pipeline, along with input and output counters associated with the FIFO memory. A control logic system is associated with the FIFO memory and adapted to provide an underflow indication according to the input and output counter values. A method for detecting video underflow in a video controller raster engine is also disclosed.

Abstract: The present invention provides data processing technology for making two or more processing units cooperate with one another such that output data from respective groups of processing units (GSM) are merged by a respective sub-MG (merger), data from the sub-MGs are merged by a main MG, and the merged output data are displayed on a display unit. Each GSM initiates drawing processing assigned thereto in response to the reception of a drawing enable signal and, after execution of the processing, outputs a drawing end signal. The GSMs to which the drawing enable signal is to be sent, and the GSMs from which the drawing end signal is to be received, are set for each application. A main SYNC sends the drawing enable signal to corresponding GSMs in the order of setting for an application in response to the reception of a processing request from the application, while it receives the drawing end signal from the corresponding GSMs so that the processing results of the GSMs will be displayed on the display unit.

Abstract: Commercial printers operate more efficiently when they run continuously after being started on a print job. Print job image data is processed by a predetermined number of raster image processors (RIP engines) before starting a printer so as to be able to operate a printer continuously for the duration of the print job. Print job partitions are determined and counted. A predetermined number of partitions are processed into hardware ready bit (HRB) output files which are transferred to the printer. Using a predetermined formula, the total number of partitions to process is calculated before sending resultant HRB output files to said printer. Remaining partitions are processed into HRB files by at least one of the RIP engines until all partitions have been processed.

Abstract: Methods and apparatus for use with AGP-capable computer systems are disclosed. Since each AGP-capable chipset can have a unique range of graphics port aperture sizes that it supports, current graphics port aperture drivers are chipset-specific, with hard-coded tables of supported graphics aperture sizes. Described herein is a driver that dynamically ascertains the range of supported graphics aperture port sizes for an attached AGP-capable chipset, thus allowing this driver to be ported between different chipsets without manual reconfiguration and recompiling. The method employed in the driver sends one or more test aperture size values to a register resident in the chipset, and then reads what is written to see if the chipset changed any of the bits of the test value. The method infers supported sizes from examining which, if any bits, were changed by the chipset.

Abstract: According to one embodiment a chipset is disclosed. The chipset includes a graphics accelerator, a memory controller and a queue mechanism. The queue mechanism includes a first functional unit block (FUB) coupled to the graphics accelerator, and a second FUB coupled to the memory controller.

Abstract: A system and method are provided for directing the flow of data and instructions into at least one functional unit. In one embodiment of a system of components defining a plurality of nodes, a queue network manager (QNM) forming a part of each node, is provided. In this embodiment, the QNM comprises an interface to a network that supports intercommunication among the plurality of nodes, an interface configured to pass messages with a functional unit within the node, a random access memory (RAM) configured to store at least one of a message and a programmable instruction, and logic configured to control an operational aspect of a functional unit based on contents of the programmable instruction.

Abstract: A receiver for recovering a serial clock of a transmitter is provided. The receiver comprises a buffer configured to store packets received from the transmitter. The packets may be sent through a packet switched network that may incur packet delay during transmission through the network. A memory controller is configured to determine a fill level of the buffer. A frequency generator is configured to generate a clock frequency, where the frequency is used to determine when to read packets from the buffer. A frequency controller is configured to instantaneously adjust the frequency of the frequency generator based on an algorithm that determines the clock frequency based on the fill level of the buffer. Accordingly, by adjusting the frequency outputted by the frequency generator, the frequency controller is able to recover the serial clock of the transmitter.

Abstract: A display for sharing the display data channel is provided. The display shares the display data channel and thus the preexisting display data channel can be used as the interface for RS232 or I2C communication for performing the ISP or adjustment of the firmware. Hence, it can simplify the manufacturing tools, enhance the manufacturing efficiency, and allow the users to update the firmware by themselves.

Abstract: Method and interface for sending vertex data output from a vertex processing unit to memory is described. Conventionally, the vertex data output is not output directly to memory via a dedicated write interface, but is instead passed through downstream computation units in a graphics processor and written to memory via the write interface normally used to write pixel data. When the downstream computation units are configured to pass the vertex data output through unmodified, processing of the vertex data output by the downstream computation units is deferred until a second pass through those units. When the vertex data output is output directly to memory, processing of the vertex data output by the downstream computation units can be initiated during a first pass through those units.

Abstract: A display is capable of displaying images in response to signals of a plurality of signal formats. The display includes a controller that is coupled to a plurality of image data interfaces. When the plurality of image data interfaces are simultaneously operating, the controller selects one of the plurality of image data interfaces according to preference variables associated with each of the plurality of image data interfaces. Each of the preference variables may indicate a relative priority of an image data signal format associated with the corresponding image data interface. In addition, each of the preference variables may indicate one or more performance metrics associated with the quality of image data signals received from the corresponding image data interface.

Abstract: An apparatus and method for performing an insert-extract operation on packed data using computer-implemented steps is described. In one embodiment, a first data operand having a data element is accessed. A second packed data operand having at least two data elements is then accessed. The data element in the first data operand is inserted into any destination field of a destination register, or alternatively, a data element is extracted from any field of the source register.

Abstract: A core logic circuit which works with a CPU and a main graphics accelerator in a computer system is provided. The core logic chip includes a host controller electrically connected to the CPU for receiving a command from the CPU; an auxiliary graphing engine electrically connected to the host controller for receiving and processing the command; and a transmission controller electrically connected to the auxiliary graphing engine for transmitting the command that is processed and outputted by the auxiliary graphing engine to the main graphics accelerator to be further processed.

Abstract: A graphics processor or display device including a microcontroller that functions as a sequencer, a computer system including at least one such graphics processor or display device, and a microcontroller for use in such a graphics processor or display device. In preferred embodiments, the microcontroller functions as a sequencer for controlling the timing of power up and/or power down operations by one or both of a graphics processor and a display device. The microcontroller is implemented to exclude any capacity to handle interrupts and so can provide guaranteed timing, and is preferably implemented to be small, simple, and programmable, and to store a small number of programs. Each program consists of instructions belonging to a small instruction set, such as a set consisting of set and clear instructions (for overriding or overwriting specified register bits) and wait, release, and stop instructions.

Abstract: A memory controller hub includes a graphics subsystem adapted to perform graphics operations on data, and interface circuitry adapted selectively to couple the graphics subsystem to a local memory through electrical connectors and to couple the memory controller hub to a graphics controller through the electrical connectors.

Abstract: A graphics display controller providing enhanced read/write efficiency for interfacing with a RAM-integrated graphics display device. According to the invention, a graphics display controller is disclosed for interfacing between a host and a graphics display device having an associated memory is provided that includes an embedded memory, a format converter, and a data storage memory. The embedded memory is adapted for storing frames of video data received from a host. The format converter is adapted to convert the video data in at least one of two ways: (1) from the data format of the host to the data format of the display device and (2) from the data format of the display device to the data format of the host. The data storage memory has a memory size that is smaller than the embedded memory, and defines a data path that bypasses the embedded memory but connects to the format converter.

Abstract: A method for managing host system power consumption is provided. The host system includes host memory and external memory. The method initiates with providing a processor in communication with a memory chip over a bus. The memory chip is external memory. Then, a usage measurement of the external memory is determined. If the usage measurement is below a threshold value, the method includes copying data from the memory chip to the host memory and terminating power to the memory chip. In one embodiment, the power is terminated to at least one bank of memory in the memory chip. In another embodiment, an amount of reduction of the external memory can be determined rather than a usage measurement. In yet another embodiment, an address map is reconfigured in order to maintain a contiguous configuration. A graphical user interface and a memory chip are provided also.

Abstract: In an image processing apparatus for processing image data in either operation mode of a full color mode or a monochromatic mode having processing speed higher than the full color mode, at least a part of an image processing circuit comprises a rewritable device such as a field gate programmable array. A controller rewrites an internal circuit in the rewritable device according as the operation mode is the full color mode or the monochromatic mode. The internal circuit in the rewritable device rewritten in the monochromatic mode performs processing based on pixel clock faster than in the full color mode.

Abstract: The graphics display architecture provided by the present invention comprises an AGP slot, a PCIE slot, and a control chip set. The control chip set comprises a plurality of multi-defined pins, which are electrically coupled to the first pins of the AGP slot and the second pins of the PCIE slot simultaneously. When the first graphics adapter is plugged in the AGP slot and the first graphics adapter complies with AGP interface specification, the multi-defined pins serve to send/receive the signal complied with AGP interface specification. When the first graphics adapter is plugged in the AGP slot and the first graphics adapter complies with the Gfx interface, the multi-defined pins serve to send/receive the signal complied with the Gfx interface. When the second graphics adapter is plugged in the PCIE slot, the multi-defined pins serve to send/receive the signal complied wit the PCIE interface specification.

Abstract: A graphics display system is disclosed. The display system comprises a plurality of heads. Each of the plurality of heads includes a VGA controller and each of the plurality of heads is adapted for a display. The graphics display system also includes a host coupled to the plurality of heads, wherein all the standard VGA settings for each of the plurality of the heads could be programmed by a single command by the host. Each of the heads are adapted for a display. A system and method for providing a broadcast mode VGA feature is disclosed. A method and system in accordance with the present invention includes one VGA controller per head. In so doing, in a broadcast mode a write transaction from the bus is broadcast or written to both heads. Also, in a broadcast mode, the VGA read data from the bus always comes from one of the heads. The output timing registers specific to a non-CRT output are not broadcast.

Abstract: A method for communicating digital display data and associated auxiliary processing data from a frame buffer to a post processor. The method includes storing the display data and the auxiliary processing data in the frame buffer, forming video scan lines from the frame buffer by handling both the display data and the auxiliary processing data as video data, and transferring the video scan lines over a digital video interface to a post-processor.

Abstract: A visual tree structure as specified by a program is constructed and maintained by a visual system's user interface thread. As needed, the tree structure is traversed on the UI thread, with changes compiled into change queues. A secondary rendering thread that handles animation and graphical composition takes the content from the change queues, to construct and maintain a condensed visual tree. Static visual subtrees are collapsed, leaving a condensed tree with only animated attributes such as transforms as parent nodes, such that animation data is managed on the secondary thread, with references into the visual tree. When run, the rendering thread processes the change queues, applies changes to the condensed trees, and updates the structure of the animation list as necessary by resampling animated values at their new times. Content in the condensed visual tree is then rendered and composed. Animation and a composition communication protocol are also provided.

Abstract: The invention provides systems, devices, and methods for using more than one Accelerated Graphics Port (AGP) to process graphics for a single computer monitor (282). In one embodiment, the invention is a method of providing advanced/high-performance AGP capabilities to a laptop computer by intercepting AGP signals from a laptop having a low-power AGP (224) and converting the AGP signals to signals for a high-performance AGP (270).

Abstract: A disclosed coprocessor receives a user-defined command during execution of an instruction including the user-defined command, and performs a predetermined function in response to the user-defined command. The user-defined command includes multiple ordered bits having values assigned by a user. In one embodiment, the coprocessor includes logic coupled to receive the user-defined command and a datapath. The logic produces a control value in response to the user-defined command. The datapath receives data and the control value, and performs the predetermined function dependent upon the control value. In one embodiment, the predetermined function is a motion estimation function. Data processing systems are described including a processor coupled to the coprocessor. Another disclosed data processing system includes an arbiter coupled between a processor and multiple coprocessors.

Abstract: An architecture for storing, addressing and retrieving graphics data from one of multiple memory controllers. In a first embodiment of the invention, one of the memory controllers having an accelerated graphics port (AGP) includes a set of registers defining a range of addresses handled by the memory controller that are preferably to be used for all AGP transactions. The AGP uses a graphics address remapping table (GART) for mapping memory. The GART includes page table entries having translation information to remap virtual addresses falling within the GART range to their corresponding physical addresses. In a second embodiment of the invention, a plurality of the memory controllers have an AGP, wherein each of the plurality of the memory controllers supplies a set of registers defining a range of addresses that is preferably used for AGP transactions.

Abstract: An interface for a graphics system includes simple yet powerful constructs that are easy for an application programmer to use and learn. Features include a unique vertex representation allowing the graphics pipeline to retain vertex state information and to mix indexed and direct vertex values and attributes; a projection matrix value set command; a display list call object command; and an embedded frame buffer clear/set command.

Abstract: A computer program product for a computer system includes code that directs a processor to display a two-dimensional representation of a three-dimensional object on a display, wherein the two-dimensional representation comprises a plurality of two-dimensional regions, wherein the three-dimensional object is associated with a plurality of components in a component hierarchy, and wherein each two-dimensional region is associated with at least one component from the plurality of components, code that directs the processor to receive a selection of a two-dimensional region from the user on the display, code that directs the processor to determine a component from the plurality of components associated with the two-dimensional region, code that directs the processor to receive a value for an animation variable associated with the component, and code that directs the processor to set the animation variable associated with the component to the value, wherein the codes reside on a tangible media.

Abstract: A personal computer system includes a core logic unit, a graphics accelerator, a first tile converter, a local memory, a second tile converter and a system memory. The core logic unit outputs first image data in a linear mode. The graphics accelerator is in communication with the core logic unit for processing the first image data into second image data in a linear mode. The first tile converter is in communication with the graphics accelerator for converting the second image data into third image data in a tile mode. The local memory is in communication with the first tile converter for storing therein the third image data. The second tile converter is in communication with the core logic unit for converting the first image data into fourth image data in a tile mode. The system memory is accessible by the core logic unit, and includes a graphics accelerating memory in communication with the second tile converter for storing therein the fourth image data.

Abstract: A user interface having a plurality of user interface elements including: background, passive elements such as frames and borders, information display elements that present information from application software operating on the control unit, and control elements that cause application software operating on the control unit to initiate programmed behaviors. The user interface as a whole is contextually sensitive in that the appearance of user interface elements (e.g., color, size, font, contrast, order, grouping, arrangement, etc.) and/or the behavior of user interface elements are varied in a manner that is dependent on the context of the control unit. The context of the control unit is represented by state information known to the control unit, which includes context-specific state information known to a particular control unit as well as global context information known to multiple or all control units in a system.

Abstract: A Memory Interface and Video Attribute Controller (MIVAC) is inserted between a dynamic RAM (DRAM) capable of a consecutive data read operation, such as the operation associated with the static column mode, page mode, or nibble mode, and a graphic processor to provide a parallel data processing. A serial data transfer is executed on each data bus between the MIVAC and the DRAM, whereas parallel data transfer is conducted between the MIVAC and the graphic processor. As a result, the graphic processor can be configured with a reduced number of DRAMs so that the graphic processor operates without paying attention to the consecutive data read mode of the DRAM.