Abstract: The present disclosure provides a backlight module and a display device. The backlight module includes a control circuit, a power chip, and light emitting devices. The control circuit include a control signal input terminal, and when the control signal input terminal is in a suspended state, the control circuit can output an enable signal. An enable pin of the power chip receives the enable signal, so that the power chip controls an output of a power supply voltage under a control of the enable signal. The light emitting components receive the power supply voltage, and are driven by the power supply voltage to emit light.

Abstract: Several embodiments of electrical circuit devices and systems with clock distortion calibration circuitry are disclosed herein. In one embodiment, an electrical circuit device includes clock distortion calibration circuitry to calibrate a clock signal. The clock distortion calibration circuitry is configured to determine when one or more duty cycle calibration (DCC) conditions are met. When the DCC condition(s) are met, the clock distortion calibration circuitry is configured adjust a trim value associated with at least one of first and second duty cycles of first and second voltage signals, respectively. In some embodiments, the clock distortion calibration circuitry is configured to calibrate at least one of the first and the second duty cycles of the first and the second voltage signals using the adjusted trim value to account for duty cycle distortion encountered across various voltages and/or temperatures while the electrical circuit devices and/or systems remain in a powered on state.

Abstract: The disclosure is directed to a timing controller having a mechanism for frame synchronization, a display panel having the timing controller thereof, and a display system having the timing controller thereof. According to an aspect of the disclosure, the disclosure provides an integrated circuit which includes a timing controller to transmit a first TE signal to an application processor and receive a first image frame from the application processor after the application processor receives the first TE signal, and a control circuit to generate a first sync signal when the timing controller receives the first image frame, wherein when the application processor receives a second TE signal and the application processor is not ready to transmit a second image frame to the timing controller, the control circuit delays a first waiting period to generate a second sync signal.

Abstract: A data sorting control circuit includes a phase detector suitable for detecting a phase of each of a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal in response to a read command, an order determiner suitable for determining a data order as a first order or a second order based on a seed address and the detected phase of each of the clock signals, and an sorting control signal generator suitable for shifting the read command based on the first clock signal to the fourth clock signal to generate a first sorting control signal, a second sorting control signal, a third sorting control signal, and a fourth sorting control signal, and outputting the first sorting control signal to the fourth sorting control signal according to the first order or the second order.

Abstract: A processing device to perform operations including detecting a first host system connected to a first interface port of the plurality of interface ports of the memory device, the first host system is one of a plurality of host systems. Detecting a second host system connected to a second interface port of the plurality of interface ports, the second host system is one of the plurality of host systems. Assigning a first subset of a plurality of virtual functions (VF)s associated with the memory device to the first host system using root input/output virtualization (SR-IOV) and assigning a second subset of the plurality of VFs to the second host system using SR-IOV. Allocating a first corresponding range of logical block addresses (LBA) to each VF of the first subset of VFs and allocating a second corresponding range of LBAs to each VF of the second subset of VFs.

Abstract: The present discloses provides a display panel driving circuit and a display device. The display panel driving circuit includes a memory; a control chip; and a timing controller including data transmission ends and a control end, the data transmission ends are connected with a control signal output end of a communication switching circuit and a data output end of the memory, and the control end is connected with a controlled end of the communication switching circuit. The timing controller is configured to receive a control signal output by the control chip when controlling the communication switching circuit to be turned on and to read software data of the memory when controlling the communication switching circuit to be turned off.

Abstract: Various embodiments disclose a method and an apparatus including a display, a memory including information on a number of duty cycles per one refresh period for emitting light by pixels of the display corresponding to each of a plurality of refresh rates of the display, and a processor, wherein the processor is configured to control the electronic device to perform an operation according to a first number of duty cycles based on the display operating at a first refresh rate, and perform an operation according to a second number of duty cycles based on the display operating at a second refresh rate, wherein the first number is less than the second number based on the first refresh rate being higher than the second refresh rate.

Abstract: A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a pixel command thread from the plurality of pixel command threads and a vertex command thread from the plurality of vertex command threads. The arbiter further selects a command thread from the previously selected pixel command thread and the vertex command thread, which command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.

Abstract: According to the present invention, it is possible to (i) prevent a deterioration in display quality caused by a disagreement between a frame interval of content and an interval for updating drawing, and (ii) carry out update of drawing quickly after receipt of a drawing update request. The drawing control section sets a first drawing period and a drawing update waiting period so that the periods become different in length and a combined length of those periods matches a frame interval of content.

Abstract: A display device includes: a pixel circuit including a switching transistor connected to a data line, a storage capacitor connected to the switching transistor, a driving transistor connected to the storage capacitor, an organic light-emitting diode connected to the driving transistor and a sensing transistor connected between a sensing line and the driving transistor; and a data-sensing circuit including a first selector connected to the data line and the sensing line, a second selector connected to an output terminal of an amplifier, he first selector and a feedback capacitor, where the second selector selectively connects the output terminal of the amplifier to the first selector and the feedback capacitor, a third selector connected to the sensing line, and a fourth selector connected to the output terminal of the amplifier and the third selector.

Abstract: A display system including a processor configured to transmit image data and command data, the command data including a first command corresponding to storing the image data and a second command corresponding to outputting the image data, and a display driving circuit configured to receive the image data and the command data from the processor and to process the image data according to the command. The display driving circuit generates a garbage image generation signal by comparing receiving timings of the first command and the second command.

Abstract: Embodiments of the present invention may be directed to a graphics system of a computer system. The system may include a frame buffer having a number of partitions respectively mapped to a number of discrete memory devices and a dedicated copy buffer operable to store new image frames, mapped to a first memory device. The first memory device corresponds to a first partition of the number of partitions. The system may also include a loader circuit coupled between the frame buffer and the dedicated copy buffer, operable to copy new image frames from the frame buffer to the dedicated copy buffer. The system may also include a clocked output coupled to receive an image frame from the dedicated copy buffer and operable to drive a display device therewith. The system may enter a low power state wherein a number of the discrete memory devices are powered off.

Abstract: Methods and systems for dynamically controlling buffer size in a computing device in a computing device (“PCD”) are disclosed. A monitor module determines a first use case for defining a first activity level for a plurality of components of the PCD. Based on the first use case, a plurality of buffers are set to a first buffer size. Each of the buffers is associated with one of the plurality of components, and the first buffer size for each buffer is based on the first activity level of the associated component. A second use case for the PCD, different from the first use case, is determined. The second use case defines a second activity level for the plurality of components. At least one of the buffers is set to a second buffer size different from the first buffer size based on the second use case.

Abstract: Methods and apparatus provide pixel information for display. In one example, the methods and apparatus map, using a computing device, pixel information of a virtual rendering surface to a physical curved display screen based on field-of-view point reference data and display curvature data of one or more curved displays using a non-constant scale ratio among a plurality of differing physical pixels in at least one row of a portion of the physical curved display screen. Display data is output based on the mapped pixel information for display to the one or more curved displays.

Abstract: An indication of a capacity of a CMB elasticity buffer and an indication of a throughput of one or more memory components associated with the CMB elasticity buffer can be received. An amount of time for data at the CMB elasticity buffer to be transmitted to one or more memory components can be determined based on the capacity of the CMB elasticity buffer and the throughput of the one or more memory components. Write data can be transmitted from a host system to the CMB elasticity buffer based on the determined amount of time for data at the CMB elasticity buffer to be transmitted to the one or more memory components.

Abstract: An electronic device may include a display panel to display an image and a display pipeline to process image data for the image. The display pipeline may include a controller to determine a first potential presentation time based on a maximum refresh rate of the display panel. The controller may also determine if a second target presentation time of a second image is equal to the first potential presentation time before a pipeline configuration time, and if the second target presentation time of the second image is equal to a second potential presentation time that occurs after the first potential presentation time and before a first pre-notification time occurring before the pipeline configuration time. The controller may output a first pre-notification signal at the first pre-notification time that instructs the display panel to pause self-refreshes until after the second image is displayed.

Abstract: A storage system in one embodiment comprises a host processor that includes a first non-volatile memory. The storage system further comprises a storage device that is coupled to the host processor. A designated portion of the first non-volatile memory is bound to the storage device responsive to storage of binding information in at least one partition table associated with the first non-volatile memory. The storage device may include a storage controller that includes a configuration register space. The binding information may be copied from the one or more partition tables to the configuration register space in conjunction with a boot operation of the host processor. The host processor illustratively comprises a storage device driver having access to the binding information copied to the configuration register space of the storage device. The storage device driver may be configured to utilize the designated portion of the first non-volatile memory that is bound to the storage device as a write back cache.

Abstract: A control apparatus that controls a memory, where the memory is capable of being shifted in accordance with a control signal to a power saving state. According to one embodiment, the control apparatus shifts the memory to the power saving state using the control signal on a basis of stopping of a clock signal input to the memory.

Abstract: A method of driving a display panel includes providing a first clock signal having a first frequency and a second clock signal having a second frequency different from the first frequency. The method also includes providing a data signal of an N-th frame image to the display panel using the first clock signal, and providing a data signal of an (N+1)-th frame image to the display panel using the second clock signal. N is a natural number.

Abstract: A sensor module of the present disclosure includes a sensor section; a memory section having a plurality of memory regions; an arithmetic operation section that performs a predetermined arithmetic operation while accessing the memory section on a basis of a detection result of the sensor section; and a memory control section that controls the memory section to start access to the memory regions at different timings.

Abstract: Systems, apparatuses, and methods for improved memory controller power management techniques. An apparatus includes control logic, one or more memory controller(s), and one or more memory devices. If the amount of traffic and/or queue depth for a given memory controller falls below a threshold, the clock frequency supplied to the given memory controller and corresponding memory device(s) is reduced. In one embodiment, the clock frequency is reduced by one half. If the amount of traffic and/or queue depth rises above the threshold, then the clock frequency is increased back to its original frequency. The clock frequency may be adjusted by doubling the divisor used by a clock divider, which enables fast switching between the original rate and the reduced rate. This in turn allows for more frequent switching between the low power and normal power states, resulting in the memory controller and memory device operating more efficiently.

Abstract: A data storage apparatus, memory controller, and or method operation method may be disclosed. The memory controller may include an address generator configured to generate an operation target address and a destination address. The memory controller may be configured to output the operation target address and the destination address. The memory controller may include a data processor configured to receive the operation target address, read data by accessing the corresponding address of the operation target address, perform an operation on the read data, access the destination address, and write a result of the operation in the accessed destination address.

Abstract: A controller includes an interface and a processor. The interface is configured to communicate with multiple memory devices over a link. The processor is configured to select at least first and second memory devices for writing, and to write at least first and second data units in sequence to the first memory device over the link, while avoiding writing to any of the other memory devices until transferal of the at least first and second data units over the link has been completed, to write at least one data unit to the second memory device after transferring the at least first and second data units to the first memory device, and, in response to verifying that the first memory device is ready to receive subsequent data, to write to the first memory device at least a third data unit.

Abstract: A display control device includes: a receiver configured to receive an image signal; a measurer configured to measure the number of vertical scanning lines and horizontal scanning time of the image signal; a table generator configured to generate a provisional signal table when data measured by the measurer has not been retained in a previously prepared signal table; a detector configured to detect data for regulating an active display region of an image, from the image signal; and an updater configured to update the provisional signal table, based on a detection result by the detector.

Abstract: In a liquid crystal display device, it is determined whether or not image data inputted from the outside has changed from image data of the previous frame by comparing those image data with respect to each line. As a result, when it is determined that the image data has changed, an entire screen is not rewritten, but image data from a top of a screen as a fixed position to a last line with the image data having changed are read from a frame memory and written into a pixel formation portion. Accordingly, of the screen for one frame, a screen from a top thereof to the last line where the image change has been detected is updated, and on subsequent lines, an image of the previous frame is continuously displayed.

Abstract: A frame pacing method, computer program product, and computing system are provided for graphics processing. A method and system for frame pacing adds a delay which evenly spaces out the display of the subsequent frames, and a measurement mechanism which measures and adjusts the delay as application workload changes in an evenly spaced manner.

Abstract: A memory access command, column address and plurality of write data values are received within an integrated-circuit memory chip via external signaling links. In response to the memory access command, the integrated-circuit memory chip (i) decodes the column address to select address-specified sense amplifiers from among a plurality of sense amplifiers that constitute a sense amplifier bank, (ii) reads first data, constituted by a plurality of read data values, out of the address-specified sense amplifiers, and (iii) overwrites the first data within the address-specified sense amplifiers with second data constituted by one or more of the write data values and by one or more of the read data values.

Abstract: A processor includes a decoder to receive an instruction that indicates first and second source packed data operands and at least one shift count. An execution unit is operable, in response to the instruction, to store a result packed data operand. Each result data element includes a first least significant bit (LSB) portion of a first data element of a corresponding pair of data elements in a most significant bit (MSB) portion, and a second MSB portion of a second data element of the corresponding pair in a LSB portion. One of the first LSB portion of the first data element and the second MSB portion of the second data element has a corresponding shift count number of bits. The other has a number of bits equal to a size of a data element of the first source packed data minus the corresponding shift count.

Abstract: Embodiments of a unified shading controller are disclosed. The embodiments may provide a first functional unit configured to send a write request to a second functional unit. The write request may include data and the data may include one or more control bits. Upon receiving the write request, the second functional unit may check the one or more control bits, and hold the data in a given queue dependent upon the control bits.

Abstract: Embodiments of the present invention provide methods and apparatuses for reducing power consumption for a mobile electronic device in order to extend battery life. In an embodiment, the mobile electronic device monitors a power level of the battery in the mobile electronic device, determines that the power level of the battery reaches a predetermined threshold, and based upon the determination, terminates a first launcher currently running on the mobile electronic device and activates a second launcher on the mobile electronic device. By activating the second launcher which has power saving features, the power consumption of the mobile electronic device is reduced and thus the battery life is extended while preserving the basic functions of the mobile device.

Abstract: An accelerator circuit for an image processing apparatus includes a buffer circuit that temporarily stores image data obtained from N (N>1) data sources and an arithmetic circuit that performs a predetermined arithmetic operation on pixel data. The buffer circuit includes N buffer memories and N 2D registers associated with the respective N data sources, a control circuit, and a selector. Each buffer memory temporarily stores image data obtained from a corresponding one of the N data sources. Each 2D register temporarily stores pixel data, which is a part of image data stored in a corresponding one of the N buffer memories, of an area of a predetermined size. The selector is controlled by the control circuit so as to select, when pixel data is stored in one of the N 2D registers, the pixel data and send the pixel data to the arithmetic circuit.

Abstract: Embodiments described herein relate to improving throughput of a CPU and a GPU working in conjunction to render graphics. Time frames for executing CPU and GPU work units are synchronized with a refresh rate of a display. Pending CPU work is performed when a time frame starts (a vsync occurs). When a prior GPU work unit is still executing on the GPU, then a parallel mode is entered. In the parallel mode, some GPU work and some CPU work is performed concurrently. When the parallel mode is exited, for example when there is no CPU work to perform, the parallel mode may be exited.

Abstract: A method of operating a timing controller, which communicates with a host through a mobile industry processor interface (MIPI) and communicates with a display panel module through a display interface, is provided. The method includes storing image data compressed by one of the host and the timing controller in a frame memory, decompressing the image data stored in the frame memory, and performing panel self-refresh on the display panel module using the decompressed image data.

Abstract: Devices and methods for providing an indication of an active frame start, while reducing a number of line buffers utilized by conventional systems are provided herein. By way of example, an electronic display panel may include a host device (e.g., a processor) that provides an indication of a pending active frame start. The indication may be provided at a predetermined and fixed time/line interval before the active frame start. Next, a timing controller of the display circuitry may generate a vertical start pulse during vertical blanking based upon the indication and the fixed time/line interval. The vertical start pulse may be used to drive multi-clock integrated row driver circuits.

Abstract: A timing controller for a panel display system includes: an image signal receiver that receives an image signal; an overdrive circuit that receives and converts the image signal from the image signal receiver according to successive first frame data and second frame data in the image signal; an image signal transmitter that receives the converted image signal from the overdrive circuit and transmits the same to a display panel; a memory; and a memory interface unit. In a normal read/write period, the memory interface unit receives the first frame data from the overdrive circuit and stores the same in the memory, and fetches the first frame data from the memory when the overdrive circuit receives the second frame data in the image signal and transmits the same to the overdrive circuit. The memory interface unit further obtains sampling results to generate a preferred delay phase.

Abstract: A display controller driver and a testing method thereof are provided. The display controller driver includes an image data memory, a timing control circuit, and a data line driving circuit. The image data memory stores display data. The timing control circuit obtains the display data from the image data memory. The data line driving circuit is coupled to the timing control circuit. The data line driving circuit receives the display data and outputs a grayscale voltage signal corresponding to the display data through at least one data-line output terminal of the display controller driver. In a test operation mode, the timing control circuit further transmits the display data from the image data memory to at least one test output port of the display controller driver.

Abstract: A control circuit for a frame memory includes a divider, a frame memory, a read control circuit, and a write control circuit. The divider divides image data into subfield data according to a plurality of subfields, where the image data is provided in synchronization with a first synchronization signal and in a unit of a frame. The frame memory has a plurality of blocks to store the subfield data. The read control circuit sequentially reads the subfield data from the blocks in synchronization with a second synchronization signal. The write control circuit writes new data to a first block before data written in a second block is read, and after data written in the first block is read by the read control circuit. The second synchronization signal may have a same cycle as the first synchronization signal and may be delayed by a preset delay time.

Abstract: A terminal includes a controller, a driver, and a display. The controller transmits image data based on a first signal. The driver includes an internal memory and performs a memory write operation for the transmitted image data in the internal memory. The display output the image data, for which the memory write operation in the internal memory has been performed, based on a memory scan operation. The performs the memory scan operation at a first frequency and generates a second signal based on when the memory scan operation and memory write operation for the internal memory are to alternate. The controller transmits the image data based on the second signal.

Abstract: Embodiments of the present invention provide for improved timing control in 2-D image processing to maintain a constant rate of fetches and pixel outputs even when the processing operations transition to a new line or frame of pixels. A one-to-one relationship between incoming pixel rate and outgoing pixel rate is maintained without additional clock cycles or memory bandwidth as an improved timing control according to the present invention takes advantage of idle memory bandwidth by pre-fetching a new column of pixel data in a first pixel block of a next line or frame while a new column of an edge pixel block on a current line is duplicated or zeroed out. As the edge pixel block(s) on the current line are processed, the data in the first pixel block of the next line or frame become ready for computation without extra clock cycles or extra memory bandwidth.

Abstract: An object of the present invention is to provide a display device and a method of driving it, capable of displaying images properly even upon asynchronous input of image data while taking advantages of decreased power consumption implemented by intermission driving. When there is an external input of new image data (image F) in a non-refreshing period in an intermission driving display device which performs intermittent refreshing based on the latest image data that is inputted in and read out from a frame memory, a coercive refreshing is started immediately based on the new image data (image F) (see the sixth frame period). Also, when there is an external input of image data (image G) during a refreshing period for the image F, the ongoing frame period including the refreshing of the image F is completed and immediately thereafter, a coercive refreshing based on the image data (image G) is started (see the ninth frame period).

Abstract: In an embodiment, there is provided a video processing component comprising a compensation engine configured to generate pixels of a first video frame from a second video frame based at least in part on specified pixel motion; and an access buffer configured to store pixel data corresponding to pixels of the second video frame for reference by the compensation engine, wherein the pixel data is stored by the access buffer at different vertical resolutions depending on vertical distances of the pixels corresponding to the pixel data from a target pixel that is indicated by the compensation engine.

Abstract: No flicker is displayed on the display screen during display of moving pictures and power consumption can be reduced by adding a high quality moving picture display function. Moreover, the number of times of transfer of moving pictures by comprising a still-picture • text • system • I/O bus • interface and a moving picture interface (external display interface), providing a display operation change register (DM) and a RAM access change register (RM) which are changed selectively depending on display content (display mode) displayed on a display device and displaying the display data on the display device via a picture memory even in the moving picture display mode.

Abstract: A display system and a data transmission method thereof are provided. When a first frame stored in a frame buffer is identical to a second frame to be output from an audio and video (AV) source, the AV source is set an AV control signal corresponding to a self-refresh mode, and a timing controller reads the first frame to output a display data controlled by the AV control signal. When the first frame is differed from the second frame, the AV source is set the AV control signal corresponding to a data update mode and a AV data signal corresponding to the second frame, and the timing controller stores the second frame in the frame buffer controlled by the AV control signal and outputs the display data corresponding to the first frame or the second frame according the timing sequences of the AV data signal and the display data.

Abstract: An electronic device for detecting static images and reducing resource usage is described. The electronic device includes a processor and instructions stored in memory. The electronic device determines image memory. The electronic device also sets a timer. The electronic device further monitors the image memory. The electronic device also determines whether there is a write access request for the image memory. Furthermore, the electronic device determines whether a time threshold has been reached based on the timer if there is not a write access request for the image memory. The electronic device also reduces display resource usage if the time threshold has been reached.

Abstract: Parallel graphics-processing methods and mobile computing apparatus with parallel graphics-processing capabilities are disclosed. One exemplary embodiment of a mobile computing apparatus includes physical memory, at least two distinct graphics-processing devices, and a bus coupled to the physical memory and the at least two graphics-processing devices. A virtual graphics processing component enables each of at least two graphics-processing operations to be executed, in parallel, by a corresponding one of the at least two distinct graphics-processing devices, which operate in the same memory surface at the same time.

Abstract: The present invention relates to a mobile terminal displaying an instant message and a control method of the same. A mobile terminal according to an aspect of the invention may include: a wireless communication unit sending or receiving an instant message; a display unit including a first region and a second region and displaying the instant message sent or received by the wireless communication unit on the first region; and a controller displaying information corresponding to at least one object included in the instant message on the second region.

Abstract: Techniques are described that can used to synchronize the start of frames from multiple sources so that when a display is to output a frame to a next source, boundaries of current and next source are aligned. Techniques are useful to avoid visual distortions when changing from a first video source to a second video source.

Abstract: Provided is a graphics rendering device that includes a frame data generation unit, access pattern setting unit, and frame data writing unit. The frame data generation unit generates, from part of stencil data, a part of frame data composed of a piece of second pixel information corresponding to a predetermined number of pixels in accordance with a first access pattern and an anti-alias pattern used in generating pieces of second pixel information. The access pattern setting unit sets, in accordance with the first access pattern and the anti-alias pattern, a second access pattern indicating pieces of second pixel information accessible by a single access to the frame buffer. The frame data writing unit writes in the frame buffer, when the frame data generation unit has generated a number of pieces of second pixel information indicated by the second access pattern, a part of the frame data corresponding to the number of pieces of second pixel information in accordance with the second access pattern.

Abstract: A frame-rate conversion system having an interpolation mode and a synchronization mode. The synchronization mode is selected when temporal interpolation confidence is and images can be retimed without dropping or repeating of images. The interpolation mode is selected when the measure of temporal interpolation confidence is high or repeating of images. Images are exchanged between a temporal interpolator and a buffer at an exchange rate which is varied in the interpolation mode to optimise the buffer occupancy for retiming of images without dropping or repeating of images in s subsequent synchronization.

Abstract: A signal controlling method for a display device for signal processing between an external system and a display panel that displays an image by receiving a signal from the external system. The method includes receiving N clock signals and N data signals synchronized with the N clock signals from the external system through N channels, N being a natural number no less than 2; writing the received N data signals in N storage units in order of reception time of the N data signals; extracting one clock signal from the N clock signals; and outputting the N data signals written in the N storage units simultaneously in synchronization with the extracted clock signal.