Abstract: An apparatus configured to match an input frame rate of a video stream with an output frame rate of an output stream, the apparatus comprising, at least one memory buffer, an output frame generator, and a threshold measurement unit, the threshold measurement unit configured to generate a control feedback, wherein the box is configured to analyze the control feedback to monitor a state of the at least one memory buffer, the threshold measurement unit further configured analyze the control feedback to regulate between two or more different settings, wherein the two or more different settings include slowing down or speeding up the output frame, wherein the two or more different settings further include slowing down or speeding up of the line rate of the output stream.

Abstract: Embodiments of the present invention provide for improved timing control in 2-D image processing to maintain a constant rate of memory fetches and pixel outputs even when the processing operations transition to a new line or frame of pixels. A one-to-one relationship between incoming pixel rate and outgoing pixel rate is maintained without additional clock cycles or memory bandwidth as an improved timing control according to the present invention takes advantage of idle memory bandwidth by pre-fetching a new column of pixel data in a first pixel block of a next line or frame while a new column of an edge pixel block on a current line is duplicated or zeroed out. As the edge pixel block(s) on the current line are processed, the data in the first pixel block of the next line or frame become ready for computation without extra clock cycles or extra memory bandwidth.

Abstract: Disclosed herein are methods, apparatuses, and systems for accessing vertex data stored in a memory, and applications thereof. Such a method includes writing vertex data of primitives into contiguous banks of a memory such that the vertex data of consecutively written primitives spans more than one row of the memory. Vertex data of two consecutively written primitives are read from the memory in a single clock cycle.

Abstract: A graphics system may include a display pipe with a buffer configured to store pixels to be processed by a display controller for displaying on a display device, with a buffer control circuit coupled to the buffer to supply pixels to the display controller. When the buffer control circuit detects an underrun of the buffer responsive to the display controller attempting to read pixels from the buffer that have not yet been written to the buffer, the buffer control circuit may supply an underrun pixel to the display. The underrun pixel may be selected from a set of previously stored set of underrun pixels, which may include a most recent valid pixel read by the display controller. A read pointer representative of the location in the buffer from where the display controller is currently attempting to read may be advanced even when an underrun condition occurs.

Abstract: Techniques are described that can used to synchronize the start of frames from multiple sources so that when a display is to output a frame to a next source, boundaries of current and next source are aligned. Techniques attempt to avoid visible glitches when switching from displaying a frame from a first source to displaying frames from a second source even though alignment is achieved by switching if frames that are to be displayed from the second source are similar to those displayed from the first source.

Abstract: No flicker is displayed on the display screen during display of moving pictures and power consumption can be reduced by adding a high quality moving picture display function. Moreover, the number of times of transfer of moving pictures by comprising a still-picture • text • system • I/O bus • interface and a moving picture interface (external display interface), providing a display operation change register (DM) and a RAM access change register (RM) which are changed selectively depending on display content (display mode) displayed on a display device and displaying the display data on the display device via a picture memory even in the moving picture display mode.

Abstract: A data transfer circuit that transfers a first kind of data stored in an external memory circuit includes: an internal memory circuit that is capable of, by an external circuit, writing and/or rewriting a second kind of data including information for one region as a transfer source in the external memory circuit and another region as a transfer destination in the external memory circuit; a transfer circuit that transfer the first kind of data; and a control circuit that makes the transfer circuit transfer the first kind of data stored in the one region to the other region based on the second kind of data.

Abstract: Embodiments of the present invention provide for improved timing control in 2-D image processing to maintain a constant rate of fetches and pixel outputs even when the processing operations transition to a new line or frame of pixels. A one-to-one relationship between incoming pixel rate and outgoing pixel rate is maintained without additional clock cycles or memory bandwidth as an improved timing control according to the present invention takes advantage of idle memory bandwidth by pre-fetching a new column of pixel data in a first pixel block of a next line or frame while a new column of an edge pixel block on a current line is duplicated or zeroed out. As the edge pixel block(s) on the current line are processed, the data in the first pixel block of the next line or frame become ready for computation without extra clock cycles or extra memory bandwidth.

Abstract: A power adjustment circuit includes memory controller logic that is couplable to system memory or other memory if desired. The memory control logic is operative to provide a variable memory clock signal to the system memory and to place the system memory in a self refresh mode wherein the self refresh mode does not require a memory clock signal. Thereafter, the memory clock control logic adjusts the frequency of the memory clock signal to a lower (or higher) frequency clock signal, and in response to the frequency of the memory clock signal becoming stable, the memory clock control logic restores the memory to a normal mode using the lower adjusted frequency memory clock signal. As such, a dynamic memory clock switching mechanism is employed for quickly varying the frequency of memory modules for discrete graphics processors, graphics processors integrated on a chip, or any other processors such that the memory clock can be reduced to a lower frequency in real time to save power.

Abstract: Provided herein is a cable label forming apparatus having an edit screen display device, a selection candidate display instructing device, and a selection candidate display device. The selection candidate display device displays a last selected candidate among the plurality of selection candidates on a priority basis in a normal edit screen when displaying the plurality of selection candidates is instructed, and displays a specific candidate among the plurality of selection candidates on a priority basis in a cable label forming edit screen when displaying the plurality of selection candidates is instructed.

Abstract: A data conversion method and a data conversion device convert a large cubic three-dimensional image data to a plurality of pieces of small cubic one-dimensional image data, or convert a plurality of pieces of small cubic one-dimensional image data to a large cubic three-dimensional image data. The data conversion method includes the following steps, marking a three-dimensional index on three-dimensional image data; converting the three-dimensional index to a writing sequence index; inputting the three-dimensional image data to a buffer memory in sequence according to the writing sequence index; computing a reading sequence index according to the writing sequence index; outputting data blocks from the buffer memory in sequence according to the reading sequence index. Through the method and the device, use of the memory is reduced, and time for conversion is lowered.

Abstract: A method and system for efficiently organizing data in memory is provided. Exemplary aspects of the invention may include storing linear data and block data in more than one DRAM device and accessing the data with one read/write access cycle. Common control signals may be used to control the DRAM devices and the address lines used to address each DRAM device may be independent from one another. The data read from the DRAM devices may be reordered to make the data more suitable for processing by applications.

Abstract: An image processing method applied to an image processing device is capable of implementing bitstream stitching technique after interrupting image processing process. The image processing method includes steps of processing the i-th slice of N slices in an image to generate a plurality of first processed data; storing the first processed data in a memory unit; once an interrupting request is generated according to a requested process, storing stitching information associated with the last first processed data after processing the i-th slice; stopping processing the image and executing the requested process according to the interrupting request; continuing to process the (i+1)-th slice of the N slices to generate a plurality of second processed data after the requested process is finished; and storing the second processed data after the last first processed data in the memory unit according to the stitching information.

Abstract: Embodiments of the present invention provide for improved timing control in 2-D image processing to maintain a constant rate of memory fetches and pixel outputs even when the processing operations transition to a new line or frame of pixels. A one-to-one relationship between incoming pixel rate and outgoing pixel rate is maintained without additional clock cycles or memory bandwidth as an improved timing control according to the present invention takes advantage of idle memory bandwidth by pre-fetching a new column of pixel data in a first pixel block of a next line or frame while a new column of an edge pixel block on a current line is duplicated or zeroed out. As the edge pixel block(s) on the current line are processed, the data in the first pixel block of the next line or frame become ready for computation without extra clock cycles or extra memory bandwidth.

Abstract: A method and an apparatus for maintaining separate information for graphics commands that have been sent to a graphics processing unit (GPU) and for graphics commands that have been processed by the GPU are described. The graphics commands may be associated with graphics resources. A manner to respond to a request for updating the graphics resources may be determined based on examining the separate information maintained for the graphics commands. The request may be received from a graphics API (application programming interface). Responding to the request may include at least one of notifying the graphics API regarding a status of the graphics resources and updating the graphics resources identified by the request.

Abstract: Systems, devices, and methods for delivering and managing media whereby a first media element contains multiple media components and a combination of user activity and time are necessary to unlock a subset of the multiple media components. In one embodiment, the user activities include serving as a peer leader, purchasing a key that unlocks at least one of the multiple media components, and other activities having value to the system. The system may also update the media components individually, or in parallel. In addition, the requirements for unlocking one or more of the media components may vary dynamically, or the media components may vary based on: known individual characteristics of a user in a group of users, group characteristics of a subset of users within a group of users or other criteria.

Abstract: Embodiments of the present invention may be directed to a graphics system of a computer system. The system may include a frame buffer having a number of partitions respectively mapped to a number of discrete memory devices and a dedicated copy buffer operable to store new image frames, mapped to a first memory device. The first memory device corresponds to a first partition of the number of partitions. The system may also include a loader circuit coupled between the frame buffer and the dedicated copy buffer, operable to copy new image frames from the frame buffer to the dedicated copy buffer. The system may also include a clocked output coupled to receive an image frame from the dedicated copy buffer and operable to drive a display device therewith. The system may enter a low power state wherein a number of the discrete memory devices are powered off.

Abstract: Graphics display adapters for driving multiple display monitors have become very popular. Graphics display adapters that drive multiple monitors can be used to provide terminal services to multiple independent terminals or be used to provide multiple displays to a single user. Generating video signals for multiple display systems puts a heavy burden on the video memory system since multiple different video signal generators may read from associated frame buffers in a shared video memory system. In one disclosed embodiment, a plurality of video memory read triggers are provided wherein at least two of which are staggered to reduce the load on the video memory system. In response to each read trigger, display data is read from a frame buffer to an associated video signal generation circuit. Each video signal generation circuit then provides a display signal to an associated display screen in a multi-screen environment.

Abstract: A display method comprises the steps of generating (1) images comprising source data (SDA) and source frame synchronization instants (SSI) having a source frame rate (SFR). The source data (SDA) is stored (2) in a frame memory (5) under control of a first address pointer (AP I) having a start address (DSA) being determined by the source frame synchronization instants (SSI). During a read period (RP), display data (DDA) is read (2) from the memory (5) under control of a second address pointer (AP2) having a start address (SSA) being determined by display frame synchronization instants (DSI) having a display frame rate (DFR). The display data (DDA) is displayed (3) on a matrix display (4). The source frame rate (SIR) or the display frame rate (DFR) is controlled (2) to obtain, in a stable situation, the first address pointer (AP I) and the second address pointer (AP2) starting with an offset in time (TO) which has a fixed polarity during the read period (RP).

Abstract: A method and system for efficiently organizing data in memory is provided. Exemplary aspects of the invention may include storing linear data and block data in more than one DRAM device and accessing the data with one read/write access cycle. Common control signals may be used to control the DRAM devices and the address lines used to address each DRAM device may be independent from one another. The data read from the DRAM devices may be reordered to make the data more suitable for processing by applications.

Abstract: Provided herein is a cable label forming apparatus having an edit screen display device, a selection candidate display instructing device, and a selection candidate display device. The selection candidate display device displays a last selected candidate among the plurality of selection candidates on a priority basis in a normal edit screen when displaying the plurality of selection candidates is instructed, and displays a specific candidate among the plurality of selection candidates on a priority basis in a cable label forming edit screen when displaying the plurality of selection candidates is instructed.

Abstract: Embodiments of the present invention provide for improved timing control in 2-D image processing to maintain a constant rate of memory fetches and pixel outputs even when the processing operations transition to a new line or frame of pixels. A one-to-one relationship between incoming pixel rate and outgoing pixel rate is maintained without additional clock cycles or memory bandwidth as an improved timing control according to the present invention takes advantage of idle memory bandwidth by pre-fetching a new column of pixel data in a first pixel block of a next line or frame while a new column of an edge pixel block on a current line is duplicated or zeroed out. As the edge pixel block(s) on the current line are processed, the data in the first pixel block of the next line or frame become ready for computation without extra clock cycles or extra memory bandwidth.

Abstract: Systems and methods of compressing and displaying the contents of multiple display devices on a single display device are presented. The display content from each of a plurality of devices is contemporaneously displayed by placing each respective desktop display raster data into video memory in a sequential order for each of the plurality of monitors and setting the scan engine to scan a single, very wide, image having a horizontal value equal to the sum of the widths of the individual displays and a vertical value equal to the original height of the individual display.

Abstract: A display control device for controlling a display panel includes a contents frame rate detector detecting a contents frame rate of an input image data and outputting a repetitive frame number dependent from a display frame rate of the display panel and the detected contents frame rate; a frame memory for storing a level data of a previous frame; and an emulated level generator in communication with the contents frame rate detector and the frame memory. An output level data to the display panel is generated according to the repetitive frame number from the contents frame rate detector, the previous level data from the frame memory and an input level data of the input image data.

Abstract: An image capturing device capable of automatically switching the clock of the memory and a control method thereof. The image capturing device comprises an image capturing module, a display module, an image buffer module, an operating module and a processing module. The operating module increases the clock of the image buffer module to a first clock, and works with the image capturing module to perform an image capturing process. After the image capturing process is finished, the processing module stops a timing generating unit in the operating module from sending a synchronizing signal to the display module, and controls the operating module to decrease the clock of the image buffer module from the first clock to a second clock. Finally, the processing module controls the timing generating unit to re-send the synchronizing signal to the display module.

Abstract: The present invention provides a data accessing system and a data accessing method. The method comprises: separately storing a (N×M)-bit digital data in L banks of a data storage module; utilizing a register module of a data accessing interface module to transmit data of a bank for L times in sequence, and to receive and latch the digital data included by a bank from the data storage module when transmitting data each time, until the (N×M)-bit digital data is totally latched in the register module; and utilizing a multiplex output module of the data accessing interface module to continuously select a M-bit digital data from the (N×M)-bit digital data registered in the register module, and input the M-bit digital data to a data retrieving device via M data transmission lines.

Abstract: A method and system for efficiently organizing data in memory is provided. Exemplary aspects of the invention may include storing linear data and block data in more than one DRAM device and accessing the data with one read/write access cycle. Common control signals may be used to control the DRAM devices and the address lines used to address each DRAM device may be independent from one another. The data read from the DRAM devices may be reordered to make the data more suitable for processing by applications.

Abstract: A graphics display device and method performing display indicating that graphics software for graphics drawing is an evaluation version including storing a display pattern indicating that the graphics software is an evaluation version, storing a parameter indicating a display method of the display pattern and displaying the display pattern based on the parameter by a cursor display hardware.

Abstract: There is provided an information processing device including: a light emitting unit to supply light to an operating means mounted on an IC card, the operating means being capable of switching display contents on a display unit of the IC card by a potential difference occurring due to photoelectric conversion; a communication unit to transmit given data to the IC card for causing the IC card to record the data; and a light emission adjusting unit to cause the data recorded on the IC card through the communication unit to be displayed on the IC card by adjusting the number of times of emitting light or a light emitting pattern from the light emitting unit.

Abstract: A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.

Abstract: A method and electronic device employing the method of processing a frame of graphics for display is provided that includes developing a frame in a first software frame processing stage following a first vertical blanking (VBL) heartbeat, issuing a command indicating the first stage is complete, and performing a final software frame processing stage without waiting for a subsequent VBL heartbeat. The method may alternatively include performing the final software frame processing stage regardless as to whether a target framebuffer is available, performing all but final hardware frame processing stages regardless as to whether the target framebuffer is in use, and performing the final hardware processing stage if the target framebuffer is not in use.

Abstract: The present invention relates to systems and methods for content resizing and caching in multi-process browser architecture. An embodiment includes initiating a rendering engine process and a browser process, receiving a request to resize content, providing the request to the rendering engine process, waiting to allow the rendering engine process to render an updated bitmap associated with the content and displaying the updated bitmap synchronously if the updated bitmap is produced during the waiting step. Another embodiment includes, receiving an input associated with the status of a tab, determining if the tab is a background tab or a foreground tab based on the receiving step, checking a cache for a bitmap of content associated with the tab if the tab has changed status to a foreground tab; and displaying the contents of the cache in the tab if the cache includes the bitmap of content previously associated with the tab.

Abstract: A data access method for a timing controller of a flat panel display includes forming a line buffer including a plurality of memory cells in the timing controller, dividing the plurality of memory cells into a first section and a second section, wherein the number of memory cells in the first section is greater than the number of memory cells in the second section, writing a first number of pixel data into the first section, wherein the first number of pixel data is included in a plurality of pixel data corresponding to a row of a frame, writing a second number of pixel data into the second section, wherein the second number of pixel data is included in the plurality of pixel data, and the first number is equal to the second number, and reading the plurality of pixel data from the plurality of memory cells according to an order.

Abstract: A method of processing a user interface component is provided and includes receiving one or more user interface components that can be communicated to a wireless device. A component risk level for each of the one or more user interface components is determined and assigned to each of the one or more user interface components. Each of the one or more user interface components can be digitally signed using an embedded risk code that indicates the assigned risk level. Further, the component risk level can be selected from a plurality of component risk levels. In a particular embodiment, the component risk level can be determined based on the type of the user interface component. Further, the component risk level can be determined based on a developer of the user interface component.

Abstract: Systems and methods of compressing and displaying the contents of multiple display devices on a single display device are presented. The display content from each of a plurality of devices is contemporaneously displayed by placing each respective desktop display raster data into video memory in a sequential order for each of the plurality of monitors and setting the scan engine to scan a single, very wide, image having a horizontal value equal to the sum of the widths of the individual displays and a vertical value equal to the original height of the individual display.

Abstract: In devices in which display data is read from a memory for display, display underflow in a processing block is alleviated by controlling a clock frequency driving the processing block. Stages of the processing block send underflow detection signals to underflow prevention logic. The underflow prevention logic controls the frequencies of clock signals generated by a clock generator to alleviate the underflow condition.

Abstract: Graphics display adapters for driving multiple display monitors have become very popular. Graphics display adapters that drive multiple monitors can be used to provide terminal services to multiple independent terminals or be used to provide multiple displays to a single user. Generating video signals for multiple display systems puts a heavy burden on the video memory system since multiple different video signal generators may read from associated frame buffers in a shared video memory system. In one disclosed embodiment, a plurality of video memory read triggers are provided wherein at least two of which are staggered to reduce the load on the video memory system. In response to each read trigger, display data is read from a frame buffer to an associated video signal generation circuit. Each video signal generation circuit then provides a display signal to an associated display screen in a multi-screen environment.

Abstract: A display controller driver and a testing method thereof are provided. The display controller driver includes an image data memory, a timing control circuit, and a data line driving circuit. The image data memory stores display data. The timing control circuit obtains the display data from the image data memory. The data line driving circuit is coupled to the timing control circuit. The data line driving circuit receives the display data and outputs a grayscale voltage signal corresponding to the display data through at least one data-line output terminal of the display controller driver. In a test operation mode, the timing control circuit further transmits the display data from the image data memory to at least one test output port of the display controller driver.

Abstract: A method and an apparatus for maintaining separate information for graphics commands that have been sent to a graphics processing unit (GPU) and for graphics commands that have been processed by the GPU are described. The graphics commands may be associated with graphics resources. A manner to respond to a request for updating the graphics resources may be determined based on examining the separate information maintained for the graphics commands. The request may be received from a graphics API (application programming interface). Responding to the request may include at least one of notifying the graphics API regarding a status of the graphics resources and updating the graphics resources identified by the request.

Abstract: An electronic device for detecting static images and reducing resource usage is described. The electronic device includes a processor and instructions stored in memory. The electronic device determines image memory. The electronic device also sets a timer. The electronic device further monitors the image memory. The electronic device also determines whether there is a write access request for the image memory. Furthermore, the electronic device determines whether a time threshold has been reached based on the timer if there is not a write access request for the image memory. The electronic device also reduces display resource usage if the time threshold has been reached.

Abstract: Embodiments of the present invention provide for improved timing control in 2-D image processing to maintain a constant rate of memory fetches and pixel outputs even when the processing operations transition to a new line or frame of pixels. A one-to-one relationship between incoming pixel rate and outgoing pixel rate is maintained without additional clock cycles or memory bandwidth as an improved timing control according to the present invention takes advantage of idle memory bandwidth by pre-fetching a new column of pixel data in a first pixel block of a next line or frame while a new column of an edge pixel block on a current line is duplicated or zeroed out. As the edge pixel block(s) on the current line are processed, the data in the first pixel block of the next line or frame become ready for computation without extra clock cycles or extra memory bandwidth.

Abstract: An image converter converts an image rendered at a given vertical synchronous frequency into an image compatible with the specification of a display. A frame memory holds the image converted by the image converter by switching a plurality of buffers. A display controller selects one of the buffers in accordance with the vertical synchronous frequency of the display, and scans out the image from the frame memory accordingly. A switch instruction issuing unit issues a frame buffer switch instruction for designating a frame buffer to scan out from subsequently, in synchronization with the vertical synchronous frequency of the display, instead of immediately after the execution of an image converting process by the image converter.

Abstract: Provided is a plasma display system capable of restricting peak data traffic when a shared memory is used. In the plasma display system, a control unit 104 prohibits a moving picture decoder 101 from accessing a shared memory 140 while an SF reading unit 101 is reading, from the shared memory 140, SF pixel data which is information about respective cells to be lit in a plurality of subfields. On the other hand, the control unit 104 permits the moving picture decoder 101 to access the shared memory 140 while the SF reading unit 101 is not reading the SF pixel data from the shared memory 140, that is to say, during a sustain discharge period.

Abstract: Registers 32a-32d hold data for pixels interleaved. An operator 34 reads the pixel data from the registers and processes the pixel data in accordance with a program code. The operator 34 writes the result of the process back to the registers via a cache 38 or writes it in a memory. Program counters PC0-PC3 provided in association with the number of pixels interleaved store the addresses of instructions in a program for the respective pixels. An instruction loader 76 alternately reads from the program counters. An incrementer 74 increments the count of the program counters. The instructions in the program for the pixels are alternately loaded and interleaved on a pixel by pixel basis, before being supplied to the operator 34 and the like.

Abstract: A Video Card with standard video output and a Network Ethernet port output of compressed digital video output that represents the image seen by a monitored computer user. A custom video card software driver is used to set up the dual display video controller configurations that assist with the functioning of the digital video compression that is a hardware combination of Run-Length, Huffman encoding and MPEG located on the same monitored user video card. One of the video controller's I2C ports is used to control the compression video circuits and as the pathway for the custom Ethernet communications, thus avoiding an additional costly connection to the user's main computer bus. The first video stream from the dual head video controller chip is used for regular viewing by the local PC (personal computer) user.

Abstract: Embodiments of the present invention provide for improved timing control in 2-D image processing to maintain a constant rate of memory fetches and pixel outputs even when the processing operations transition to a new line or frame of pixels. A one-to-one relationship between incoming pixel rate and outgoing pixel rate is maintained without additional clock cycles or memory bandwidth as an improved timing control according to the present invention takes advantage of idle memory bandwidth by pre-fetching a new column of pixel data in a first pixel block of a next line or frame while a new column of an edge pixel block on a current line is duplicated or zeroed out. As the edge pixel block(s) on the current line are processed, the data in the first pixel block of the next line or frame become ready for computation without extra clock cycles or extra memory bandwidth.

Abstract: When inputted pixels from an input DMA unit, a packing unit outputs data package. One data package consists of ? inputted pixels. A memory control unit writes, on a write line memory at a write interval, the data package that is outputted by the packing unit. The write interval is ? times longer than an input interval at which the pixels are inputted into the packing unit. During the writing process, the memory control unit reads out another data package from a read line memory at a read interval that is the same as the input interval. In addition, the memory control unit treats the write line memory as the read line memory, after completing the writing process. Alternatively, the memory control unit treats the read line memory as the write line memory, after completing the reading process.

Abstract: A method of automatically recovering bit values of a control register includes storing command data inputted from a host in the control register and a portion of a graphic RAM (GRAM), and while a scanning operation is performed by the GRAM, outputting the command data stored in the GRAM to the control register and refreshing the control register.

Abstract: A display control circuit capable of performing arbitration with the use of a simple configuration. The display control circuit exchanges, with a plurality of masters, attribute information defining conditions for displaying video on a display, and includes a memory for storing the attribute information, a plurality of channels associated with the respective masters for accepting, from the masters, access requests to access the memory, and an arbitration controller configured by hardware. The arbitration controller arbitrates the access requests accepted via the respective channels and permits a selected one of the access requests to access the memory.

Abstract: A display unit includes: a display panel for displaying a plurality of information images; a memory for storing a plurality of image data elements corresponding to the information images; an image memory for storing the image data elements transferred from the memory; and a controller for controlling the display panel to display the information images based on the image data elements in the image memory. The controller transfers a part of the image data elements to the image memory on ahead when the display unit starts to operate, and the controller controls the display panel to display a part of information images on ahead based on the part of the image data elements.