Abstract: A picture processing apparatus is composed of a plurality of picture processing systems. Each picture processing system includes an identical picture processing IC (integrated circuit) and a plurality of memories each capable of memorizing a picture frame and including at least two memories operating at different timings. The picture processing IC includes a picture processing unit, an operation timing signal generator, a plurality of control timing signal generators for controlling different memories, and a memory control signal selection circuit for selectively outputting one of at least two memory control timing signals. As a result, the number of output pins of each picture processing IC for outputting memory control signal can be reduced, whereby the picture processing apparatus can be produced at a lower cost while retaining an identically large size of the picture processing ICs.

Abstract: A system-on-a-chip controller having a first processor and a second processor. The first processor provides control processing and image processing. The second processor provides image processing. The processors receive data from an external source through a data bus. Also, the controller can include a third controller to provide I/O functionality to an external device. The second processor processes the stored data in either a row or column configuration. A fixed-length instruction word can be decoded into two instructions, an operation instruction and an I/O instruction, and can be used to process the data. The I/O instruction can be disposed in an unused bit field of the operation instruction.

Abstract: A system for synchronizing video data streams utilizes a plurality of buffer pairs and buffering logic. The buffering logic is configured to receive image frames from a plurality of asynchronous video data streams and to perform comparisons between frame identifiers associated with the image frames. The buffering logic is further configured to double buffer the image frames via the plurality of frame buffer pairs based on the comparisons and to synchronously output the image frames from the frame buffer pairs.

Abstract: The basic section of the multimedia data-processing system includes a CPU 1100, an image display unit 2100, a unified memory 1200, a system bus 1920, and devices 1300, 1400, and 1500 connected to the system bus. In this configuration, the CPU is formed on an LSI mounted on a single silicon wafer including instruction processing unit 1110 and display control unit 1140. Main storage area 1210 and display area 1220 are stored within the unified memory. Unified memory port 1910 for connecting the corresponding LSI and the unified memory is provided independently of the system bus intended to connect the LSI and the input/output devices. The unified memory port can be driven faster than system bus.

Abstract: A feedback path to the processor for a video signal in a computer. The video image data is not normally subjected to benchmark testing because it would make it susceptible to illegal copying. The digital video output signal is sent back to the processor one pixel at a time, with a delay between pixels equivalent to one line time. The result is that the pixel feed is so slow that digital copying is impractical. A lockout timer allows the pixel data to be sent to the processor only at intervals.

Abstract: An object of the present invention is to provide a display device in which a frame frequency does not decrease even in the case of employing a method for driving having little difference between reading time of a memory and writing time of a memory. According to the present invention, a reading device and a writing device are synchronized by determining allotment of two memories every cycle of a writing signal and by determining a start of reading through a start signal for writing and horizontal synchronizing signals.

Abstract: A graphics system may include a frame buffer, a processing device coupled to access data in the frame buffer, a frame buffer interface coupled to the frame buffer, and an output controller configured to assert a request for display data to provide to a display device. The frame buffer interface may receive the request for display data from the output controller and delay providing the request for display data to the frame buffer if the processing device is currently requesting access to a portion of the frame buffer targeted by the request for display data. For example, if the frame buffer includes several memory banks and the request for display data targets a first bank, the frame buffer interface may delay providing the request for display data to the frame buffer if the processing device is currently requesting access to the first bank.

Abstract: The present invention, a method of the arbitration of memory request for a computer graphics system, consecutively services the requests having the same type in the same period, thereby increasing the chance of page-hit. In this arbitration method, the length of a fixed period is defined by the 3-D graphics engine in accordance with the amount of memory cycles or the amount of the requests, and is used for controlling the amount of the requests of each type. The length of the period can be the cycles of servicing a block comprising a tile or several tiles. Alternatively, instead of defining a fixed length of the period, the 3-D graphics engine can choose another arbitration method of the present invention. Another arbitration method of the present invention is to mark a message at the end of the drawing block, so that the memory control can decide to rotate the service order to the next type of requests according to the block-end message received.

Abstract: A display FIFO memory management system and method includes a programmable FIFO emulator for emulating a drain and fill time of the display FIFO memory to automatically predict a number of register entries remaining in the display FIFO memory at each predefined clock cycle. A programmable timer/counter has programmable precision to accommodate varying bandwidths of display screen display modes and is used to determine the number of entries remaining so that the emulator can accommodate varying screen display modes. A FIFO controller controls the timing of fetching display data from memory to fill the display FIFO memory based on the prediction of the number of remaining register entries in the display FIFO by the programmable emulator.

Abstract: A programmable display controller for use in a digital imaging system has a video control register, a data access controller and a programmable modulator. The programmable display control is designed to be used with a digital imaging systems, such as digital cameras, having a variety of display different devices that require respective different control signals, different image signal modulations, and so on. The video control register stores video mode bits indicating the type of video signal to output. The data access controller has a buffer for requesting image data and storing the requested image data in the buffer. The programmable modulator, in response to the video mode bits, generates a video signal from the image data stored in the buffer. In some embodiments, a decoder detects and decodes a link code in received image data. An address generator is responsive to the decoder and outputs a link address corresponding to the decoded link code for fetching image data that is stored at the link address.

Abstract: An image processing apparatus and method, and a display apparatus capable of preventing field tearing caused by memory overrun even when performing a read operation and a write operation of input/output images with respect to a single image memory, wherein a system microcomputer (MC) is used for generating and supplying output delay data for delaying an image output timing based on the write speed to the image memory, the read speed from the image memory, and the read area so that the timing of access to the read end address address and the timing for performing a write operation to the same address match and of a scan converter for receiving the output delay data supplied by the system MC and delaying the image output timing so that the timing of access to the read end address and the timing for performing a write operation to the same address match.

Abstract: It is an object to provide a drive unit capable of properly responding to an access request from a microprocessor side and an access request from a display section side, and further of realizing a high-speed operation and a low power consumption operation. When an MPU access request from an MPU side and an LCD access request from an LCD side take place, an arbitration circuit (160) makes arbitration to start an access operation to a RAM (100) according to one of the access requests. Additionally, a memory access monitor signal /BUSY for monitoring an access state to the RAM is outputted to an external terminal to be inputted to a hardware wait control terminal of the MPU. The arbitration circuit starts the access operation on condition that a RAM precharge operation reaches completion. The MPU sets a start address and an end address on a column and a page and issues a writing start command, whereupon display data in a display area is rewritten automatically.

Abstract: The monitor system comprises the display device which has a screen having a display area virtually divided into a plurality of sub-screens. Provided are graphics adapters, each of which has two frame buffers, so as to correspond to the sub-screens of the display device.

Abstract: An apparatus and method dynamically controls the graphics and/or video memory power dynamically during idle periods of the memory interface during active system modes. In one embodiment, a memory request detector generates memory request indication data, such as data representing whether memory requests have been received within a predetermined time, based on detection of graphics and/or video memory requests during an active mode of the display system operation. A dynamic activity based memory power controller analyzes the memory request indication data and controls the power consumption of the graphics and/or video memory based on whether memory requests are detected.

Abstract: In one embodiment of the invention, an integrated device is described that employs a mechanism to control power consumption of a graphics memory controller hub (GMCH) through both voltage and frequency adjustment of clock signal received from a clock generator. The GMCH comprises a graphics core and a circuit to alter operational behavior, such as the frequency of a render clock signal supplied to the graphics core. The circuit is adapted to monitor idleness of the graphics core and reduce a frequency level of the render clock signal if the idleness exceeds a determined percentage of time.

Abstract: A dual-mode dual-data rate (DDR) synchronous dynamic random access memory (SDRAM)/synchronous graphic random access memory (SGRAM). An exemplary DDR SDRAM/SGRAM comprises a single memory device, which itself comprises a memory array and a logic circuitry. The logic circuitry is coupled to the memory array and is configurable to operate the single memory device in a first mode and a second mode. The first mode may include a delayed lock loop (DLL) capability while the second mode may include a non-DLL capability.

Abstract: On-screen-display graphics data is transmitted from a source device to a display device over an IEEE 1394-1995 serial bus network utilizing an isochronous data format. The on-screen-display graphics data is generated by the source device and transmitted to a display device, as a stream of isochronous data, separate from video data. Each packet of isochronous data within the stream of on-screen-display graphics data includes an address value corresponding to a memory address within the display device forming a buffer. When received by the display device the on-screen-display graphics data is loaded into the appropriate memory locations within the buffer corresponding to the address values. At the display device, an embedded stream processor is utilized to strip the header information from each packet and determine the appropriate memory location that the data is to be stored. A trigger packet is sent at the end of the data stream for a screen of on-screen-display graphics.

Abstract: An image display device includes a display panel having predetermined numbers of pixels defined in horizontal and vertical directions, respectively, and an interpolated-data generation circuit whereby an expanded image data is produced in such a manner that when the number of pixels in the horizontal direction of the display panel is greater than the number of pixels in the horizontal direction of a given image signal, the interpolated-data generation circuit directly stores a plurality of image data A, B, C, D, E of the original image signal along one horizontal line at data storage locations closest to the original locations, and data at data storage locations remaining after storing all original data are given the results X, Y, and Z obtained by calculation from two original image data at locations adjacent to the respective remaining data storage locations thereby expanding the original image signal to have a resolution well matched to the resolution of the display panel without causing a reduction in con

Abstract: A FIFO memory device, FIFO control method and graphics processing system are disclosed which incorporate spread-spectrum EMI compensation. In one embodiment, a FIFO memory device and method includes generating a spread-spectrum adjustment signal for a spread-spectrum FIFO based on an address offset associated with a read and write address associated with a spread-spectrum FIFO. The method includes adjusting the spread-spectrum clock signal in response to the spread-spectrum adjustment signal based on the address offset associated with the read and write address. A spread-spectrum FIFO receives data from a data source, such as a graphics data source, which may include a memory such as a RAMDAC. The data can be provided by a display engine or other suitable information provider.

Abstract: A line delay generator including a packetizing circuit, one port RAM and a RAM controller. The RAM controller provides the one port RAM with a write command to write packet data generated by the packetizing circuit, and with a read command to read any one or more packet data currently stored in the one port RAM, and output them as line delay data. The line delay generator can solve a problem involved in a conventional line delay generator in that because m (positive integer) two-port FIFOs must be connected in cascade to generate m line delay data, the FIFO memory becomes bulky.

Abstract: A method and apparatus for preventing over-prefetching from a buffer receives an address of a last data set item in a data buffer, and reads data from the data buffer into a read streamer buffer starting at a data buffer start address until the address of said last item.

Abstract: A memory architecture for a video transpose memory employs SDRAM memory devices which are arranged in memory rows such that elements in a single row may be accessed without memory set-up latency. The memory architecture includes at least two memory banks such that memory write operations to one bank may be interleaved with memory write operations to the other bank. Samples of the image along one direction are stored into the memory in groups such that corresponding samples in the orthogonal direction are held in the same memory row. The memory banks are interleaved on the store operation such that consecutive write operations access respective memory rows in the alternating memory banks. The number of samples in a group of samples is selected such that the total time for displaying the number of samples in the group is at least equal to the set-up latency of the memory. Accordingly, consecutive groups of samples may be stored into the alternating memory banks continuously.

Abstract: An embodiment of a memory controller that improves processor to graphics device throughput by reducing the frequency of retries of postable write transaction requests is disclosed. The memory controller includes a posted write buffer and a timeout counter. The memory controller is coupled to a processor via a host bus and is also coupled to a graphics device via a graphics bus. If the posted write buffer is unavailable when a first postable write transaction request is received by the memory controller, the memory controller stalls the host bus and waits for the posted write buffer to become available. If a second transaction request is received while the posted write buffers are unavailable, the timeout counter is initiated. If the posted write buffer becomes available before the timeout counter expires, the first postable write transaction request is completed.

Abstract: In a data transfer circuit, a hold signal generating circuit generates and outputs a hold signal Hold when transmission data is equal to transmission data one cycle before, and sets a 3-state output buffer for transmission data to high-impedance state, while, in a data reception circuit, when the hold signal Hold is valid, a data reception circuit outputs the reception data held, thereby power consumption in a data bus which is terminated with a terminal resistor is reduced.

Abstract: A display controller has a display data RAM, and generates a frame frequency in an internal oscillating circuit. A memory area of the display data RAM corresponds to a moving image display area of a liquid crystal panel. The liquid crystal panel is driven by moving image data read from the display data RAM at the frame frequency. In the display controller, display data generated at a frame frequency lower than the frame frequency from a display data generation circuit is written to the display data RAM. In this case, a control operation is performed such that the display data is read at the frame frequency after a write operation is performed precedently by at least one scanning line.

Abstract: The basic section of the multimedia data-processing system comprises CPU 1100, image display unit 2100, unified memory 1200, system bus 1920, and devices 1300, 1400, and 1500 connected to the system bus. In this configuration, the CPU is formed on LSI mounted on a single silicon wafer including instruction processing unit 1110 and display control unit 1140. Main storage area 1210 and display area 1220 are stored within the unified memory. Unified memory port 1910 for connecting the corresponding LSI and the unified memory is provided independently of the system bus intended to connect the LSI and the input/output devices. The unified memory port can be driven faster than system bus.

Abstract: An image processing apparatus and method of the same, and a display apparatus capable of avoiding occurrence of field tearing (memory overrun) even when performing a read operation and a write operation of input/output images with respect to a single image memory, wherein provision is made of a system MC for generating and supplying output delay data for delaying an image output timing based on the write speed to the image memory, the read speed from the image memory, and the read area so that the timing of access to the read end address (or the timing of access to the read start address) and the timing for performing a write operation to the same address match and of a scan converter for receiving the output delay data supplied by the system MC and delaying the image output timing so that the timing of access to the read end address and the timing for performing a write operation to the same address match.

Abstract: A transfer-target unit outputs commands for data reading and data writing. An address generator generates control signals in accordance with the commands, and outputs the number of bytes of data first transferred by read access. A command generator generates control commands in accordance with the control signals to control an SDRAM. At this time the command generator judges the number of transferred bytes to control so that the SDRAM executes instructions in order from an instruction which is the most efficient in data transfer. That is, in the case where data is read across a bank boundary, the command generator judges which is to be executed first between read processing in a bank 0 and active processing in a bank1, to control the SDRAM. A data processor mediates data transfer between the transfer-target unit and the SDRAM in accordance with the control commands.

Abstract: A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.

Abstract: In a rendering processing system having a rendering memory for storing rendering pixel data generated by a rendering operation circuit and a display memory for storing the image data of a current frame read out from the rendering memory, the display memory stores only the pixel data read out from the rendering memory with prescribed information excluded therefrom. Thus, it is possible to decrease the storage capacity of the display memory and also reduce the time required for writing data into the display memory.