Abstract: A method and system for improving data coherency in a parallel rendering system is disclosed. Specifically, one embodiment of the present invention sets forth a method, which includes the steps of receiving a common input stream, tracking a periodic event associated with the common input stream, generating a plurality of fragment streams from the common input stream, inserting a marker based on an occurrence of the periodic event in a first fragment stream in the multiple fragment streams, and utilizing the marker to influence the processing of the first fragment stream so that a plurality of raster operation (ROP) request streams maintains substantially the same coherence as the common input stream. Each fragment stream is independently processed and corresponds to one of the ROP request streams.

Abstract: Data is written to one of two frame buffers in write access cycles having write and non-write sub-periods. Data is read out to a display device from the other of the two frame buffers in read access cycles having read and non-read sub-periods. The writing of data and the reading of data are switched to a respective opposite frame buffer during a switching opportunity, a switching opportunity occurring when a read access cycle is in a non-read sub-period and a write access cycle is in a non-write sub-period. A count of the number of times a switching opportunity is not executed because a read access cycle is in a non-read sub-period while a write access cycle is in a write sub-period is incremented. If the count exceeds a particular threshold, a write access cycle subsequent to the count exceeding the threshold is masked. When a write access cycle is a masked data is not written into a buffer.

Abstract: A method of controlling an interface between an I2C master in a time controller for a liquid crystal display and an external memory may include causing a pre-scaler to determine whether or not a first clock signal from the I2C master to the external memory is synchronized with a second clock signal from the external memory to the I2C master. If the first clock signal is not synchronized with the second clock signal, the pre-scaler stops transmission of a third clock signal for an I2C interface with the external memory to the I2C master.

Abstract: Embodiments of the present invention provide for improved timing control in 2-D image processing to maintain a constant rate of memory fetches and pixel outputs even when the processing operations transition to a new line or frame of pixels. A one-to-one relationship between incoming pixel rate and outgoing pixel rate is maintained without additional clock cycles or memory bandwidth as an improved timing control according to the present invention takes advantage of idle memory bandwidth by pre-fetching a new column of pixel data in a first pixel block of a next line or frame while a new column of an edge pixel block on a current line is duplicated or zeroed out. As the edge pixel block(s) on the current line are processed, the data in the first pixel block of the next line or frame become ready for computation without extra clock cycles or extra memory bandwidth.

Abstract: A memory unit includes a buffer memory unit having first and second write buffer memories and first and second read buffer memories, and a frame memory section. The buffer memory unit is connected to the frame memory and a gray signal converter. The first and the second write buffer memories alternately store a sequence of data segments of current gray data from a signal source and alternately output the current data segments to the frame memory for storing. The first and the second read buffer memories read out a sequence of data segments of previous gray data from the frame memory and alternately output the previous data segments to the gray signal converter. The frame memory stores a plurality of previous and current data segments, and the total amount of the data segments stored in the frame memory is equal to or larger than those for one frame.

Abstract: A repeater comprises an EDID memory to store a control data and a memory control unit. The memory control unit is configured to make access to the EDID memory to read the control data therefrom, store the read control data into the EDID memory and, when access is made to the EDID memory by the set-top box, transfer the control data stored in the EDID memory to the set-top box. In this case, the memory control unit outputs an inhibiting signal to a set-top box to inhibit it from making access to the EDID memory until the completion of an operation of storing the control data from the EDID memory in the set-top box into the EDID memory in the repeater.

Abstract: A repeater comprises an EDID memory to store a control data and a memory control unit. The memory control unit is configured to make access to the EDID memory to read the control data therefrom, store the read control data into the EDID memory and, when access is made to the EDID memory by the set-top box, transfer the control data stored in the EDID memory to the set-top box. In this case, the memory control unit outputs an inhibiting signal to a set-top box to inhibit it from making access to the EDID memory until the completion of an operation of storing the control data from the EDID memory in the set-top box into the EDID memory in the repeater.

Abstract: Apparatus and methods are disclosed for controlling the memory controller and, in particular, controlling signaling of the memory controller to a memory via memory interface during a static screen condition. An apparatus includes static image detection logic that is configured to detect when image data being displayed by a display controller is static and to communication detection of static image data to the display controller. The apparatus also includes control logic within the display controller responsive to the static image detection logic, where the control logic is configured to detect a level of a line buffer within the display controller and to send a signal to a memory controller directing the memory controller to issue a signal to a memory to enter a self-refresh mode, thereby turning off at least one memory clocking circuit within the memory controller. A corresponding method is also disclosed.

Abstract: Presently disclosed are a method and apparatus for generating graphics in a protected manner by establishing a user graphics partition while in an executive context. Once the user context is established, an operating mode is switched to the user context and then executing a user graphics program while in the user context. The operating mode then reverts to the executive context when the user context expires.

Abstract: Values are calculated which control the manner in which a display streamer directs the movement of display data. The values are stored in the display streamer.

Abstract: A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.

Abstract: A timing controller includes a first stage removing a first surge signal generated during a first logic level period of a data enable signal, and a second stage receiving the data enable signal generated by the first stage and removing a second surge signal generated during a second logic level period of the received data enable signal.

Abstract: One embodiment of the invention sets forth a technique for compressing and storing display data and optionally compressing and storing cursor data in a memory that is local to a graphics processing unit to reduce the power consumed by a mobile computing device when refreshing the screen. Compressing the display data and optionally the cursor data also reduces the relative cost of the invention by reducing the size of the local memory relative to the size that would be necessary if the display data were stored locally in uncompressed form. Thus, the invention may improve mobile computing device battery life, while keeping additional costs low.

Abstract: A display error occurs upon contention between writing of pixel data in a GRAM and reading of pixel data representing a scanning line including pixels which correspond to the pixel data above. Pixel data corresponding to pixels representing a scanning line stored in a latch circuit is displayed on a display panel, and when contention occurs between writing of pixel data in a GRAM and reading of pixel data corresponding to pixels representing a scanning line to the latch circuit from the GRAM, a controller delays reading of the pixel data corresponding to the pixels representing the scanning line and controls so as to perform reading of the pixel data corresponding to the pixels representing the scanning line to the latch circuit from the GRAM once again.

Abstract: A repeater comprises an EDID memory to store a control data and a memory control unit. The memory control unit is configured to make access to the EDID memory to read the control data therefrom, store the read control data into the EDID memory and, when access is made to the EDID memory by the set-top box, transfer the control data stored in the EDID memory to the set-top box. In this case, the memory control unit outputs an inhibiting signal to a set-top box to inhibit it from making access to the EDID memory until the completion of an operation of storing the control data from the EDID memory in the set-top box into the EDID memory in the repeater.

Abstract: A technique for performing an anti-aliasing operation by multiple graphics processing units includes utilizing a first graphics processing unit to generate a first subset of filtered data resulting from performing anti-aliasing processing and similarly utilize a second graphics processing unit to generate a second subset of filtered data. The first graphics processing unit then pulls a first portion of the second subset of filtered data from a first memory block of a temporary buffer and blends such pulled data with a first portion of the first subset of filtered data. Overlapping in time with the pulling and blending operation of the first graphics processing unit, the second graphics processing unit pulls a second portion of the first subset of filtered data from a second memory block of the temporary buffer and blends such pulled data with a second portion of the second set of filtered data.

Abstract: When inputted pixels from an input DMA unit, a packing unit outputs data package. One data package consists of a inputted pixels. A memory control unit writes, on a write line memory at a write interval, the data package that is outputted by the packing unit. The write interval is a times longer than an input interval at which the pixels are inputted into the packing unit. During the writing process, the memory control unit reads out another data package from a read line memory at a read interval that is the same as the input interval. In addition, the memory control unit treats the write line memory as the read line memory, after completing the writing process. Alternatively, the memory control unit treats the read line memory as the write line memory, after completing the reading process.

Abstract: Apparatus and systems, as well as methods and articles, may operate to update video display pixels. A video display bus can communicate data to a video display according to specified clock frequencies and a refresh time period. Power conservation can be enhanced by adjusting the specified clock frequencies and/or refresh time period to provide idle time on the video display bus.

Abstract: A repeater comprises an EDID memory to store a control data and a memory control unit. The memory control unit is configured to make access to the EDID memory to read the control data therefrom, store the read control data into the EDID memory and, when access is made to the EDID memory by the set-top box, transfer the control data stored in the EDID memory to the set-top box. In this case, the memory control unit outputs an inhibiting signal to a set-top box to inhibit it from making access to the EDID memory until the completion of an operation of storing the control data from the EDID memory in the set-top box into the EDID memory in the repeater.

Abstract: Circuits, methods, and apparatus that adaptively control 1T and 2T timing for a memory controller interface. An embodiment of the present invention provides a first memory interface as well as an additional memory interface, each having a number of address and control lines. The address and control lines of the redundant memory interface may be individually enabled and disabled. If a line in the additional interface is enabled, it and its corresponding line in the first interface drive a reduced load and may operate at the higher 1T data rate. If a line in the additional interface is disabled, then its corresponding line in the first interface drives a higher load and may operate at the slower 2T data rate. In either case, the operating speed of the interface may also be considered in determining whether each line operates with 1T or 2T timing.

Abstract: The present invention provides a data accessing system and a data accessing method. The method comprises: separately storing a (N×M)-bit digital data in L banks of a data storage module; utilizing a register module of a data accessing interface module to transmit data of a bank for L times in sequence, and to receive and latch the digital data included by a bank from the data storage module when transmitting data each time, until the (N×M)-bit digital data is totally latched in the register module; and utilizing a multiplex output module of the data accessing interface module to continuously select a M-bit digital data from the (N×M)-bit digital data registered in the register module, and input the M-bit digital data to a data retrieving device via M data transmission lines.

Abstract: An interface unit 20 assigns different SDRAMs 1 and 2 to adjacent drawing blocks in a frame-buffer area. In processing that extends across the adjacent drawing blocks, active commands, for example, are issued alternately to the SDRAMs 1 and 2 to reduce waiting cycles resulting from the issue interval restriction. Furthermore, since individual clock enable signals CKE1 and CKE2 are output to the SDRAMs 1 and 2 so that burst transfers of the SDRAMs 1 and 2 can be stopped individually, no cycle is necessary to stop the burst transfers.

Abstract: A buffer management method implemented in a video image display apparatus for displaying images, including: controlling a write address in a buffer for writing input data thereto; controlling a read address in the buffer for reading display data therefrom; comparing the write address and read address; and managing a transmission of the display data to a spatial light modulator (SLM) based on a comparison result of comparing the write address to the read address.

Abstract: An apparatus includes a central processing unit having an output to provide a status indicator, a graphics controller having an output coupleable to a display interface, a cache comprising a plurality of cache lines, and memory controller having an input to receive the status indicator. The memory controller is configured to disable allocation of cache lines of the cache for cache misses for data requests from the graphics controller in response to the status indicator indicating the central processing unit is in an active mode. The memory controller further is configured to enable allocation of cache lines of the cache for cache misses for data requests from the graphics controller in response to the status indicator indicating the central processing unit is in an idle mode.

Abstract: Embodiments of methods and apparatus for memory training concurrent with data transfers are disclosed. For an example embodiment, data may be transferred from a first memory device to a first partition of a memory controller, and a training operation may be performed for a second partition of the memory controller coupled to a second memory device while the first partition of the memory controller is transferring data from the first memory device.

Abstract: A system of processing data in a graphics processing unit having a core configured to process data in hexadecimal form and other graphics modules configured to process data in quads includes a transpose buffer with a crossbar to reorganize incoming data, several memory banks to store the reorganized data over a period of several clock cycles, and a second crossbar for reorganizing the stored data after it is read from the bank of memories in one clock cycle. The method for converting between data in hexadecimal form and data in quads includes providing data in hexadecimal form, reorganizing the data provided in hexadecimal form, storing the reorganized data in several memories, and reading several of the memory locations, which contain all of the elements of the quad, in one clock cycle.

Abstract: A display control device and a display control method for use in a portable electronic apparatus are disclosed. The portable electronic apparatus includes a main controller and a display panel. The display control device includes a digital data register in communication with the main controller for storing a digital data display signal received from the main controller, and a digital-to-analog converter in communication with the digital data register, converting the digital data display signal stored in the digital data register into an analog data display signal and outputting the analog data display signal to the display panel to be revealed. The main controller keeps on outputting refreshed digital data display signals in a normal mode, and suspends the output of any further digital data display signal in an idle mode. In the idle mode, the digital data register reiteratively outputs a last stored digital data display signal to the digital-to-analog converter.

Abstract: A display driver having Dynamic Random Access Memory (DRAM) cells and a method of controlling the timing of the display driver are disclosed. The display driver includes memory cells each of which is implemented using a DRAM cell having a single transistor and a single capacitor. The display driver includes a drive control unit generating a scan signal, a refresh signal and a write/read signal, a word line drive unit driving word lines of the memory cells, and a data input/output unit for controlling input/output of data to/from the memory cells. The display driver gives priority to a write/read operation over a refresh operation and a scan operation.

Abstract: A display memory circuit includes a drawing memory and a dynamic display memory. The drawing memory stores data and at least a portion of the data are possibly rewritten into a new data at a third timing, the third timing being optional between a first timing and a second timing. The dynamic display memory is connected with the drawing memory, which latches the data in response to the first timing and continues to hold the data between the first timing and the second timing. The drawing memory is partially disconnected from the dynamic display memory in the rewritten portion when the portion is rewritten in the drawing memory.

Abstract: A method for converting a frame rate of a video signal comprising a data enable signal by means of a first buffer and a second buffer is disclosed. The method comprises: alternatively accessing the first buffer and the second buffer according to a first frame rate; determining an accessing time point of the first and the second buffers according to the data enable signal; and accessing the buffer, which is one of the first and the second buffers and not accessed at the accessing time point, according to a second frame rate, wherein the second frame rate is faster than the first frame rate.

Abstract: Architecture for compact multi-ported register file is disclosed. In an embodiment, a register file comprises a single-port random access memory (RAM). The single-port RAM comprises a single port for read operations and for write operations. Either a single read or a single write operation is performed for a given clock via the single port. Moreover, the single-port RAM serially performs N read operations and M write operations associated with a data group using a clock phase of (N+M) clock phases generated from a clock. In another embodiment, a semiconductor device includes the architecture for compact multi-ported register file. The semiconductor device comprises a plurality of register files. Each register file comprises a RAM comprising a port for read operations and for write operations. Moreover, each RAM serially performs N read operations and M write operations associated with one of a plurality of data groups using a corresponding clock phase of (N+M) clock phases generated from a clock.

Abstract: A printer specifies at least one arbitrary option out of a plurality of options displayed on a display screen as a tentative option, determines the tentative option as a determined option (determinate option), and performs printing based on the determinate option. When a handling explanation is requested before the determination, display is switched to display of the handling explanation from option display. A user can therefore easily and quickly view the handling explanation at once during operations.

Abstract: An address processing section allocates addresses of desired data in a main memory, input from a control block, to any of three hit determination sections based on the type of the data. If the hit determination sections determine that the data stored in the allocated addresses does not exist in the corresponding cache memories, request issuing sections issue transfer requests for the data from the main memory to the cache memories, to a request arbitration section. The request arbitration section transmits the transfer requests to the main memory with priority given to data of greater sizes to transfer. The main memory transfers data to the cache memories in accordance with the transfer requests. A data synchronization section reads a plurality of read units of data from a plurality of cache memories, and generates a data stream for output by a stream sending section.

Abstract: An apparatus comprises a first unit to receive a first frame. The first unit replaces each datum of the first frame with a datum having a particular value if the datum of the first frame is within a region of the first frame. A second frame is thereby created. The first unit also writes the second frame.

Abstract: A display unit includes: a display panel for displaying a plurality of information images; a memory for storing a plurality of image data elements corresponding to the information images; an image memory for storing the image data elements transferred from the memory; and a controller for controlling the display panel to display the information images based on the image data elements in the image memory. The controller transfers a part of the image data elements to the image memory on ahead when the display unit starts to operate, and the controller controls the display panel to display a part of information images on ahead based on the part of the image data elements.

Abstract: Overclocking parameters in a graphics system are automatically set. In one embodiment, in response to a user request, overclocking parameters for different sets of overclocking parameters are tested using a graphical stress test to select optimum overclocking parameters.

Abstract: A data transfer circuit that transfers a first kind of data stored in an external memory circuit includes: an internal memory circuit that is capable of, by an external circuit, writing and/or rewriting a second kind of data including information for one region as a transfer source in the external memory circuit and another region as a transfer destination in the external memory circuit; a transfer circuit that transfer the first kind of data; and a control circuit that makes the transfer circuit transfer the first kind of data stored in the one region to the other region based on the second kind of data.

Abstract: Disclosed is an image processing apparatus for inputting a plurality of rectangular images each composed of n×n pixels and outputting line-by-line image data in which one line is composed of n×n×m pixels. A line buffer stores n lines of image data, each line is composed n×n×m pixels. The apparatus generate a write address for writing a rectangular image to the line buffer memory and a read-out address for reading line-by-line image data out of the line buffer memory, and changes over a method of generating the write address between a first write-address generating method and a second write-address generating method whenever m rectangular images are written to the line buffer, and changes over the read-out address between a first read-out-address generating method and a second read-out-address generating method whenever n lines of image data are read out of the line buffer.

Abstract: The scan converter comprises first and second memories 3, 7, a frame memory 5; having a write period and a read period, a video data input circuit 2 for writing data at a first transfer rate into the memory 3, a video data output circuit 8 for outputting the data from the memory 7 at a third transfer rate. The transfer rate between the memories 3, 7 and the memory 5 is twice as fast as the first or third transfer rate, whichever is faster, and the memories 3 has data storage capacities greater than an amount of the data to be written into the memory 5 in each write period, and the memories 7 has data storage capacities greater than an amount of the data to be read from the memory 5 in each read period.

Abstract: A liquid crystal display device employing an overshooting driving method is provided which is capable of reducing memory capacity of a frame memory used to delay input data. The above liquid crystal display device for displaying an image using a liquid crystal panel includes a data converting table to generate output gray-scale data obtained by thinning out input gray-scale data to reduce a number of bits of input gray-scale data, a frame memory to generate second input gray-scale data by delaying output gray-scale data in a data converting table by one frame image display period in a liquid crystal panel and a look-up table to generate an overshooting gray-scale output being in advance stored according to a relation in size between the first input gray-scale data and the second input gray-scale data, wherein image display is performed by an overshooting gray-scale output in a liquid crystal panel.

Abstract: A receiver for recovering a serial clock of a transmitter is provided. The receiver comprises a buffer configured to store packets received from the transmitter. The packets may be sent through a packet switched network that may incur packet delay during transmission through the network. A memory controller is configured to determine a fill level of the buffer. A frequency generator is configured to generate a clock frequency, where the frequency is used to determine when to read packets from the buffer. A frequency controller is configured to instantaneously adjust the frequency of the frequency generator based on an algorithm that determines the clock frequency based on the fill level of the buffer. Accordingly, by adjusting the frequency outputted by the frequency generator, the frequency controller is able to recover the serial clock of the transmitter.

Abstract: A graphics processor or display device including a microcontroller that functions as a sequencer, a computer system including at least one such graphics processor or display device, and a microcontroller for use in such a graphics processor or display device. In preferred embodiments, the microcontroller functions as a sequencer for controlling the timing of power up and/or power down operations by one or both of a graphics processor and a display device. The microcontroller is implemented to exclude any capacity to handle interrupts and so can provide guaranteed timing, and is preferably implemented to be small, simple, and programmable, and to store a small number of programs. Each program consists of instructions belonging to a small instruction set, such as a set consisting of set and clear instructions (for overriding or overwriting specified register bits) and wait, release, and stop instructions.

Abstract: A memory device includes a memory cell array, an addressing circuit, a data communication circuit and a control circuit. The addressing circuit receives first signals that are indicative of an address associated with a write command, decodes the address to provide column select signals that are indicative of a column address in the memory cell array, and uses the column address to perform a column redundancy check. The data communication circuit latches data signals that are associated with the write command in response to a data strobe signal. The control circuit causes the addressing circuit to perform the column redundancy check during a delay to accommodate variations in the timing of the data strobe signal and begins providing the column select signals to the memory cell array after performing the column redundancy check. The memory device may be a double data rate (DDR) synchronous dynamic random access memory (SDRAM), for example.

Abstract: Methods and apparatus for changing the timing of memory requests in a graphics system. Reading data from memory in a graphics system causes ground bounce and other electrical noise. The resulting ground bounce may be undesirably synchronized with a video retrace signal sent to a display, and may therefore cause visible artifacts. Embodiments of the present invention shift requests made by one or more clients by a duration or durations that vary with time, thereby changing the timing of the data reads from memory. The requests may be shifted by a different duration for each memory request, for each frame, or multiples of requests or frames. The durations may be random, pseudo-random, or determined by another algorithm, and they may advance or delay the requests. By making the ground bounce and other noise asynchronous with the video retrace signal, these artifacts are reduced or eliminated.

Abstract: A common DRAM controller is provided for supporting a plurality of memory types such as double data rate or quad data rate mode or types. The controller is adapted to use a number of clock signals to process data. The controller can further delay the data for a predetermined time period and capture the same.

Abstract: This invention is directed to the active matrix display device with an imaging speed rapid enough for the moving image display and the small power consumption. The selector makes the switch between the moving image mode, where the image signal consecutively inputted is consecutively displayed after the certain processing is performed by the data processing unit and the still image mode, where the display is made based on the image signal stored in the frame memory. The messy display upon the switching between the modes can be prevented by differentiating the switching timing of the still to moving image mode from that of the moving to still image mode, improving the display quality.

Abstract: A dual-mode dual-data rate (DDR) synchronous dynamic random access memory (SDRAM)/synchronous graphic random access memory (SGRAM). An exemplary DDR SDRAM/SGRAM comprises a single memory device, which itself comprises a memory array including a quad-bank DRAM and a logic circuitry. The logic circuitry is coupled to the memory array and is configurable to operate the single memory device in a first mode and a second mode. The first mode may include a delayed lock loop (DLL) capability while the second mode may include a non-DLL capability.

Abstract: An apparatus for processing image data to produce an image for covering an image area of a display includes a plurality of graphics processors, each graphics processor being operable to render the image data into frame image data and to store the frame image data in a respective local frame buffer; a control processor operable to provide instructions to the plurality of graphics processors; and at least one merge unit operable to synchronously receive the frame image data from the respective local frame buffers and to synchronously produce combined frame image data based thereon.

Abstract: Disclosed are methods and systems for interfaces between video applications and display screens that allow applications to intelligently use display resources of their host device without tying themselves too closely to operational particulars of that host. Video applications (1) receive information about the display environment from a graphics arbiter, (2) use that information to prepare their video output, and (3) send their output to the graphics arbiter which efficiently presents that output to the display screen. The graphics arbiter tells applications the estimated time when the next frame will be displayed on the screen. Applications tailor their output to the estimated display time, thus improving output quality while decreasing resource waste by avoiding the production of “extra” frames. The graphics arbiter tells an application when its output is fully or partially occluded so that the application need not expend resources to draw portions of frames that are not visible.

Abstract: A processor executes image processing under control of a clock facility, such that a sequence of C effective clock cycles will effect a processing operation of a predetermined amount of image information. In particular, the processor has programming means for implementing programmable stall clock cycles interspersed between the effective clock cycles for implementing a programmable slowdown factor S, such that a modified number of C*S overall clock cycles will effect processing of the predetermined amount of digital signal information.