Abstract: Systems and methods for transitioning from buffering video to recording video. The control application receives a video and causes the video to be buffered until it detects a buffer full condition. Upon receiving the buffer full condition, the control application causes the media recorder to begin recording the newly received video as a recording, and designates the buffered video as part of the recording. In one method, the control application can be set to either record or play when the buffer becomes full. In other methods, the control application prompts the user for input indicating whether the video should be recorded or played when the buffer becomes full. In still other methods, the control application alerts the user as to how long a program may be paused before the buffer will become full.

Abstract: One embodiment of the invention sets forth a mechanism for retrieving and storing data from/to a frame buffer via a storage driver included in a GPU driver. The storage driver includes three separate routines, the registration engine, the page-fault routine and the write-back routine, that facilitate the transfer of data between the frame buffer and the system memory. The registration engine registers a file system, corresponding to the frame buffer, the page-fault routine and the write-back routine with the VMM. The page-fault routine causes a portion of data stored in a specific memory location in the frame buffer to be transmitted to a corresponding memory location in the application memory. The write-back routine causes data stored in a particular memory location in the application memory to be transmitted to a corresponding memory location in the frame buffer.

Abstract: Systems and methods for cache-based compressed display data storage are provided. One system includes memory operable to store compressed display data, a processor comprising a processing core and a cache, a cache storage module operably coupled to the memory and the processor, wherein the cache storage module is to initiate a storage of at least a portion of the compressed display data in the cache in response to an indication that the processing core is in an inactive mode. One method comprises, in response to an indication that a processor is in an inactive mode, transferring compressed display data from a frame buffer in memory to a cache associated with the processor, obtaining a first compressed display data from the cache, and decompressing the first compressed display data to generate a first uncompressed display data.

Abstract: A method controls display of an image by dividing a source image into a plurality of M×N blocks of pixels, selecting a first one of the blocks, and transferring the pixels in the first block from a source memory to a display memory, the pixels in the first block transferred based on orientation change information. The selecting and transferring steps are then repeated to transfer pixels in remaining ones of the blocks to the display memory. Each block corresponds to only a portion of the source image, where any given portion represents less than a full line of pixels in the source image.

Abstract: A display controller is provided. The display controller includes an external memory and a timing controller which compresses current frame data to generate front first in-first out (FIFO) input data, temporarily stores the front FIFO input data and writes the front FIFO input data to the external memory in a burst mode, and reads data from the external memory in the burst mode, temporarily stores the read data as back FIFO output data, and decodes the back FIFO output data to output previous frame data.

Abstract: A method for displaying thumbnails on a mobile device includes allocating at least two buffers in a storage system of the mobile device, where the at least two buffers comprise a displayed thumbnail buffer and a current thumbnail buffer. Indices of the thumbnails on are displayed on a display screen of the mobile device, and thumbnails from the displayed thumbnail buffer are read if the thumbnails correspond to the indices are found in the displayed thumbnail buffer. In addition, the method further includes reading the thumbnails from the current thumbnail and displaying the thumbnails on the display screen of the mobile device.

Abstract: An apparatus generally including an internal memory and a direct memory access controller is disclosed. The direct memory access controller may be configured to (i) read first information from an external memory across an external bus, (ii) generate second information by processing the first information, (iii) write the first information across an internal bus to a first location in the internal memory during a direct memory access transfer and (iv) write the second information across the internal bus to a second location in the internal memory during the direct memory access transfer. The second location may be different from the first location.

Abstract: Systems, devices, and methods for delivering and managing media whereby a first media element contains multiple media components and a combination of user activity and time are necessary to unlock a subset of the multiple media components. In one embodiment, the user activities include serving as a peer leader, purchasing a key that unlocks at least one of the multiple media components, and other activities having value to the system. The system may also update the media components individually, or in parallel. In addition, the requirements for unlocking one or more of the media components may vary dynamically, or the media components may vary based on: known individual characteristics of a user in a group of users, group characteristics of a subset of users within a group of users or other criteria.

Abstract: An image processing apparatus capable of providing a plurality of image processing functions includes: a first controller to execute and control a plurality of application programs; and a second controller to execute and control a part of the plurality of application programs. When the power of the image processing apparatus is turned on, the second controller completes the execution of the part of the plurality of application programs before the execution of the plurality of application programs by the first controller completes, and causes a part of the plurality of image processing functions provided by the part of the application programs executed by the second controller to be available for use by a user before the plurality of image processing functions becomes available for use by the user.

Abstract: To provide an image processing apparatus that changes methods of storage to a memory depending on image data to be input and improves overall image processing performance, as well as a control method of the image processing apparatus. To accomplish this, the present image processing apparatus changes methods in which input image data is stored depending on whether scanner image processing is to be performed by a system control unit that comprehensively controls the image processing apparatus or performed outside of the system control unit. Specifically, when performing scanner image processing in the system control unit, since input image data is to be input directly from a CCD, the image data is stored frame-sequentially in a memory. On the other hand, when performing scanner image processing outside of the system control unit, input image data is stored dot-sequentially in a memory.

Abstract: An apparatus for driving a light scanner and method thereof are disclosed. The present invention includes an apparatus for driving a light scanner, which scans an image on a screen, the apparatus comprising the light scanner driven by a drive signal, a sensing unit sensing a driving of the light scanner, a pixel clock signal generating unit generating a pixel clock signal by detecting a 90-degree phase difference between the drive signal and a sensing signal sensed by the sensing unit, a sync signal adjusting unit adjusting vertical and horizontal sync signals of an input video according to the pixel clock signal and a driving unit driving the light scanner according to the adjusted horizontal and vertical sync signals.

Abstract: A system includes a memory, a specialized processing unit and a processor. The processor receives data from a user and creates a first set of objects in a first structure based on the data. The system further creates, contemporaneously with the creation of the first set of objects and based on the first set of objects in the first structure, a second set of objects in a second structure, where the second set of objects is optimized for use by the specialized processing unit, and stores the first and second sets of objects in the memory. The specialized processing unit executes an algorithm based on the second set of objects.

Abstract: An image processing apparatus is configured to rasterize an object into a bitmap using a first memory and a second memory which can be accessed quicker than the first memory. The image processing apparatus includes an extraction unit configured to extract a plurality of objects to be rasterized on the second memory from a plurality of the objects, and a first combination unit configured to combine a plurality of objects which can be rasterized within capacity of the second memory from among the objects extracted by the extraction unit into an object.

Abstract: An information processing system stores a plurality of content data having different display qualities for each content in a storage unit, and detects a user operation to instruct switching of a content displayed on a display screen, and determines a switching speed of content display on the display screen based on the detected user operation, and decides a distribution for content data of each display quality to be read out to a temporary memory unit based on the determined switching speed, and reads out the content data from the storage unit to the temporary memory unit in accordance with the decided distribution.

Abstract: A method for using a state machine to control a pipelined L2 cache to implement memory transfers for a video processor. The method includes accessing a queue of read requests from a video processor, and tracking each of a plurality of cache lines stored within the cache using a least recently used variable. For each a cache line hit out of the plurality of cache lines and corresponding to one of the read requests, the least recently used variable is adjusted for a remainder of the plurality of cache lines. A replacement cache line is determined by examining the least recently used variables for each of the plurality of cache lines. For each cache line miss, a cache line slot corresponding to the replacement cache line is allocated to store a new cache line responsive to the cache line miss.

Abstract: Methods and apparatuses to create and manage volatile graphics objects in a video memory are disclosed. An object is created and marked as volatile. The volatile object is stored in a video memory of a graphics subsystem. A volatile marking indicates that data for an object is not to be paged out from the video memory to make room for other data. The video memory space occupied by the volatile object is indicated as a volatile storage, in a data structure. Another object is written into at least a portion of the video memory space, which is occupied by the volatile object, without paging out data for the volatile object. In one embodiment, at least a portion of the volatile object is referenced or used while another object is formed. The volatile object may be discarded after being referenced or used to form another object.

Abstract: In a single-instruction-multiple-data (SIMD) processor having multiple lanes, and local memory dedicated to each lane, a method of processing an image is disclosed. The method comprises mapping consecutive rasters of the image to consecutive lanes such that groups of consecutive rasters form image strips, and vertical stacks of strips comprise strip columns. Local memory allocates memory to the image strips. A sequence of functions is processed for execution on the SIMD processor in a pipeline implementation, such that the pipeline loops over portions of the image in multiple iterations, and intermediate data processed during the functions is stored in the local memory. Data associated with the image is traversed by first processing image strips from top to bottom in a left-most strip column, then progressing to each adjacent unprocessed strip column.

Abstract: A system comprises a memory storing data at addresses associated with pixels in images, each address being linked by a function to coordinates of a pixel in an ordered image reference frame, a device for processing the data associated with the pixels, where a pixel being processed is referenced by an associated vector relative to a reference pixel, and an interface device providing data to the processing device. A data request indicates a vector associated with a pixel being processed. The coordinates of the reference pixel are determined by applying the function to an address associated with the reference pixel. The coordinates of the pixel being processed are obtained based on the coordinates of the reference pixel and the vector. Then the address of the data associated with the pixel being processed is determined by applying the inverse function of the function to the coordinates of the pixel being processed.

Abstract: An image processing apparatus includes: a plurality of image processing units each of which is disposed so as to correspond to each of partial images and processes data of each of pixels composing the partial image with reference to data of peripheral pixels of the pixel, wherein the plurality of image processing units includes at least a first image processing unit which use data of pixels composing other partial images adjacent to a first partial image as the data of the peripheral pixels for the image processing on a first partial image, and a second image processing unit which performs the image processing on a second partial image and brokers data of pixels treated as the peripheral pixels by the first image processing unit from an image processing unit which processes the other partial image to the first image processing unit.

Abstract: A system for processing graphics data. The graphics processing system includes an embedded memory array having at least three separate banks of single-ported memory in which graphics data are stored. A memory controller coupled to the banks of memory writes post-processed data to a first bank of memory while reading data from a second bank of memory. A synchronous graphics processing pipeline processes the data read from the second bank of memory and provides the post-processed graphics data to the memory controller to be written back to a bank of memory. The processing pipeline concurrently processes an amount of graphics data at least equal to that included in a page of memory. A third bank of memory is precharged concurrently with writing data to the first bank and reading data from the second bank in preparation for access when reading data from the second bank of memory is completed.

Abstract: A computer readable medium embodies a set of instructions. The set of instructions includes an instruction to manipulate a processor to determine a first value representative of a source memory location of a source storage component, a second value representative of a destination memory location of a destination storage component, a third value representative of a number of lines of a data block to be transferred from the source storage component to the destination storage component, a fourth value representative of a number of bytes to be transferred per line of the data block, a fifth value representative of a byte width of the source storage component and a sixth value representative of a byte width of the destination storage component. The instruction further is to transfer a data block from the source storage component to the destination storage component based on the first, second, third, fourth, fifth and sixth values.

Abstract: A method and system for controlling the algorithmic elements in 3D graphics systems via an improved 3D graphics API is provided. In one aspect, in a 3D graphics system having privatized formats with privatized drivers used to increase the efficiency of display, existing problems are eliminated that are associated with multiple redundant copies of the publicly formatted graphics data made in host system memory pursuant to various graphics operations e.g., lock and unlock operations. The ability to make a system copy of publicly formatted data is exposed to the developer, eliminating the creation of unnecessary, and redundant copies. Efficient switching between the privatized and public format remains hidden from the developers so that applications execute efficiently while removing consideration thereof from the developers. Thus, developers are free to consider other tasks.

Abstract: A VLC data transfer interface is presented that allows digital data to be packed and assembled according to a format selectable from a number of formats while the data is being transferred to a desired destination.

Abstract: A method and system for interface compression in a raster stage of a graphics processor. The method includes receiving a graphics primitive for rasterization in a raster stage of a graphics processor and rasterizing the graphics primitive at a first level in a coarse raster component to generate a plurality of tiles related to the graphics primitive. The method determines whether a window ID operation is required for the plurality of tiles. If the operation is required, a respective plurality of uncompressed coverage masks for the tiles are output from the coarse raster component to a fine raster component on a one coverage mask per clock cycle basis. If the operation is not required, a compressed coverage mask for the tiles is output in a single clock cycle. The tiles are subsequently rasterized at a second-level in the fine raster component to generate pixels related to the graphics primitive.

Abstract: Methods, software, and apparatuses for graphics processing, including caching pixel data of one or more tiles of a graphics surface. Methods generally include setting a caching bit corresponding to the surface, setting tile pattern bits corresponding to tiles in the surface, and when the caching bit is active, storing one or more pixel values in a cache memory. When at least one tile contains pixels having the same value for at least one predetermined parameter, the caching bit and the corresponding tile pattern bits may be active. Apparatuses generally include a pixel memory, a cache memory, and a controller including logic configured to reserve the caching bit, tile pattern bits, and same pixel values in cache memory when the caching bit is active.

Abstract: An embodiment of the present invention provides a system and method for adaptive video decoding. A method for adaptive video decoding includes determining whether a resource constrained mode is to be initiated, and responsive to a determination that the resource constrained mode is to be initiated, initiating the resource constrained mode, including foregoing the decoding of portions of received video input. For example, adaptive video decoding may include foregoing the decompression and reconstruction of selected video frames during intervals of high demand for memory and/or bus bandwidth resources.

Abstract: A display controller which prevents the duplication of functional parts and processes and which displays dynamic content on a plurality of displays is provided. A terminal used as the controller has a shared dynamic image decoder which decodes the dynamic content. A first frame buffer used by the terminal stores the decoded dynamic content. A buffer transfer unit sends the dynamic content stored in the first frame buffer to a second frame buffer used by an external monitor. A terminal display displays the dynamic content stored in the first frame buffer on a display of the terminal. An external monitor interface displays the dynamic content stored in the second frame buffer on an external monitor.

Abstract: A display control device for controlling a display panel includes a contents frame rate detector detecting a contents frame rate of an input image data and outputting a repetitive frame number dependent from a display frame rate of the display panel and the detected contents frame rate; a frame memory for storing a level data of a previous frame; and an emulated level generator in communication with the contents frame rate detector and the frame memory. An output level data to the display panel is generated according to the repetitive frame number from the contents frame rate detector, the previous level data from the frame memory and an input level data of the input image data.

Abstract: A graphics animation and compositing operations framework has a layer tree for interfacing with the application and a render tree for interfacing with a render engine. Layers in the layer tree can be content, windows, views, video, images, text, media, or other types of objects for an application's user interface. The application commits state changes to the layers of the layer tree. The application does not need to include explicit code for animating the changes to the layers. Instead, an animation is determined for animating the change in state by the framework which can define a set of predetermined animations based on motion, visibility, and transition. The determined animation is explicitly applied to the affected layers in the render tree. A render engine renders from the render tree into a frame buffer. Portions of the render tree changing relative to prior versions can be tracked to improve resource management.

Abstract: A graphics display system integrated circuit processes analog video input, digital video input, and graphics input. The system incorporates a graphics accelerator that includes memory for graphics data. The accelerator preferably includes a coprocessor for performing vector type operations on a plurality of components of one pixel of the graphics data. The accelerator also includes an expanded instruction set for storing and loading data.

Abstract: A graphics processor or a graphics block for use in a processor includes a type buffer used for determining if a currently processed pixel requires further processing. Each pixel has a number of sub-pixels and each sub-pixel line includes at least one counter that is stored in an edge buffer. A limited edge buffer that can store edge buffer values in a limited range can be employed. Each buffer can include information regarding the whole screen or a portion of thereof. The edge buffer also can be an external or internal buffer, and when implemented internally, the graphics processor or graphics block need not employ a bi-directional bus.

Abstract: A method for determining the frequency distribution of the signal level of a measured signal measured respectively in overlapping observation intervals via a time or frequency raster. The method includes determining the incrementation of a memory cell in a first memory to be implemented for each measured signal level of the measured signal at a value of the time or frequency raster, and un-delayed summation of the incrementation determined for every memory cell of the first memory in every measurement cycle. The method also includes delayed summation of the incrementation determined for every memory cell of the first memory in every measurement cycle, and subtracting the result of the delayed summation of the incrementation determined for every memory cell of the first memory in every measurement cycle from the result of the un-delayed summation of the incrementation determined for every memory cell of the first memory in every measurement cycle.

Abstract: Virtualization of graphics resources and thread blocking is disclosed. In one exemplary embodiment, a system and method of a kernel in an operating system including generating a data structure having an identifier of a graphics resource assigned to a physical memory location in video memory, and blocking access to the physical memory location if a data within the physical memory location is in transition between video memory and system memory wherein a client application accesses memory in the system memory directly and accesses memory in the video memory through a virtual memory map.

Abstract: A method with quick response time applied to the electronic apparatus is provided. The method includes: providing a storage configured for storing a plurality of images; providing a cache memory configured for temporarily storing decoded images; invoking the images that are previously to and next to the currently displayed image from the storage, decoding the invoked images, and storing the decoded images in the cache memory; receiving an instruction from user input; determining whether the instruction is for displaying a previous image or a next image; and invoking the decoded image of the image from the cache memory and displaying the selected image. A related electronic apparatus is also provided.

Abstract: The invention relates to a programming method for a display driver, and the display driver and a display using the same. The programming method includes: providing programming data; providing a display buffer, which is used for pre-storing display data in a display period, in the display driver; providing a non-volatile memory, which is coupled to the display buffer through a data bus; and proceeding a programming procedure, which includes the steps of: inputting the programming data to the display buffer; and programming the programming data from the display buffer to the non-volatile memory through the data bus.

Abstract: A method of configuring an image for data storage on a storage device in an overlapping-tiled format and a method of displaying a desired image selected for viewing on a display are disclosed. The method of configuring an image for data storage includes formatting an image to include a plurality of image tiles, each image tile in the plurality of image tiles having at least a portion that is substantially identical to at least a portion of an adjacent image tile in the plurality of image tiles. The method further includes converting data of the image from data in a first color space into data in a second color space so as to reduce a size of the data of the image, and storing the image data in the second color space.

Abstract: A VLC data transfer interface is presented that allows digital data to be packed and assembled according to a format selectable from a number of formats while the data is being transferred to a desired destination.

Abstract: A programmable data processing circuit has a memory for storing pixel values, or more generally data values as a function of position in a signal. The programmable data processing circuit supports instructions that include an indication of a selected parameter value set that indicates how a plurality of data values must be arranged for parallel output from a memory. Instructions that indicate different parameter value sets can be executed intermixed with one another. The programmable data processing circuit responds to instructions of this type by retrieving the selected parameter value sets from a parameter storage circuit (246), and controlling a switching circuit (22) between a memory port (21) of a memory circuit (20) and a data port (26) at least partly dependent on the selected parameter value set.

Abstract: A system and method for performing zero-bandwidth-clears reduces external memory accesses by a graphics processor when performing clears and subsequent read operations. A set of clear values is stored in the graphics processor. Each portion of a color or z buffer may be configured using a zero-bandwidth-clear command to reference a clear value without writing the external memory. The clear value is provided to a requestor without accessing the external memory when a read access is performed.

Abstract: A system includes a memory, a specialized processing unit and a processor. The processor receives data from a user and creates a first set of objects in a first structure based on the data. The system further creates, contemporaneously with the creation of the first set of objects and based on the first set of objects in the first structure, a second set of objects in a second structure, where the second set of objects is optimized for use by the specialized processing unit, and stores the first and second sets of objects in the memory. The specialized processing unit executes an algorithm based on the second set of objects.

Abstract: A method of managing resources is provided. The method includes identifying a resource associated with a processor responsive to an impending transition, and copying the identified resource from a memory associated with the GPU or to the memory associated with the GPU.

Abstract: A display device includes a plurality of electronic papers that are each provided with a display surface outputting a piece of display data, a binding member that binds together the plurality of electronic papers, and an output device that controls output of the piece of display data to each of the plurality of electronic papers, a first storage device that stores rewrite information, a second storage device that stores a plurality of pieces of display data to be displayed on the plurality of electronic papers, an allocation device that respectively allocates the plurality of pieces of display data stored in the second storage device to a consecutive series of electronic papers for which the rewrite information permits rewriting, and a display control device that respectively displays the plurality of pieces of display data allocated by the allocation device on the consecutive series of electronic papers.

Abstract: A method for processing display data includes: storing an image data in a plurality of first-type memories by taking scanning line data as a unit; providing one of the scanning line data stored in a particular memory of the first-type memories to one of a plurality of second-type memories, the particular memory being one of the first-type memories, which are not receiving and storing the image data; and outputting the scanning line data stored in the second-type memories. Time periods for outputting the scanning line data of the image data from the second-type memories are not overlapped.

Abstract: Provided are a system for compensating response speed and a method of controlling frame data of an image. The system includes: a circuit for compensating response speed; an internal frame memory that comprises N sub frame memories formed in a single chip with the circuit for compensating response speed, wherein N is a natural number; a frame memory controller that comprises N sub frame memory controllers corresponding to each sub frame memory; and a data flow controller that comprises N write first-in-first-out (FIFO) circuits and N read FIFO circuits corresponding to each sub frame memory.

Abstract: A memory access system and method for efficiently utilizing memory bandwidth is disclosed. A data arrangement unit arranges video data into at least a primary block and a supplemental block, which are then stored in a memory device. The video data are arranged such that the video data of the primary block stored in the memory device can be sequentially read by a device, thereby increasing efficiency in memory bandwidth usage and memory data access.

Abstract: A screen update method includes identifying image resource data associated with a first image update event from a basic recording space in case that the first image update event occurs; loading the identified image resource data in a buffer space including a plurality of buffers, in which the image resource data are loaded in rotation on the buffer by a frame, respectively; sequentially determining the image resource data loaded on the buffer for each buffer, rendering the determined image resource data, and generating a first image at a first frame rate; generating a second image associated with a second image update event at a second frame rate in case that the second image update event occurs; compositing the first image with the second image to generate an entire image; and displaying the entire image on a display means.

Abstract: A self-emission type display device is disclosed. A current comparator circuit (47) in a data line drive circuit having a current compensating function (2) detects only the result of size comparison between the current amount due to the degeneration of a self-emission element and a reference value. The reduction of the current amount below the reference value is stored by being added to the least significant bits of a display data storage circuit (30). In accordance with the display data read from the storage circuit (30), a D/A conversion circuit (41) generates a write signal voltage.

Abstract: A storage system of an embodiment of this invention comprises a first transfer engine, a second transfer engine, a first storage device, a second storage device, a processor, and a transfer sequencer which is a device different from the processor. The processor creates transfer sequence information for indicating a sequence of transfers of user data. The transfer sequencer receives the transfer sequence information made by the processor and controls the first and the second transfer engines in accordance with the transfer sequence information. The first and the second transfer engines transfer user data between storage devices in accordance with instructions from the transfer sequencer.

Abstract: A method for interactively viewing a vector animation sequence, including receiving an indexed look-up table that stores a plurality of local vector objects associated with tile regions of a first vector image, indicating a request for a desired portion of a second vector image, for display at a specified resolution, determining tile regions of a pre-processed vector image, wherein the pre-processed vector image includes a plurality of tile regions and a plurality of local vector objects, each local vector object being associated with one of the tile regions, requesting at least one tile region of the pre-processed vector image from a server computer, receiving local vector objects and local vector object indices, extracting local vector objects from the indexed look-up table according to the local vector object indices, and generating the desired portion of the second vector image using the received local vector objects and the extracted local vector objects.

Abstract: A device for displaying data transfer rates on a display. The device includes a system for displaying the transfer rates in an alphanumeric mode or an alternative graphics mode; and a system for switching between displaying the transfer rates in the alphanumeric mode and the graphics mode.