Abstract: A system and method uses the capabilities of a geometry shader unit within the multi-threaded graphics processor to offload data compression computations from a central processing unit (CPU), reduce the memory needed to store image data, and reduce the bandwidth needed to transfer image data between graphics processors and between a graphics processor and a system memory. The multi-threaded graphics processor is also configured to compress data for use in memory paging and when data is relocated to lie within an accessible memory aperture. The data is losslessly compressed using a geometry shading program to produce variable length compressed data.

Abstract: A method for storing a first frame into a system, wherein the system includes i) a first chip, ii) a display controller, and iii) a copy device, and wherein the first chip includes a first memory. The method includes: reading, using the display controller, a first frame from a second memory, wherein the second memory is external to the first chip; and while the first frame is being read from the second memory by the display controller, using the copy device to copy the first frame from the second memory to the first memory. Subsequent to the copy device copying the first frame from the second memory to the first memory, the first frame is stored in both the first memory and the second memory.

Abstract: A method for interactively viewing a vector image, including indicating a request for a desired portion of a vector image, for display at a specified resolution, determining local rectangular regions of a pre-processed vector image that was generated from the vector image, from among a plurality of local rectangular regions, that are appropriate for generating the desired portion of the vector image therefrom, wherein the pre-processed vector image includes a plurality of local rectangular regions and a plurality of local vector objects, each local vector object being associated with one of the local rectangular regions, requesting at least one rectangular region of the pre-processed vector image from a server computer, receiving local vector objects associated with the requested at least one rectangular region of the pre-processed vector image from the server computer, and generating the desired portion of the vector image using the received local vector objects.

Abstract: A graphics animation and compositing operations framework has a layer tree for interfacing with the application and a render tree for interfacing with a render engine. Layers in the layer tree can be content, windows, views, video, images, text, media, or other types of objects for an application's user interface. The application commits state changes to the layers of the layer tree. The application does not need to include explicit code for animating the changes to the layers. Instead, an animation is determined for animating the change in state by the framework which can define a set of predetermined animations based on motion, visibility, and transition. The determined animation is explicitly applied to the affected layers in the render tree. A render engine renders from the render tree into a frame buffer. Portions of the render tree changing relative to prior versions can be tracked to improve resource management.

Abstract: An image generation apparatus provides correction for color offsets. Color offsets may be caused by misalignments in laser diodes or optics assemblies in a laser projector. The offsets may be measured during or after manufacture of the laser projector. An image buffer is responsive to the offset data to translate each color plane separately. The image buffer may include separately addressable portions for each color. Further, variable delay elements on the output of the image buffer may provide color offset correction. Interpolation provides further offset correction.

Abstract: An image converter converts an image rendered at a given vertical synchronous frequency into an image compatible with the specification of a display. A frame memory holds the image converted by the image converter by switching a plurality of buffers. A display controller selects one of the buffers in accordance with the vertical synchronous frequency of the display, and scans out the image from the frame memory accordingly. A switch instruction issuing unit issues a frame buffer switch instruction for designating a frame buffer to scan out from subsequently, in synchronization with the vertical synchronous frequency of the display, instead of immediately after the execution of an image converting process by the image converter.

Abstract: Registers 32a-32d hold data for pixels interleaved. An operator 34 reads the pixel data from the registers and processes the pixel data in accordance with a program code. The operator 34 writes the result of the process back to the registers via a cache 38 or writes it in a memory. Program counters PC0-PC3 provided in association with the number of pixels interleaved store the addresses of instructions in a program for the respective pixels. An instruction loader 76 alternately reads from the program counters. An incrementer 74 increments the count of the program counters. The instructions in the program for the pixels are alternately loaded and interleaved on a pixel by pixel basis, before being supplied to the operator 34 and the like.

Abstract: Systems, apparatus, methods and computer program products for rendering a graphical user interface by selectively compositing display contents are described. In general, for each of one or more content producers, where each content producer is associated with content storage containing display content, display content for output is identified depending on the content consumer to which the graphical user interface is being rendered.

Abstract: A display apparatus and a method for displaying an image are provided. The display apparatus includes a memory which stores one or more images; a communication unit which receives a universal serial bus (USB) video signal transmitted via a USB cable from an external apparatus, and receives a specific command signal from the external apparatus if the external apparatus starts to boot; and a main controller which determines that the external apparatus is being booted and causes the stored images to be displayed on a screen if the command signal is received through the communication unit.

Abstract: A computer system that initializes a fraction of the computer system's memory for execution of video during booting of the computer system is provided. The computer system can include a first portion of BIOS code on a ROM device, wherein the first portion includes instructions for initializing the fraction. The computer system further can include a second portion of BIOS code that copies itself to the fraction upon completion of initialization of the fraction, wherein the second portion executes on the fraction and wherein the second portion initializes system memory and initializes a video buffer. The computer system further can include a copy of the second portion located on the ROM device, wherein the copy of the second portion executes until video buffer initialization is completed but before all of the system memory is initialized. Further, the video buffer displays video before all of the computer system's memory is initialized.

Abstract: A system and method for processing graphics data which requires less read and write bandwidth. The graphics processing system includes an embedded memory array having at least three separate banks of single-ported memory in which graphics data are stored. A memory controller coupled to the banks of memory writes post-processed data to a first bank of memory while reading data from a second bank of memory. A synchronous graphics processing pipeline processes the data read from the second bank of memory and provides the post-processed graphics data to the memory controller to be written back to a bank of memory. The processing pipeline concurrently processes an amount of graphics data at least equal to that included in a page of memory. A third bank of memory is precharged concurrently with writing data to the first bank and reading data from the second bank in preparation for access when reading data from the second bank of memory is completed.

Abstract: Provided is a screen display control device including: a compression unit which compresses image data; a rewritable video memory in which the data compressed by the compression unit of image data of one frame including line data (Y (Y: natural number) pixels/one line) of X (X: natural number) lines is written asynchronously with reading; an expansion unit which expands the compressed data which is periodically read from the video memory in synchronization with a frame period of a screen display, and restores original image data; a display unit which displays an image of the image data expanded and restored by the expansion unit; an input image data holding unit which holds input image data of one frame including line data (X pixels/one line) of Y lines by M (M: natural number, M<Y) lines; and a data replacement control unit which performs a replacement process.

Abstract: A system comprises a memory storing data at addresses associated with pixels in images, each address being linked by a function to coordinates of a pixel in an ordered image reference frame, a device for processing the data associated with the pixels, where a pixel being processed is referenced by an associated vector relative to a reference pixel, and an interface device providing data to the processing device. A data request indicates a vector associated with a pixel being processed. The coordinates of the reference pixel are determined by applying the function to an address associated with the reference pixel. Next the coordinates of the pixel being processed are obtained based on the coordinates of the reference pixel and on the vector. Then the address of the data associated with the pixel being processed is determined by applying the inverse function of the function to the coordinates of the pixel being processed.

Abstract: A bit block transfer (Bitblt) circuit includes a read register, a write register, a bit shifting circuit and an overflowing register. The read register stores decomposition data including original data. The bit shifting circuit shifts the decomposition data in the read register to the write register and shifts bits of the decomposition data in the write register such that an initial bit of the original data of the decomposition data is situated apart from an initial address of the write register by a bit-shifting amount. The overflowing register coupled to the write register stores overflowing data of the original data overflowing from a memory length of the write register when the bits of the decomposition data in the write register are being shifted. The write register outputs and writes the decomposition data therein to a memory cell of a first memory.

Abstract: A peer-to-peer special purpose processor architecture and method is described. Embodiments include a plurality of special purpose processors coupled to a central processing unit via a host bridge bus, a direct bus directly coupling each of the plurality of special purpose processors to at least one other of the plurality of special purpose processors and a memory controller coupled to the plurality of special purpose processors, wherein the at least one memory controller determines whether to transmit data via the host bus or the direct bus, and whether to receive data via the host bus or the direct bus.

Abstract: One embodiment of the present invention sets forth a system for generating multiple video output signals from a single video pipeline within a graphics processing unit. Pixel data from more than one display surface is retrieved and multiplexed before being transmitted to a video pipeline for processing. The resulting video pixel data is routed to video output encoders, which selectively accept the video pixel data for transmission to attached display devices.

Abstract: A method and apparatus for creating, updating, and using guest physical address (GPA) to host physical address (HPA) shadow translation tables for translating GPAs of graphics data direct memory access (DMA) requests of a computing environment implementing a virtual machine monitor to support virtual machines. The requests may be sent through a render or display path of the computing environment from one or more virtual machines, transparently with respect to the virtual machine monitor. The creating, updating, and using may be performed by a memory controller detecting entries sent to existing global and page directory tables, forking off shadow table entries from the detected entries, and translating GPAs to HPAs for the shadow table entries.

Abstract: One embodiment of the present invention sets forth a technique for addressing data in a hierarchical graphics processing unit cluster. A hierarchical address is constructed based on the location of a storage circuit where a target unit of data resides. The hierarchical address comprises a level field indicating a hierarchical level for the unit of data and a node identifier that indicates which GPU within the GPU cluster currently stores the unit of data. The hierarchical address may further comprise one or more identifiers that indicate which storage circuit in a particular hierarchical level currently stores the unit of data. The hierarchical address is constructed and interpreted based on the level field. The technique advantageously enables programs executing within the GPU cluster to efficiently access data residing in other GPUs using the hierarchical address.

Abstract: Modification to frame buffer memory information associated with a first display may be used to update information displayed on a second display. The first display may be mapped to a matrix of display areas. The modification to the frame buffer memory information may be detected be detecting write memory address. One or more display areas affected by the modification to the frame buffer memory information may be identified based on display parameters associated with the first display. Frame buffer memory information associated with the one or more affected display areas may be retrieved and compressed before being transmitted over a communication link to be displayed on the second display.

Abstract: Techniques to generate partial display updates in a buffered window system in which arbitrary visual effects are permitted to any one or more windows (e.g., application-specific window buffers) are described. Once a display output region is identified for updating, the buffered window system is interrogated to determine which regions within each window, if any, may effect the identified output region. Such determination considers the consequences any filters associated with a window impose on the region needed to make the output update.

Abstract: The invention relates generally to computer memory access. Embodiments of the invention provide a multi-level page-walk apparatus and method that enable I/O devices to execute multi-level page-walks with an out-of-order memory controller. In embodiments of the invention, the multi-level page-walk apparatus includes a demotion-based priority grant arbiter, a page-walk tracking queue, a page-walk completion queue, and a command packetizer.

Abstract: A hardware-based aperture compression system permits addressing large memory spaces via a limited bus aperture. Streams are assigned dynamic base addresses (BAR) that are maintained in registers on sources and destinations. Requests for addresses lying between BAR and BAR plus the size of the bus aperture are sent with BAR subtracted off by the source and added back by the destination. Requests for addresses outside that range are handled by transmitting a new, adjusted BAR before sending the address request.

Abstract: A method for assisting in data calculation by using a display card: In the present method, input data stored in a system memory is transformed into texture data, which is then stored in a display memory of the display card. Then, a Graphic processing unit (GPU) of the display card is used for executing a texture calculation to the texture data, and a result of the texture calculation is stored in a display target of the display memory. Finally, the display target is outputted to the system memory as the output data. Accordingly, a part of calculation tasks of a central processing unit (CPU) can be given to the GPU of the display card when the CPU is in a high usage rate, so as to reduce a calculation burden of the CPU.

Abstract: One embodiment of the present invention sets forth a system for computing and error checking configuration parameters related to raster image generation within a graphics processing unit. Input parameters are validated by a hardware-based error checking engine. A hardware-based pre-calculation engine uses validated input parameters to compute additional private configuration parameters used by the raster image generation circuitry within a graphics processing unit.

Abstract: The present invention provides an image processing apparatus including: a production section configured to determine polygon groups each composed of a predetermined number of polygons juxtaposed in a first direction successively as an object block, which is an object of a production process, in an order in which the polygon groups are juxtaposed in a second direction substantially perpendicular to the first direction and produce apex data of the polygons which compose the object block in a unit of a polygon; and a determination section configured to store image data corresponding to those polygons which are positioned in a boundary portion of an immediately preceding block, which is a preceding object block to the object block, with respect to the object block from among those polygons which compose the immediately preceding block into a storage section for storing the pixel data in a unit of a data block to determine the number of the polygons which compose the polygon groups and are juxtaposed in the first

Abstract: A system stores a first object tree that describes a graphical scene in memory and creates a second object tree based on the first object tree, where the second object tree is optimized for use by a graphics processing unit (GPU) to render a graphical scene. The system receives indications of one or more changes associated with the first object tree and traverses the first object tree to make the one or more changes to the first object tree and to generate a composite command for use in making corresponding changes in the second object tree. The system executes the composite command to make the corresponding changes in the second object tree.

Abstract: A framework for performing graphics animation and compositing operations has a layer tree for interfacing with the application and a render tree for interfacing with a render engine. Layers in the layer tree can be content, windows, views, video, images, text, media, or any other type of object for a user interface of an application. The application commits change to the state of the layers of the layer tree. The application does not need to include explicit code for animating the changes to the layers. Instead, an animation is determined for animating the change in state. In determining the animation, the framework can define a set of predetermined animations based on motion, visibility, and transition. The determined animation is explicitly applied to the affected layers in the render tree. A render engine renders from the render tree into a frame buffer for display on the computer system.

Abstract: One embodiment of the invention sets forth a technique for compressing and storing display data and optionally compressing and storing cursor data in a memory that is local to a graphics processing unit to reduce the power consumed by a mobile computing device when refreshing the screen. Compressing the display data and optionally the cursor data also reduces the relative cost of the invention by reducing the size of the local memory relative to the size that would be necessary if the display data were stored locally in uncompressed form. Thus, the invention may improve mobile computing device battery life, while keeping additional costs low.

Abstract: A method of automatically recovering bit values of a control register includes storing command data inputted from a host in the control register and a portion of a graphic RAM (GRAM), and while a scanning operation is performed by the GRAM, outputting the command data stored in the GRAM to the control register and refreshing the control register.

Abstract: An image processing apparatus including a frame doubling processing part for generating a doubled image signal, a false impulse drive processing part for outputting a current image signal after dividing the doubled image signal, a first frame memory for outputting the current image signal as a previous image signal delayed by one sub-frame, a correction processing part for correcting a gradation level of the current image signal after the previous image signal and the current image signal being input thereto, a second frame memory for outputting a delayed doubled image signal from the doubled image signal, and a movement detector for outputting a movement detection signal after the delayed doubled image signal and the doubled image signal being input thereto is provided, wherein the correction processing part corrects the gradation level of the current image signal when the movement detection signal is a signal indicating a dynamic image.

Abstract: A state management sub-system that assists in transmitting and processing documents and messages between two applications in a sequentially correct order through an integration server is disclosed. The state management subsystem analyzes the message and enters state information about the message into a state management table. Once the message is transformed the state management subsystem check the status of the message in the state management table, and checks all waiting parameters. Depending on the status of the check, the state management subsystem changes the state of message in the table. Only when all messages have passed the waiting parameters check is a message posted to the destination system.

Abstract: A display controller unit for controlling a display on a display panel comprises a first set of registers to hold data to be displayed and a second set of registers loadable from the first set of registers. A set of multiplexers has first data inputs coupled to the first set of registers, second data inputs coupled to the second set of registers, and select inputs. Logic circuitry is coupled to the output of the set of multiplexers and to the control inputs of the multiplexers, the control circuitry providing select information to the set of multiplexers and providing waveforms to the display panel to selectively display data from the first set of registers and the second set of registers in accordance with the select information.

Abstract: Display data and video data are stored within a graphics processing unit to reduce power consumed by the computing device during video playback. Storing display data and video data within the GPU reduces power consumption, because bus transaction activity is reduced and the need to read data from a larger, common main memory is avoided.

Abstract: A display unit includes: a display panel for displaying a plurality of information images; a memory for storing a plurality of image data elements corresponding to the information images; an image memory for storing the image data elements transferred from the memory; and a controller for controlling the display panel to display the information images based on the image data elements in the image memory. The controller transfers a part of the image data elements to the image memory on ahead when the display unit starts to operate, and the controller controls the display panel to display a part of information images on ahead based on the part of the image data elements.

Abstract: Systems and methods for using multiple versions of programmable constants within a multi-threaded processor allow a programmable constant to be changed before a program using the constants has completed execution. Processing performance may be improved since programs using different values for a programmable constant may execute simultaneously. The programmable constants are stored in a constant buffer and an entry of a constant buffer table is bound to the constant buffer. When a programmable constant is changed it is copied to an entry in a page pool and address translation for the page pool is updated to correspond to the old version (copy) of the programmable constant. An advantage is that the constant buffer stores the newest version of the programmable constant.

Abstract: A method detects border tiles or border pixels of a primitive corresponding to an object to be displayed on a display screen. The detecting includes: calculating the number of border tiles or pixels covered by an edge of the primitive; identifying a plurality of vertices that divide the edge in a plurality of segments of equal length; calculating coordinates of the vertices; and associating a tile or pixel with the coordinates of each vertex. The number of vertices for the edge is greater than or equal to the number of border tiles or pixels.

Abstract: A system and method for adjusting pictures minimizes the impact on graphics processing performance of a discrete processor. A hybrid system configuration includes the discrete processor and an integrated processor, where the discrete processor typically consumes more power and provides greater processing performance compared with the integrated processor. A picture is produced by a video or graphics engine of a discrete processor within a hybrid system. Each picture is then transferred to a back buffer in the host processing memory. The picture is analyzed to produce picture analysis results that are used to generate adjustment settings. The back buffer is swapped to become the front buffer and the adjustment settings are applied to the picture by an integrated processor to display an adjusted picture. The adjustment may be used in conjunction with power saving techniques to maintain the image quality when display backlighting is reduced.

Abstract: A raster operations (ROP) unit interleaves read and write requests for efficiently communicating with a frame buffer via a PCI Express (PCI E) link or other system bus that provides separate upstream and downstream data transfer paths. One example of a ROP unit processes pixels in groups, performing read modify writeback sequences for each group. The read requests associated with pixels in a second group are advantageously interleaved with the writeback requests for pixels in the first group prior to sending the requests on the system bus.

Abstract: There is provided a screen update method and system including: a first step of identifying image resource data associated with a first image update event from a predetermined basic recording space in case that the first image update event occurs; a second step of loading the identified image resource data in a buffer space including a plurality of buffers, in which the image resource data are loaded in rotation on the buffer by a frame, respectively; a third step of sequentially determining the image resource data loaded on the buffer for each the buffer, rendering the determined image resource data, and generating a first image at a first frame rate; a fourth step of generating a second image associated with a second image update event at a second frame rate in case that the second image update event occurs; a fifth step of compositing the first image with the second image to generate an entire image; and a sixth step of displaying the entire image on a predetermined display means.

Abstract: Methods and systems for applying visual effects to active content, such as buttons, comboboxes, video, edit fields, etc., wherein interactivity of the active content are retained thereafter. Also, the present disclosure provides a mechanism for developers to build new visual effects and have them applied to active content.

Abstract: A system including a first chip, a display controller and a copy device. The first chip includes a first memory. The display controller is configured to read a first frame from a second memory external to the first chip. The copy device is configured to copy the first frame from the second memory to the first memory while the display controller reads the first frame from the second memory. Subsequent to the copy device copying the first frame from the second memory to the first memory, the first frame is stored in both the first memory and the second memory.

Abstract: A video display apparatus that supports a display data channel (DDC) standard includes: one DDC-supported non-volatile memory and a control unit for writing, based on information indicating the kind of input video signal, extended display identification (EDID) data for this input video signal out of EDID data for plural kinds of video signals into the DDG-supported non-volatile memory. Accordingly, in the video display apparatus that supports DDC, it becomes possible to make the host side perform settings for plural kinds of video signals in accordance with properties of the video display apparatus, and also a reduction in cost and down-sizing are facilitated.

Abstract: One embodiment of the present invention sets forth a system for computing and error checking configuration parameters related to raster image generation within a graphics processing unit. Input parameters are validated by a hardware-based error checking engine. A hardware-based pre-calculation engine uses validated input parameters to compute additional private configuration parameters used by the raster image generation circuitry within a graphics processing unit.

Abstract: An image data transfer method including the steps of: (a) reading pixel data of a two-dimensional image stored in a first image storage and having a plurality of pixels, the position of each of the pixels being represented by coordinates of first and second directions, the pixel data being read by scanning data transfer units of the pixel data in the second direction where each of the data transfer units is formed by data of a predetermined number of pixels consecutive in the first direction; (b) writing the data transfer units read at step (a) in a temporary data storage where data is stored at a position designated by a combination of first and second addresses, the data transfer units being written in burst mode in a region of the temporary data storage in which the first addresses are consecutive while the second address is fixed; and (c) reading the data transfer units written in the temporary data storage from the region in which the first addresses are consecutive while the second address is fixed in b

Abstract: An imaging system for use with an external memory system, an external memory system for use with an imaging system, and methods for archiving digital content are provided. The imaging system has a source of content data files and a communications link adapted to exchange data with the external memory system. A processor is adapted to prepare content data files for archival storage on the external memory system and to cause the external memory system to store the prepared content data files.

Abstract: A method comprises storing pixel data in a frame buffer, retrieving the pixel data from the frame buffer and processing at least one pixel value of the pixel data to generate an output pixel bit stream. The method further comprises storing pixel values in a first update buffer. The pixel values are derived from the output pixel bit stream. The method also comprises providing the pixel values from the first update buffer across a network to a remote graphics system.

Abstract: A method and system for implementing transfers of texture data in a computer system. The method includes the step of accessing a first block of texture data in a low latency memory, the first block having a predetermined size and accessing a second block of texture data in high latency memory, the second block having the predetermined size. The first block of texture data is copied from the low latency memory to a transfer space in high latency memory having the predetermined size. The second block of texture data is written from the high latency memory to the low latency memory, wherein the second block overwrites the first block. What used to be the transfer space is now treated as the first block now placed in high latency memory, and what used to be the second block is now treated to be the new transfer space.

Abstract: A system for processing image data from a plurality of images is disclosed. The invention involves alpha blending of two images of different resolution and color space utilizing shared logic for multiple image streams and without display storage frame buffer. The invention utilizes Direct Memory Access (DMA) fetching module for fetching image data from source images or from source image memory areas and transferring the data to another memory area without having to go through a central processing unit or display storage frame buffer. The DMAs are configured with direct registers or memory mapped descriptors as to the location of the source data. The DMA channels of the DMA module will fetch a portion of the source images (tiling) utilizing a link list or series of descriptors in a certain fetching order. The DMA modules can perform the alpha blending on the fetched image data.

Abstract: A memory manager interfaces between a rendering application and the driver controlling one or more memories. A multi-level brick cache system caches bricks in a memory hierarchy to accelerate the rendering. One example memory hierarchy may include system memory, AGP memory, and graphics memory. The memory manager allows control of brick overwriting based on current or past rendering. Since different memories are typically available, one or more memory managers may control storage of bricks into different memories to optimize rendering. Management of different memory levels, overwriting based on current or previous rendering, and an interfacing memory manager may each be used alone or in any possible combination.

Abstract: A multimedia data processing apparatus with reduced buffer size includes an accessing unit and a data processing module. The accessing unit has a plurality of buffers therein. The data processing module includes a processing unit and a real-time buffer. The processing unit processes the data temporarily stored in the accessing unit and the real-time buffer. By adding the real-time buffer, the size of the buffer in the accessing unit and the maximum bandwidth requirement can be reduced thereby increasing the system performance.