Abstract: A non-buffered video line memory eliminates the need for double buffering video data during processing. While most double buffering systems double the amount of memory necessary to store video data, a non-buffered approach reduces the hardware memory costs substantially. A set of write and read pointers coupled with write and read incrementors allows data to be stored in raster order and removed in block order from a non-buffered memory device. The incrementors, in conjunction with a set of write and read pointers generate a base address for data to be written to and read from the non-buffered memory at substantially the same time. Encoding systems benefit substantially by being able to read and write information into a common memory rather than continuously switching between two different memories, by reducing complexity and cost.

Abstract: A system and method for efficiently scheduling memory access requests. A semiconductor chip includes a memory controller for controlling accesses to a shared memory and a display controller for processing frame data. In response to detecting an idle state for the system and the supported one or more displays, the display controller aggregates memory requests for a given display pipeline of one or more display pipelines prior to attempting to send any memory requests from the given display pipeline to the memory controller. Arbitration may be performed while the given display pipeline sends the aggregated memory requests. In response to not receiving memory access requests from the functional blocks or the display controller, the memory controller may transition to a low-power mode.

Abstract: An apparatus generally having a plurality of memories and a first circuit is disclosed. The memories may be configured to store a plurality of first data points. The first data points generally form a two-dimensional block. The first data points may be arranged among the memories such that a load cycle from the memories accesses a rectangular region of the two-dimensional block. The load cycle generally comprises a plurality of read cycles, a different one of the read cycles corresponding to each one of the memories. The first circuit may be configured to (i) receive the first data points as read from the memories and (ii) generate a plurality of second data points by a video codec transformation of the first data points between a spatial domain and a frequency domain.

Abstract: A video sequence control system that includes an input video frame buffer and an output video frame selection component is described. The input video frame buffer receives input video frames from a video source. The output video frame selection component determines the video frame to be output according to a scheduler that provides timing information and modulation information. The timing information includes information regarding when a video frame will be output. The modulation information varies dependent upon the frame types available to be output, wherein the available frame types include at least image frames from the input video frame buffer and functional frames, wherein the at least image frames and functional frames are output according to a pattern defined by the scheduler. In addition based on the timing information, a synchronization output signal is output corresponding to the output of the functional frame.

Abstract: An adder adds, to a luminance value indicated by the image signal of the nth frame, a correction value corresponding to a combination of a luminance value indicated by the image signal of the nth frame and one indicated by the image signal of the (n+1)th frame. The adder outputs an image signal having the luminance value after addition as the image signal of the nth frame.

Abstract: A method for video coding is described. A compressed bitstream is received from a host via a data link. Each slice of the compressed bitstream is mapped to a compressed frame buffer. The compressed frame buffer supports selective overwriting for regional updates. Parallel processing of the compressed data in the compressed frame buffer is performed. Pixel data is written to a display panel.

Abstract: Systems and methods for hardware-accelerated key color extraction are disclosed. An update corresponding to a portion of a digital representation of a display screen is received. Key color information for locations within the update is identified. A data structure code associated with the portion of the digital representation of the display screen is determined based on the identification of the key color information. The data structure code is provided to a data structure. During a scan of the frame buffer for display, the frame buffer is capable of being read according to the data structure.

Abstract: A projector includes: an image processing section adapted to perform image processing based on image information; a image projection section adapted to project an image based on an image signal output from the image processing section; a communication section adapted to connect to a network; and a control section adapted to transmit usage information including one of an image content of the image information and a projection environment for projecting the image to an information provision server via the communication section and the network, then receive operation setting information, which is prepared by the information provision server in accordance with the usage information, from the information provision server, and then adjust a projection operation, which is performed by the image processing section and the image projection section, based on the operation setting information.

Abstract: The video output system in a computer system reads pixel information from a frame buffer to generate a video output signal. In addition, a full-motion video may also be displayed. Reading from both the frame buffer and the full-motion video buffer when displaying the full-motion video window wastes valuable memory bandwidth. Thus, the disclosed system provides a system and methods for identifying where the video output system must read from the frame buffer and where it must read from the full-motion video buffer while minimizing the amount of area it reads from both the frame buffer and the full-motion video buffer.

Abstract: An operation terminal for remotely operating an electronic apparatus includes a processing unit for remotely communicating with the electronic apparatus in accordance with a program, a memory on which the processing unit performs writing or reading of data, a nonvolatile memory for storing a basic screen image drawing command for drawing a basic screen image that is displayed before the operation terminal is operated, a drawing processor for creating a bitmapped image of the basic screen image in accordance with the basic screen image drawing command, and a display unit for displaying the bitmapped image on a screen.

Abstract: An electronic device has a display, a video memory, a video data buffer unit, a central processing unit, and a video processing unit. The central processing unit, according to a number of divided screens and a resolution for each of the divided screens, retrieves different but continuous video data corresponding to the resolution of each of the divided screens from the video data buffer unit, and stores the retrieved continuous video data in consecutive memory addresses in the video memory. The video processing unit reads in sequence the continuous video data stored in the video memory, and sends the continuous video data in sequence to the display according to a direction of arrangement of the divided screens such that video contents displayed on the divided screens by the display are continuous.

Abstract: A computer-implemented method for estimating a pose of an articulated object model that is a computer based 3D model of a real world object observed by one or more source cameras, including the steps of obtaining a source image from a video stream; processing the source image to extract a source image segment maintaining, in a database, a set of reference silhouettes, each being associated with an articulated object model and a corresponding reference pose; comparing the source image segment to the reference silhouettes and selecting reference silhouettes by taking into account, for each reference silhouette, a matching error that indicates how closely the reference silhouette matches the source image segment retrieving the corresponding reference poses of the articulated object models; and computing an estimate of the pose of the articulated object model from the reference poses of the selected reference silhouettes.

Abstract: A method encodes or decodes a frame (also file), such as a video, graphic, media, or other frame or data, representing a real-time graphic output from a frame buffer, output by a video camera, or another file or data. The file includes frames each comprising macroblocks. Reference frame buffers (PFTs), virtual frame buffer tables (VFTBs) of equal number to the PFTs, each VFTB corresponds to a respective PFT, and respective sectors of each PFT for respective macroblocks are created. Frames of the file are encoded/decoded by successive encode/decode of macroblocks. A pointer is created in the VFBT associated with the PFT rather than encoding/decoding any matching macroblock. The pointer and its reference are relied on for each already encoded/decoded macroblock retained in the PFT. Processing, memory, bandwidth and power requirements for encoding or decoding are reduced.

Abstract: A portable electronic device is provided. The portable electronic device includes a processor for providing encoding data and an LCD module coupled to the processor. The processor includes an encoder for encoding a frame data to generate the encoding data. The LCD module includes a driver and an LCD coupled to the driver. The driver includes a decoder for decoding the encoding data to obtain an image data. The LCD displays the image data.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for analyzing data. In one aspect, a mixer server receives a request for a visualization of television reporting data, translates the request for the visualization of the television reporting data into sharded requests, and provides each sharded request to a respective shard server. Each shard server processes a respective proper subset of the television reporting data to generate data representing the visualization, and provides the data representing the visualization to the mixer server. The mixer server aggregates the data representing the visualizations received from each of the shard servers, and provides the aggregated data representing the visualization as a response to the request for the visualization of the television reporting data.

Abstract: An image processing system includes a memory, a data slicer and an image processor. The data slicer divides each of current image data and adjacent image data into a first portion and a second portion to be stored into the memory. The image processor reads from the memory the first portion and the second portion of the current image data and the first portion of the adjacent image data for image processing.

Abstract: An apparatus configured to match an input frame rate of a video stream with an output frame rate of an output stream, the apparatus comprising, at least one memory buffer, an output frame generator, and a threshold measurement unit, the threshold measurement unit configured to generate a control feedback, wherein the box is configured to analyze the control feedback to monitor a state of the at least one memory buffer, the threshold measurement unit further configured analyze the control feedback to regulate between two or more different settings, wherein the two or more different settings include slowing down or speeding up the output frame, wherein the two or more different settings further include slowing down or speeding up of the line rate of the output stream.

Abstract: In one embodiment, the present invention is a t-commerce platform, which is linked to the content from a video signal that the user is currently watching. At some point during the broadcast of the content, a close-up of the product is shown. Simultaneous with this, a VBI-based trigger is added to the video signal of the broadcast. This trigger causes the television, a set-top box, or a similar device to capture in a memory, a “freeze-frame” of the image being shown. This action is transparent to the user while the video being displayed on the television is continuing normally. If the user chooses to perform an interactive “buy” transaction the saved image data is used as part of the interactive screen display.

Abstract: A video processing device includes a video processing unit that decodes a video input signal into a decoded video signal in accordance with a video compression protocol, based on uncompressed video frame data. A tile engine includes a tile accumulation module that accumulates the uncompressed video frame data into a plurality of tile units, wherein each of the plurality of tile units includes a plurality of video span units. A tile compression/decompression module generates compressed video frame data for storage in a compressed video frame buffer by compressing the plurality of video span units into a plurality of compressed video span units and further that retrieves the compressed video frame data from the compressed video frame buffer by retrieving the plurality of compressed video span units and generating the uncompressed video frame data by decompressing the plurality of compressed video span units.

Abstract: In an embodiment, a host computing device includes an internal display and also includes a connector to connect to an external display. A cable is provided to connect to the connector and to connect to the external display. The cable includes video processing capabilities. For example, the cable may include a memory configured to store a frame buffer. The frame buffer may store a frame of video data for further processing by the video processing device in the cable. The video processing device may manipulate the frame in a variety of ways, e.g. scaling, rotating, gamma correction, dither correction, etc.

Abstract: In one embodiment, a display device comprises a graphics interface, an image processing system, an input device coupled to the image processing system to receive a screen capture signal and transmit the screen capture signal to the image processing system, and a storage subsystem coupled to the image processing system to store, in response to the screen capture signal, screen capture data generated by the image processing system.

Abstract: A scanning image display apparatus includes a light source unit (1) that emits a laser beam, a scanning mirror (3) that two-dimensionally scans the laser beam in a first direction and in a second direction that crosses the first direction at predetermined scanning frequencies, respectively, a frame buffer (5) that temporarily stores image data corresponding to images to be displayed on a display screen frame by frame, and a display controller (4) that generates display data used to modulate an intensity of the laser beam at a predetermined frame frequency using the read image data and causes the light source unit to emit the laser beam intensity-modulated based on the display data. The frame buffer is so configured that the respective image data of a plurality of different frames can be temporarily stored therein and read therefrom.

Abstract: Methods and systems for processing video data are disclosed herein and may include determining a first video format associated with video data to be displayed on a first video display communicatively coupled to a single mobile multiple media processor that supports a plurality of display formats. The single mobile multiple media processor may be integrated within a mobile device. An amount of the video data that is transferred from memory to the first video display, by a DMA controller, may be restricted based on the determined first video format associated with the video data to be displayed on a first video display. Only the restricted amount of the video data that is to be displayed by the first video display may be transferred from the memory to the first video display by the DMA controller.

Abstract: Embodiments of the invention may include an apparatus that may include a graphics processor operable to generate video frames. Further, a screen refresh controller may be communicatively coupled with the graphics processor, wherein the screen refresh controller is operable to receive generated video frames from the graphics processor and send framelock signals to the graphics processor. In addition, a display device may be communicatively coupled with the screen refresh controller, wherein the display device is operable to receive and display video frames from the screen refresh controller.

Abstract: Image latency is reduced in a video display system where an image is displayed for a stroke video frame period. The system has a display device and a plurality of memory buffers, each of which is adapted to receive image data (in a receiving condition) or to display data to the display device (in a display condition). The stroke video frame period is divided into at least two time periods and the number of memory buffers provided is at least the number of time periods per stroke video frame period. One of the memory buffers is in the display condition for a first time period, with the remaining memory buffers in the receiving condition. At the end of the time period, the memory buffers are rotated so that the displayed memory buffer moves to the receiving condition and one of the receiving buffers moves into the display condition.

Abstract: Embodiments provide techniques for generation and outputting of display data. For instance, embodiments provide features involving frame data storage within display devices. Also, embodiments provide features involving the isolation of different user contexts to different frame buffers. Further, embodiments provide efficient techniques for saving frame data upon the transitioning between power states. Moreover, embodiments provide techniques for flexibly and dynamically allocating multiple display content to a physical display.

Abstract: The present invention relates to a display device for a glass cockpit of an aircraft, intended to provide video streams to a plurality of viewing screens of said glass cockpit, said aircraft being partitioned into a secured area, a so-called avionic world (AW), and a non-secured area, a so-called open world (OW), said system comprising at least one first port intended to receive first data to be displayed from a system (210, 310, 410) belonging to the avionic area and at least one second port intended to receive second data to be displayed from a system (220, 320, 420) belonging to the open world, the display device comprising: predetermined hardware resources allocated to the processing of the second data; a processor (241, 341, 441), belonging to the avionic area, adapted to controlling the hardware resources used by said processing and interrupting this processing if said hardware resources used exceed said allocated resources.

Abstract: Systems and methods are described including creating a mask that indicates which pixel groups do not need to be loaded from Graphics Memory (GMEM). The mask indicates a pixel group does not need to be loaded from GMEM. The systems and methods may further include rendering a tile on a screen. This may include loading the GMEM based on the indication from the mask and skipping a load from the GMEM based on the indication from the mask.

Abstract: Systems and methods for an efficient display data transfer algorithm over a network are disclosed. A compressed frame buffer update transmitted from a server via a network is received by a hardware decompression engine. The hardware decompression engine identifies one or more palette entries indicated in the compressed frame buffer update and determines whether the one or more palette entries is stored in a palette cache of the hardware decompression engine. If the one or more palette entries is not stored in the palette cache, the hardware decompression engine writes the one or more palette entries from an external palette memory to the palette cache. Decompressed display data is generated based on the compressed frame buffer update using the palette cache. The decompressed display data is written to an output buffer of the hardware decompression engine.

Abstract: A hybrid display frame buffer for a display subsystem. An embodiment of an apparatus a first logic to split a video image into a first data portion and a second data portion; a display frame buffer including a first memory component having a first type of memory and a second memory component having a second type of memory, the first logic to write the first data portion to the first memory component and the second data portion to the second memory component; and a second logic to read the first data portion from the first memory component and the second data component from the second memory component, and to combine the first data portion and the second data portion to generate a combined video image.

Abstract: An image processing apparatus is provided that includes a main memory; at least one sub-memory that stores data, a cache memory that temporarily stores data, and controller that controls whether to temporarily store the data in the cache memory selectively with respect to each of the at least one sub-memory.

Abstract: An information processing apparatus comprising: a reception unit adapted to receive a packet containing first data to be stored in a storage unit, a first address indicating an address of second data held in the storage unit, and a second address indicating an address at which the first data is to be written in the storage unit; an access unit adapted to read out the second data from the storage unit based on the first address, and write the first data in the storage unit based on the second address; and a transmission unit adapted to replace the first data of the packet received by the reception unit with the second data read out by the access unit, and transmit the packet.

Abstract: A method for synchronizing an input data stream with an output data stream in a video processor. The method includes receiving an input data stream and receiving an output data stream, wherein the input data stream and the output data stream each comprise a plurality of pixels. The method further includes sequentially storing pixels of the input data stream using an input buffer and sequentially storing pixels of the output data stream using an output buffer. Timing information is determined by examining the input data stream and the output data stream. A synchronization adjustment is applied to the input buffer and the output buffer in accordance with the timing information. Pixels are output from the input buffer and the output buffer to produce a synchronized mixed video output stream.

Abstract: Described systems and methods allow a reduction in the memory bandwidth required in video coding (decoding/encoding) applications. According to a first aspect, the data assigned to each memory word is chosen to correspond to a 2D subarray of a larger array such as a macroblock. An array memory word organization allows reducing both the average and worst-case bandwidth required to retrieve predictions from memory in video coding applications, particularly for memory word sizes (memory bus widths) larger than the size of typical predictions. According to a second aspect, two or more 2D subarrays such as video predictions are retrieved from memory simultaneously as part of a larger 2D array, if retrieving the larger array requires fewer clock cycles than retrieving the subarrays individually. Allowing the combination of multiple predictions in one memory access operation can lead to a reduction in the average bandwidth required to retrieve predictions from memory.

Abstract: The described embodiments provide a system that renders graphics for a computer system. During operation, the system loads a software client and a software service in the computing system. Next, the system receives a set of rendering commands from the software client in a command buffer, wherein the rendering commands include at least one of a state change command, a resource allocation command, a direct memory access (DMA) command, buffer data, and a synchronization command. Finally, the system uses the software service to render an image corresponding to the rendering commands by reading the rendering commands from the command buffer and executing the rendering commands.

Abstract: Technologies are described herein for buffer management during real-time streaming. A video frame buffer stores video frames generated by a real-time streaming video capture device. New video frames received from the video capture device are stored in the video frame buffer prior to processing by a video processing pipeline that processes frames stored in the video frame buffer. A buffer manager determines whether a new video frame has been received from the video capture device and stored in the video frame buffer. When the buffer manager determines that a new video frame has arrived at the video frame buffer, it then determines whether the video processing pipeline has an unprocessed video frame. If the video processing pipeline has an unprocessed video frame, the buffer manager discards the new video frame stored in the video frame buffer or performs other processing on the new video frame.

Abstract: Provided are methods and systems for video data processing. In an exemplary system, there is a video source and a display unit. The display unit may receive video data from the video source and display it at a first refresh rate. The video source may cause the display unit to enter a power economy mode, in which the displayed video is static. In this mode, the video source stops sending new video data, while the display unit selectively stores one or more of the previously received video frames and further displays it repeatedly at a second refresh rate, which may be lower than the first refresh rate (e.g., it may be decreased from 60 Hz to 40 Hz). In the power economy mode, the power consumed may be decreased by about 10-20% for both the video source and the display unit in some embodiments.

Abstract: A system and method of capturing, storing, editing and outputting multi-track motion data in a continuous stream on a computer with deterministic timing, where the length of the motion dataset is not limited by computer Random Access Memory. A hard real time periodic motion task takes in data streams from sensors or other computers, stores it in a shared memory area, and streams out the data to other computers so as to actuate motion. A shared memory area stores buffers and flags which indicate what data should be swapped to and from persistent storage. A soft real time periodic task transfers data pages between RAM and persistent storage based on requests from the motion task. Three data pages surround the active point in the motion dataset, four pages are reserved for copying whole blocks of data, and three pages are reserved for data editing. These ten active memory pages define a fixed memory footprint which can handle a deterministic data stream of effectively infinite length.

Abstract: This disclosure provides systems, methods and apparatus, including computer programs encoded on computer storage media, for improving the visual appearance of displayed images at high frame rates by skipping writing lines of display data. In one aspect, clusters of changed image regions are detected, and lines are preferentially written when such clusters are detected.

Abstract: Systems and methods for transitioning from buffering video to recording video. The control application receives a video and causes the video to be buffered until it detects a buffer full condition. Upon receiving the buffer full condition, the control application causes the media recorder to begin recording the newly received video as a recording, and designates the buffered video as part of the recording. In one method, the control application can be set to either record or play when the buffer becomes full. In other methods, the control application prompts the user for input indicating whether the video should be recorded or played when the buffer becomes full. In still other methods, the control application alerts the user as to how long a program may be paused before the buffer will become full.

Abstract: When multi-frame rate contents including many high frame-rate portions are played back in a video player, a playback can be easily selected by showing to a user a playback time in respective playback modes of a normal playback and a slow playback. The video player includes a rate analysis unit for calculating playback time in the respective playback modes by analyzing a frame rate of multi-frame rate contents, and thumbnail images of multi-frame rate contents and playback time in the respective playback modes are listed and displayed as display units in a pair with respect to a plurality of contents.

Abstract: A method for processing digital image data is provided that includes compressing a block of the digital image data to generate a compressed block, storing the compressed block in an external memory when a number of bits in the compressed block does not exceed a first compression threshold, and storing the block in the external memory when the number of bits in the compressed block exceeds the first compression threshold.

Abstract: A video card includes a mapping module to map data of the video card from a first video memory into a second video memory. The video card further includes a detection module to detect whether there is a non-working bit in the first video memory or in the second video memory. If there is the non-working bit, a position of the non-working bit is determined. When the non-working bit in the first video memory is accessed, the video card switches to a bit in the second video memory corresponding to the non-working bit. When the non-working bit in the second video memory is accessed, the video card switches to a bit in the first video memory corresponding to the non-working bit.

Abstract: The video stabilization method can generate output data for an output frame from input data of an input frame according to a perspective transform of a transform matrix. The input data used for the perspective transform can be obtained from a buffer of a predetermined depth. The transform matrix can be altered when the input data required for the transform exceeds the depth of the buffer.

Abstract: An apparatus comprising a plurality of memory modules and a plurality of memory controllers. The plurality of memory modules may be configured to store video data in a half-macroblock organization. Each of the plurality of memory controllers is generally associated with one of the memory modules. The memory controllers are generally configured to index a fetch of pixel data for an unaligned macroblock from the plurality of memory modules.

Abstract: A memory address mapping method of controlling storage of images in a memory device is provided. The memory device includes banks each having a plurality of pages. The memory address mapping method includes: receiving a first image; and referring to an image partition setting to generate a first memory address setting for each horizontal line partition in the first image, wherein the image partition setting defines that one image is divided into horizontal line groups each having at least one horizontal line, and each of the horizontal line groups is divided into horizontal line partitions in a horizontal line direction. First memory address settings of the horizontal line partitions in each horizontal line group of the first image control that a corresponding horizontal line group having the horizontal line partitions included therein is not stored into a same bank of the memory device.

Abstract: An apparatus having a first memory and a circuit is disclosed. The first memory may be configured to store a list having a plurality of read requests. The read requests generally (i) correspond to a plurality of blocks of a reference picture and (ii) are used to decode a current picture in a bitstream carrying video. The circuit may be configured to (i) rearrange the read requests in the list based on at least one of (a) a size of a buffer in a second memory and (b) a width of a data bus of the second memory and (ii) copy a portion of the reference picture from the second memory to a third memory using one or more direct memory access transfers in response to the list.

Abstract: The invention is directed to a method of storing videos for a portable device having a buffer memory space and a storage device The method comprises recording a plurality of video frames and storing the video frames into the buffer memory space of the portable device and detecting an event. According to the event, a portion of the video frames recorded from a first predetermined time before the event is detected until the event is detected is restored into the storage device as a plurality of pre-event video frames and, meanwhile, a plurality of post-event video frames is continuously recorded for a second predetermined time after the event is detected and the post-event video frames are stored into the storage device, wherein the storage device is coupled to the portable device.

Abstract: Embodiments of the present invention are directed to memory subsystems implemented within, or connected to and accessed by, parallel, pipelined, integrated-circuit implementations of computational engines designed to solve complex computational problems. Additional embodiments of the present invention are directed to memory subsystems implemented within, or connected to and accessed by, a variety of different types of electronic devices. One embodiment of the present invention comprises a memory controller implemented in a first integrated circuit or other electronic system and one or more separate memory devices. Alternative embodiments of the present invention incorporate the memory controller within one or more memory devices that are connected to, and accessed by, an integrated-circuit-implemented computational engine or another electronic device.

Abstract: A video card includes a memory which has a plurality of memory bank. The video further includes a check unit which is used to check whether there is a malfunctioning bit in a memory bank. If there is at least one malfunctioning bit, a malfunctioning memory bank that contains the malfunctioning bit is determined. When the video card is written to or read from, the malfunctioning memory bank is not written to or read from according a bank address and an offset address of the malfunctioning memory bank and data is written to or read from other memory bank that are functioning.