Abstract: A technique for encoding and decoding video information uses a plurality of video processing modules (VPMs), whereby each video processing module is dedicated to a particular video processing function, such as filtering, matrix arithmetic operations, and the like. Information is transferred between the video processing modules using a set of first-in first-out (FIFO) buffers. For example, to transfer pixel information from a first VPM to a second VPM, the first VPM stores the pixel information at the head of a FIFO buffer, while the second VPM retrieves information from the tail of the FIFO buffer. The FIFO buffer thus permits transfer of information between the VPMs without storage of the information to a cache or other techniques that can reduce video processing speed.

Abstract: A display apparatus and a method for displaying an image are provided. The display apparatus includes a memory which stores one or more images; a communication unit which receives a universal serial bus (USB) video signal transmitted via a USB cable from an external apparatus, and receives a specific command signal from the external apparatus if the external apparatus starts to boot; and a main controller which determines that the external apparatus is being booted and causes the stored images to be displayed on a screen if the command signal is received through the communication unit.

Abstract: A computer system that initializes a fraction of the computer system's memory for execution of video during booting of the computer system is provided. The computer system can include a first portion of BIOS code on a ROM device, wherein the first portion includes instructions for initializing the fraction. The computer system further can include a second portion of BIOS code that copies itself to the fraction upon completion of initialization of the fraction, wherein the second portion executes on the fraction and wherein the second portion initializes system memory and initializes a video buffer. The computer system further can include a copy of the second portion located on the ROM device, wherein the copy of the second portion executes until video buffer initialization is completed but before all of the system memory is initialized. Further, the video buffer displays video before all of the computer system's memory is initialized.

Abstract: A method for performing video display control within a video display system includes: dynamically utilizing two of a plurality of buffers as on-screen buffers for three-dimensional (3D) frames, wherein the plurality of buffers is positioned within the video display system; and during utilizing any of the two of the plurality of buffers as an on-screen buffer, dynamically utilizing at least one other buffer of the plurality of buffers as at least one off-screen buffer for at least one 3D frame. An associated video processing circuit and an associated video display system are also provided. In particular, the video processing circuit is positioned within the video display system, where the video processing circuit operates according to the method.

Abstract: Video display pipes may terminate with a FIFO (first-in first-out) buffer from which pixels are provided to a display controller to display the pixels on a graphics/video display. The display pipes may frequently process the pixels at a much higher rate than at which the display controller fetches the pixels from the FIFO buffer. In an error-checking only mode, the FIFO may be disabled, and an error-checking (e.g. CRC) block connected in front of the FIFO may receive the pixels processed by the display pipes as fast as the display pipes are capable of processing the pixels. Accordingly, the length of test/simulation time required to perform a test may be determined by the rate at which pixels are generated rather than the rate at which the display controller displays the pixels. It also becomes possible to perform testing/simulation in environments where a display is not supported or is not available.

Abstract: The video output system in a computer system reads pixel information from a frame buffer to generate a video output signal. In addition, a full-motion video may also be displayed. Reading from both the frame buffer and the full-motion video buffer when displaying the full-motion video window wastes valuable memory bandwidth. Thus, the disclosed system provides a system and methods for identifying where the video output system must read from the frame buffer and where it must read from the full-motion video buffer while minimizing the amount of area it reads from both the frame buffer and the full-motion video buffer.

Abstract: Described systems and methods allow a reduction in the memory bandwidth required in video coding (decoding/encoding) applications. According to a first aspect, the data assigned to each memory word is chosen to correspond to a 2D subarray of a larger array such as a macroblock. An array memory word organization allows reducing both the average and worst-case bandwidth required to retrieve predictions from memory in video coding applications, particularly for memory word sizes (memory bus widths) larger than the size of typical predictions. According to a second aspect, two or more 2D subarrays such as video predictions are retrieved from memory simultaneously as part of a larger 2D array, if retrieving the larger array requires fewer clock cycles than retrieving the subarrays individually. Allowing the combination of multiple predictions in one memory access operation can lead to a reduction in the average bandwidth required to retrieve predictions from memory.

Abstract: The present invention includes a method and device that allows efficient mixing of multiple video images with a graphics screen while utilizing only one video buffer. The present invention partitions the sole video buffer, pre-scales the plurality of video images and inserts them into the partitioned video buffer in a predetermined range of buffer addresses. The present invention mixes the partitioned video including the pre-scaled video images with the graphics screen to produce a video display including both a video screen and a graphics screen.

Abstract: Modification to frame buffer memory information associated with a first display may be used to update information displayed on a second display. The first display may be mapped to a matrix of display areas. The modification to the frame buffer memory information may be detected be detecting write memory address. One or more display areas affected by the modification to the frame buffer memory information may be identified based on display parameters associated with the first display. Frame buffer memory information associated with the one or more affected display areas may be retrieved and compressed before being transmitted over a communication link to be displayed on the second display.

Abstract: One embodiment of the present invention sets forth a system for generating multiple video output signals from a single video pipeline within a graphics processing unit. Pixel data from more than one display surface is retrieved and multiplexed before being transmitted to a video pipeline for processing. The resulting video pixel data is routed to video output encoders, which selectively accept the video pixel data for transmission to attached display devices.

Abstract: Methods and systems for mosaic mode display of video are disclosed. Aspects of one method may include generating video data for a plurality of video windows using a single video feeder module comprising a single video scaler and a single video capture module. The video data for the video windows may be generated in a single frame time. Register DMA may be used to transfer register update data (RUD) to a plurality of registers to configure video processing for generating video data for a video window. The plurality of RUDs may be generated in response to a single interrupt to a processor, and may be configured as a linked list or stored sequentially in memory. The configuring may occur prior to generating video data for the corresponding video window. Video processing for a subsequent video window may be configured automatically after generating video data for the present video window.

Abstract: In a mobile device with a mobile device video driver that can be interdicted, such as a display telephone or PDA, a method and system for display on a remote video display device is provided involving forming an enhanced display image in an enhanced video frame buffer and reconstructing the display image in a duplicate enhanced video frame buffer in the remote video display device.

Abstract: Display data and video data are stored within a graphics processing unit to reduce power consumed by the computing device during video playback. Storing display data and video data within the GPU reduces power consumption, because bus transaction activity is reduced and the need to read data from a larger, common main memory is avoided.

Abstract: A moving-picture processing apparatus has a pre-fetch memory pre-fetching a portion of a decoded picture stored in an external memory, and a miss/hit determination unit determining a manner in which a miss occurs in response to a read request to the pre-fetch memory.

Abstract: According to one embodiment, a graphics processing unit detects characteristics of video data by analyzing frames of the video data by using at least one first processing core of a plurality of processing cores, and applies a process, which is associated with the detected characteristics of the video data, to audio data on a memory, by using at least one second processing core of the plurality of processing cores. The graphics processing unit includes an audio signal output interface and outputs an audio signal corresponding to the audio data, to which the process has been applied, to a sound device.

Abstract: An information processing device to generate data pertaining to a document from electronic paper which has a display section to display and retain the document, and a memory to store document identification data, includes a document data storage unit which stores document electronic data, a communication unit which acquires document identification data from the electronic paper, a reading unit which scans the display section, a data extraction unit which extracts from the document data storage unit document electronic data corresponding to the document identification data, a difference processing unit which extracts a note image appended on a surface of the display section according to a difference between an image from the extracted document electronic data and an image of the scanned display section, and a data generation unit which associates data of the extracted appendix image and the extracted document electronic data, thereby generates data pertaining to the document.

Abstract: Systems and methods for compressing data within a block of data for storage in memory and for transmission along a data path are described herein. By utilizing previously unused bits in data words, the valid data can be stored more efficiently and transmitted in fewer transfer cycles, thereby increasing the availability of the data bus to other masters. One embodiment of a system for storing and transmitting compressed data includes masters and slaves interconnected by a data bus. One of the masters is a video input interface configured to receive video data from an external video source. The video input interface is further configured to compress the video data using a compression algorithm based on the difference in color between two adjacent pixels. Another one of the masters is a video display controller configured to receive the compressed video data.

Abstract: A sink device having a display panel capable of performing a video frame self-refresh as directed by a source device is described. A source determines that a video frame will persist (i.e., remain the same). In this situation, the frame data does not need to be repeatedly transmitted over a main link between the source and sink devices. The main link can be turned off and transmission can cease for a certain time thereby reducing power usage by the devices or system as a whole. The source ensures that the last frame transmitted to the sink is correct by performing CRC checks and then instructs the sink, via certain bit settings in a video status indication symbol, to store the last transmitted frame in the sink's local buffer and use that frame to refresh the panel. The source can then disable the self-refresh when the frame changes.

Abstract: A method for displaying images asynchronously is provided. The method includes: providing at least one display mode, the display mode defines a total display area count displayable showed on a display, an interval to display images on the display, and a predetermined displaying manner; obtaining images and the display mode; generating one or more display areas according to the display mode; and displaying the images on the generated display areas according to the interval and displaying manner.

Abstract: A display system that achieves a gamma characteristic different than 1, such as a gamma characteristic of 2 for example. The gamma characteristic may be selectable and it may be selectable via timing characteristics rather than by varying the intensity of the light source. Defective memory registers are also compensated for by selecting them to store bits of relatively lower significance.

Abstract: An electronic system, an integrated circuit and a method for display are disclosed. The electronic system contains a first device, a memory and a video/audio compression/decompression device such as a decoder/encoder. The electronic system is configured to allow the first device and the video/audio compression/decompression device to share the memory. The electronic system may be included in a computer in which case the memory is a main memory. Memory access is accomplished by one or more memory interfaces, direct coupling of the memory to a bus, or direct coupling of the first device and decoder/encoder to a bus. An arbiter selectively provides access for the first device and/or the decoder/encoder to the memory based on priority. The arbiter may be monolithically integrated into a memory interface. The decoder may be a video decoder configured to comply with the MPEG-2 standard. The memory may store predicted images obtained from a preceding image.

Abstract: There is provided an image processing device for controlling a display device to display a plurality of unit images making up a moving image at predetermined intervals, the image processing device including: 4×N (N: an arbitrary integer) quadrant memories; a separation section; a memory output control section; an assignment section; and an output control section.

Abstract: A table-based driving circuit for displays that switches between a normal operational mode and a read table block mode. The driving circuit comprises an address sequencer and a memory. The memory comprises the full table of individual sequences, such as interlacing or color-sequential sequence. In the read table mode, the next upcoming addresses are read, i.e. are downloaded, from the memory into an address table register in the address sequencer. In the normal operational mode, the address sequencer generates the addresses for the video data to be stored in the memory or to be displayed.

Abstract: A method for identifying motion video/audio content, by means of comparing a video A to a registered video B so as to determine if they are originally the same as each other, wherein said method at least comprises the steps of extracting a fingerprint A from the video A; and searching from a fingerprint database for a pre-extracted and registered fingerprint B of the video B by means of comparison of fingerprint A with a sliding window of a possible fingerprint B, so as to determine that the video A is visually identical to the video B if a match is found. According to the present invention, the method for extracting a fingerprint data from video/audio signals facilitates the automatic identification, archiving and search of video content, and can be of without the need for human visual inspections.

Abstract: This invention provides an image processing apparatus and an image processing method. By calculation of the pixel difference that is the difference of each corresponding pixels between the current image and the previous image with its neighbor pixel difference, this invention can determine the blending value.

Abstract: A method for deriving three-dimensional information progressively from a streaming video sequence.

Abstract: A graphics system including a custom graphics and audio processor produces exciting 2D and 3D graphics and surround sound. The system includes a graphics and audio processor including a 3D graphics pipeline and an audio digital signal processor. The graphics system has a graphics processor includes an embedded frame buffer for storing frame data prior to sending the frame data to an external location, such as main memory. The embedded frame buffer is selectively configurable to store the following pixel formats: point sampled RGB color and depth, super-sampled RGB color and depth, and YUV (luma/chroma). Graphics commands are provided which enable the programmer to configure the embedded frame buffer for any of the pixel formats on a frame-by-frame basis.

Abstract: A method and apparatus is provided in which a digital image is transmitted to a presentation projector resource over a wireless transmission medium using a reduced amount of transmission bandwidth by transmitting a subset of the digital image data. The subset image data may be a delta subset that represents those areas of the image that have changed since the previous transmission. The subset image data may also be a scalable vector graphics representation of the subset of the digital image. Header data is provided to further describe the subset image data. A projector discovery logic selects a suitable projector resource based on the order or signal strength of the discovery replies. A wireless image transmission session is established with the selected projector resource during which the projector is unavailable to other devices. The subset image data may be compressed and transmission coordinated with the projector resource so that the data is sent only when it is ready to be received.

Abstract: A memory access method intended for a memory required to provide an interval of a predetermined number of clock cycles or longer between successive occurrences of access when the same bank is successively accessed, and that eliminates an idle time between successive occurrences of access to allow for improved performance. Pieces of data are written into 0th, the first, the second, and the third banks, respectively. No idle time is caused between successive occurrences of access because different banks are successively accessed. Since a burst length of each of the pieces of data is eight, an interval of 16 cycles which is longer than 15 cycles is provided between a start of writing of first data and a start of second writing of data. Accordingly, no idle time is caused also between completion of writing of the first data and start of writing of the second data.

Abstract: Techniques are described that can used to synchronize the start of frames from multiple sources so that when a display is to output a frame to a next source, boundaries of current and next source are aligned. Techniques attempt to avoid visible glitches when switching from displaying a frame from a first source to displaying frames from a second source even though alignment is achieved by switching if frames that are to be displayed from the second source are similar to those displayed from the first source.

Abstract: An integrated circuit is a baseboard management controller that is a fully integrated system-on-a-chip microprocessor incorporating function blocks and interfaces that provide remote management solution. The integrated circuit uses a microprocessor, a media co-processor to accelerate video processing, and a set of system and peripheral functions that are useful in a variety of remote management applications. It further includes an integrated USB high-speed device and an OTG interface to support keyboard, mouse and mass storage emulation without additional external components, and two integrated MII LAN interfaces and one FSB interface, a memory controller to support a variety of static and dynamic memory components, an encryption controller to ensure secure remote management sessions and IPMI2.0-compliant BMC interfaces. The integrated circuit is based on structured ASIC technology, which enables easy customization of function blocks according to customer demands or new industry standards.

Abstract: Systems and methods are provided for variable source rate sampling in connection with image rendering, which accumulate and resolve over all samples forward mapped to each pixel bin. In accordance with the invention, the textured surface to be rendered is sampled, or oversampled, at a variable rate that reflects variations in frequency among different regions, taking into account any transformation that will be applied to the surface prior to rendering and the view parameters of the display device, thus ensuring that each bin of the rendering process receives at least a predetermined minimum number of samples. A variety of image processing applications are contemplated wherein variable rate source sampling, and accumulation and resolution of forward mapped point samples can be applied, ranging from 3-D graphics applications to applications wherein images recorded in a recording/storage environment are mapped to the arbitrary requirements of a display environment.

Abstract: An imaging and display apparatus for passive displays evaluates the illumination of an input scene and incorporates data representative of such input scene within a transfer media. The transfer media may be a broadcast or transmission of image data, illumination data and gamma information that can be received by a display system, which includes a passive display illuminated by incident light, to display images while adjusting the incident light and/or gamma based on the received data. The transfer media may be a storage medium storing image data, illumination data and gamma information for delivery to a passive display system. The data controls the optical characteristics of the illumination source for the passive display and the gamma and tends to minimize energy requirements, to maximize contrast or shades of gray in the displayed image, and to optimize light source operation for color fidelity.

Abstract: Screen recording may be implemented with better security, performance, power savings and cost without the need of additional software to support the screen recording feature, in some embodiments, by using a keyboard, video, mouse functionality already provided in a computer system chipset on a motherboard. Frames of video may be stored on that system or, in some cases, may be selectively provided to a local area network.

Abstract: A system, method, and computer program product are provided for calculating statistics associated with a surface to be rendered utilizing a graphics processor. In use, w-values are identified using a graphics processor. Additionally, the graphics processor is utilized for calculating statistics associated with at least one surface to be rendered using the w-values. Furthermore, the statistics are stored.

Abstract: An object is to realize downsizing and cost reduction of a display device by efficiently using a physical region of a memory in a control circuit of the display device. A structure of a video data storage portion of the control circuit is that provided with a video data storage portion for storing video data of an n-th frame (n is a natural number), a video data storage portion for storing video data of an (n+1)th frame, and a video data storage portion for sharing video data of the n-th frame and the (n+1)th frame among received video data.

Abstract: Graphics display adapters for driving multiple display monitors have become very popular. Graphics display adapters that drive multiple monitors can be used to provide terminal services to multiple independent terminals or be used to provide multiple displays to a single user. Generating video signals for multiple display systems puts a heavy burden on the video memory system since multiple different video signal generators may read from associated frame buffers in a shared video memory system. In one disclosed embodiment, a plurality of video memory read triggers are provided wherein at least two of which are staggered to reduce the load on the video memory system. In response to each read trigger, display data is read from a frame buffer to an associated video signal generation circuit. Each video signal generation circuit then provides a display signal to an associated display screen in a multi-screen environment.

Abstract: A programmable system for dithering video data. The system is operable in at least two user-selectable modes which can include a small kernel mode and a large kernel mode. In some embodiments, the system is operable in at least one mode in which it applies two or more kernels (each from a different kernel sequence) to each block of video words. Each kernel sequence repeats after a programmable number of the blocks (e.g., a programmable number of frames containing the blocks) have been dithered. The period of repetition is preferably programmable independently for each kernel sequence. The system preferably includes a frame counter for each kernel sequence. Each counter generates an interrupt when the number of frames of data dithered by kernels of the sequence has reached a predetermined value. In response to the interrupt, software can change the kernel sequence being applied. Typically, the system performs both truncation and dithering on words of video data.

Abstract: An electronic system, an integrated circuit and a method for display are disclosed. The electronic system contains a first device, a memory and a video/audio compression/decompression device such as a decoder/encoder. The electronic system is configured to allow the first device and the video/audio compression/decompression device to share the memory. The electronic system may be included in a computer in which case the memory is a main memory. Memory access is accomplished by one or more memory interfaces, direct coupling of the memory to a bus, or direct coupling of the first device and decoder/encoder to a bus. An arbiter selectively provides access for the first device and/or the decoder/encoder to the memory based on priority. The arbiter may be monolithically integrated into a memory interface. The decoder may be a video decoder configured to comply with the MPEG-2 standard. The memory may store predicted images obtained from a preceding image.

Abstract: A system and method for converting a pixel rate of a digital image frame is provided. The system includes a display controller with an embedded buffer and programmable input and output buffers. The input buffer writes lines of the frame at a source pixel rate while the output pointer reads out lines of the frame at a display pixel rate thereby allowing display of an image having a source pixel rate that is different, e.g., higher, than a display pixel rate.

Abstract: A system with a main monitor for a host computer and a second, mini monitor for displaying a portion of the display normally intended for the main monitor. In one embodiment, the mini monitor is connected to the computer over a shared, peripheral bus, such as the universal serial bus (USB). The smaller size of the mini monitor and either compression or slower refresh rates allow it to be connected to the USB just like other peripheral devices.

Abstract: Display data and video data are stored within a graphics processing unit to reduce power consumed by the computing device during video playback. Storing display data and video data within the GPU reduces power consumption, because bus transaction activity is reduced and the need to read data from a larger, common main memory is avoided.

Abstract: A method for decreasing end-to-end delay in a video conferencing context is disclosed. At video conferencing system startup, a processor is initialized to receive either a top field or a bottom field of video frame data. If the first line of a new field arriving after initialization does not match a field state that the processor is initialized to, the present invention senses the state mismatch and adjusts a display buffer by one display line, and the field is stored in the display buffer. The display buffer is adjusted in order to preserve a vertical spatial relationship between the top and bottom fields.

Abstract: According to one embodiment, an information processing apparatus comprises video memories each corresponding to each of the display devices, a determination module configured to determine whether an access that satisfies conditions preset with respect to display of the display devices exists in at least one of the video memories, and a changing module configured to change, when the determination module determines that the access that satisfies conditions preset with respect to display of the display devices does not exist in at least one of the video memories, an operation state of a display device corresponding to the at least one of the video memories determined that an access does not exist, from a first operation state to a second operation state having a power consumption lower than a power consumption of the first operation state.

Abstract: An apparatus comprising a memory and a coder/decoder circuit. The memory may have a first memory portion and a second memory portion. The coder/decoder circuit may be configured to (i) position a set of atoms across the memory, (ii) define a strip across a portion of the atoms, (iii) designate a first atom within the strip, (iv) locate one or more second atoms to be paired with the first atom, (v) determine whether the one or more second atoms when paired with the first atom forms a legitimate pair, and (vi) read the legitimate pair from the first memory portion and the second memory portion.

Abstract: A window surface associated with a first application is automatically detected as an exclusive window surface for a display. In response, the system automatically transitions to a full-screen mode in which a graphics processor flushes content to the display. The full-screen mode includes flipping between a front surface buffer and a back surface buffer associated with the first application. It is subsequently detected that the window surface associated with the first application is not an exclusive window surface for the display. In response, the system automatically transitions to a windowed mode in which the graphics processor flushes content to the display. In windowed mode, the system frame buffer is flushed to the display. The transition to windowed mode includes a minimum number of buffer content copy operations between the front surface buffer, the back surface buffer and the system frame buffer.

Abstract: A frame synchronization method includes: temporarily storing input data of at least one source frame in a frame buffer according to an input time sequence; generating an output time sequence according to the input time sequence and a delay time; generating output data of a destination frame according to the input data of the source frame; and outputting the output data of the destination frame according to an output time sequence; wherein an average frame rate of the source frame is substantially the same as that of the destination frame.

Abstract: Methods and apparatus for storing and retrieving data using two-dimensional arrays. In one implementation, a checkerboard buffer page system includes: a data source, providing data elements in a first order; a data destination, receiving data elements in a second order; memory devices having memory pages, data elements stored and retrieved in parallel to and from the memory devices; each buffer page having entries along a first dimension corresponding to the first order and along a second dimension corresponding to the second order, data elements stored in the first order and retrieved in the second order, at least one memory page stores data elements in multiple locations according to the first and second orders, at least two data elements consecutive in the first order are stored in parallel to the memory devices, and where at least two data elements consecutive in the second order are retrieved in parallel from the memories.

Abstract: According to some embodiments, systems, methods, apparatus, computer program code and means are provided to set a first depth value associated with a plurality of pixels of a video image comprising a plurality of planes, create a first clear rectangle with respect to the first depth value, color render the pixels that are not associated with the first clear rectangle, and render the plurality of planes.

Abstract: A system, method and computer program product are provided for retrieving instructions from memory utilizing a texture module in a graphics pipeline. During use, an instruction request is sent to memory utilizing a texture module in a graphics pipeline. In response thereto, instructions are received from the memory in response to the instruction request utilizing the texture module in the graphics pipeline.