Abstract: Remote desktop servers include a display encoder that maintains a secondary framebuffer that contains display data to be encoded and transmitted to a remote client display and a list of display primitives effectuating updated display data in the secondary framebuffer. The display encoder submits requests to receive the list of drawing primitives to a video adapter driver that receives and tracks drawing primitives that, when executed, update a primary framebuffer.

Abstract: A system and method for storing a multidimensional array of data, such as a two dimensional (2-D) array of video data, in a non-contiguous memory space. The system and method maps individually indexed elements of a multidimensional array of data from a source device into blocks of non-contiguous memory available in a destination memory system, even when the destination blocks are small and/or their size does not correlate in any way to the dimensions of a source buffer. In particular, the blocks of non-contiguous memory may be as small as a single element of the data indexed in the 2-D array.

Abstract: Activating a screen capture tool in a display adapter to capture information on a display. An operating system sends a command to the display adapter to initiate the capture of information from the graphical user interface of a display. The display adapter captures the information on the graphical user interface of the display. The information may be stored by the display adapter to a storage device that may be connected to the display adapter. The display is monitored for additional changes. Any changes that occur to the information on areas of the display may be captured and stored to the storage device. The operating system may enable the display adapter to retrieve the information stored in the storage device and/or play back the information retrieved to the display.

Abstract: A remote management controller may include a capture engine and a processor. The capture engine may be configured to obtain a slice of video data output from a video graphics controller, store the slice of video data, and calculate at least one value correlative to the slice of video data. The processor may be configured to retrieve the slice of video data stored by the capture engine and process any changed portion of the slice of video data for transmission to a remote system.

Abstract: In one embodiment, the present invention is a t-commerce platform, which is linked to the content from a video signal that the user is currently watching. At some point during the broadcast of the content, a close-up of the product is shown. Simultaneous with this, a VBI-based trigger is added to the video signal of the broadcast. This trigger causes the television, a set-top box, or a similar device to capture in a memory, a “freeze-frame” of the image being shown. This action is transparent to the user while the video being displayed on the television is continuing normally. If the user chooses to perform an interactive “buy” transaction the saved image data is used as part of the interactive screen display.

Abstract: Circuits, methods, and apparatus that pre-load data that may be needed by a graphics processor to render upcoming scenes. One example determines one or more possible upcoming scenes or views. To save computing resources, the possible upcoming scenes are not fully rendered, but the addresses, and corresponding pages, of data that would be needed to render the scenes are determined. Page usage information is also gathered. Pages that would be needed to render the upcoming scenes, but which are not resident in memory, are read in from a disk drive and stored in memory before they are needed. Pages that are infrequently used are removed from physical memory. In this way, when the scene changes, a large number of page faults do not occur in one frame, rather, they are distributed among several frames.

Abstract: A cache control unit of a video data playback control apparatus sets priority video data in order to efficiently use a storage area of a cache memory. The priority video data includes video data which includes a greater number of portions of video data than that of data displayed in a display unit, which includes a smaller number of portions of video data than a maximum number that can be held in the cache memory, and which has a high possibility of being output from the cache memory to the display unit. Also, the cache control unit preferentially reads the priority video data from a recording medium and stores it in the cache memory.

Abstract: In a video processor unit, a method of providing a video data stream at a clock rate that is independent of a pixel clock rate. Receiving native video data from a video source at a native clock rate, storing the video data in a memory unit, reading selected portions of the video data at a memory clock rate, rasterizing the selected video data, packetizing the rasterized video data, sending the packetized video data to a display unit by way of a link at a link rate, wherein the link rate is directly related to the memory clock rate.

Abstract: An image signal processing apparatus which is capable of preventing the “simultaneous display of an original image and the immediately preceding image” as well as dropping of frames. A signal processor subjects an image pickup signal corresponding to a subject outputted from an image pickup device to signal processing. A VRAM (Video Random Access Memory) section is composed of at least three storage areas that store image signals outputted from the signal processing circuit. A VRAM management information section stores management information indicative of storage states of the respective storage areas of the VRAM section. A compression circuit subjects an image signal read from the VRAM section to compression processing. An image display processing circuit subjects an image signal read from the VRAM section to image display processing. An image display section displays images based on the image signal outputted from the image display processing circuit.

Abstract: A method and apparatus for digitizing and compressing video signals for transmitting the signals between a remotely located computer and a host or local computer. The digitization and compression method and apparatus is capable of dividing frame buffers into cells and comparing image data from previously captured frame buffers to create synchronized video signals and transmit the video signals over an extended range by limiting the portions of the transmission bandwidth of pixel data transferred between the remote computer and the local computer. In an alternate embodiment of the present invention, a keyboard video mouse switch is disposed between the remotely located computer and the local computer.

Abstract: Included are systems and methods for reducing power consumption in a computer system. At least one embodiment of a method, among others, includes processing data in a normal mode, receiving an indication of a transition into an idle mode, capturing at least one frame of display data, and transmitting the captured frame of display data for display during idle mode.

Abstract: An electronic system, an integrated circuit and a method for display are disclosed. The electronic system contains a first device, a memory and a video/audio compression/decompression device such as a decoder/encoder. The electronic system is configured to allow the first device and the video/audio compression/decompression device to share the memory. The electronic system may be included in a computer in which case the memory is a main memory. Memory access is accomplished by one or more memory interfaces, direct coupling of the memory to a bus, or direct coupling of the first device and decoder/encoder to a bus. An arbiter selectively provides access for the first device and/or the decoder/encoder to the memory based on priority. The arbiter may be monolithically integrated into a memory interface. The decoder may be a video decoder configured to comply with the MPEG-2 standard. The memory may store predicted images obtained from a preceding image.

Abstract: Methods and apparatus for switching the voltages supplied to the electrodes of pixels disposed within a liquid crystal display device. By reducing the frequency associated with an alternating voltage supplied to a first set of liquid crystal electrodes, the power required to drive the liquid crystal display device can be reduced. At the same time, a reordered schedule for updating rows of pixels in the liquid crystal display device can provide improved image quality.

Abstract: Virtualization of graphics resources and thread blocking is disclosed. In one exemplary embodiment, a system and method of a kernel in an operating system including generating a data structure having an identifier of a graphics resource assigned to a physical memory location in video memory, and blocking access to the physical memory location if a data within the physical memory location is in transition between video memory and system memory wherein a client application accesses memory in the system memory directly and accesses memory in the video memory through a virtual memory map.

Abstract: An over driving method for a display is disclosed. The steps of the method mentioned above includes the following. A power saving parameter is set equal to an initial value, a current frame data is received, and a previous frame data is read from a memory. Afterward, the power saving parameter is updated by comparing the current frame data and the previous frame data. Moreover, an over driving process is executed to the display according to the comparison result for the power saving parameter and a reference value.

Abstract: A three-dimensional graphics data rendering method. The method divides initially inputted first graphics data into a static object and a dynamic object, performs a rendering process with respect to the static object, and updates a predetermined buffer with the rendering result. Then the method performs a transformation process, a portion of the rendering process with respect to the dynamic object, determines an updating area, and stores a rendering result of the buffer corresponding to the updating area in a predetermined storage unit; performs a remaining rendering process with respect to the dynamic object, updates the buffer and outputs a first image whose rendering is completed. Finally, the method restores a rendering result of the updating area to the buffer by referring to the storage unit and utilizes a rendering result of the restored buffer as a rendering result of subsequently inputted second graphics data.

Abstract: For lower load in image encoding, the present invention causes the CPU core to function as the following sections: an editing execution section for an editing process, including shifting process, of an unprocessed image which may undergo previous editing process, under user's input; a shift amount calculation section for calculating the shift amount of the resultant edited image; a difference data calculation section for obtaining difference data between the processed image and an image obtained through shifting of the unprocessed image by the calculated shift amount; and an image addition section for storing, in the image storage section, the calculated shift amount, and the obtained difference data, so as to be associated with each other.

Abstract: A display module for displaying information on a screen, using a display data structure, wherein the display data structure is a doubly linked list. A display space in defined in video memory and the display space is filled by sequentially copying at least a portion of a set of characters from the display data structure into the video memory.

Abstract: A semiconductor device capable of displaying a still image with low consumption power is provided. In the semiconductor device incorporated with a semiconductor display device capable of displaying the still image, a memory portion is mounted on a substrate on which a pixel portion is formed. As a mounting method, the memory portion is formed on the substrate on which the pixel portion is formed or a stick driver including the memory portion is used. When the still image is displayed using image data stored in such a memory portion, the still image can be displayed by inputting only simple control signals from the outside of the semiconductor device. Thus, there are provided the semiconductor display device capable of displaying the still image with low consumption power and the semiconductor device incorporated with the semiconductor display device.

Abstract: A system and method for allocating video processing tasks over multiple video processors include an apparatus. The apparatus includes a plurality of video processors. Each video processor includes a first processor that processes video data and manages buffers used in conversion and displaying video data. The video processor includes a second processor that performs video data signal processing and manages buffers used in processing video data. The apparatus also includes a switch coupled to each video processor, as well as video inputs and video outputs. A third processor coupled to the switch, and a memory coupled to each video processor and to the third processor, are also part of the apparatus. The switch selectively couples a video processor to a video input or a video output, the third processor configures the switch based on processing requirements of each video stream, and the memory buffers and stores video data.

Abstract: A 3-dimensional computer generated image is generated by subdividing the image into a plurality of rectangular areas. Object data for each rectangular area is loaded into a display list memory until that memory is substantially full. Image data and shading data for each picture element of each rectangular area are derived by an image synthesis processor from the object data. The image data is then stored in a local memory. Additional object data is loaded into the display list memory and replaces existing contents. Then, the stored image data and the shading data are retrieved, and additional image data and shading data are derived for each picture element by the image synthesis processor using the additional object data and the previously derived image and shading data. When there is no further object data to load to the display list memory, the shading data is provided for display for the rectangular areas by a frame buffer.

Abstract: Multiple grayscale image data is displayed efficiently. Image data is stored in a frame memory, and a predetermined bit of the image data is also stored in a pixel memory having a memory for each pixel. Video data in the pixel memory and video data in the frame memory (22) are exchanged using an input/output unit, to control display of an image in a pixel.

Abstract: Graphics resources are virtualized through an interface between graphics hardware and graphics clients. The interface allocates the graphics resources across multiple graphics clients, processes commands for access to the graphics resources from the graphics clients, and resolves conflicts for the graphics resources among the clients.

Abstract: A video signal processing apparatus includes two image display memory areas 22 and 24 which alternately repeat input and output operations by receiving a signal obtained by performing predetermined processing for an output image signal from an image sensor 12, an image display unit 28 for displaying an object image represented by image frames sequentially output from the two memory areas, a system controller 40 which, when an image frame is to be input to one of the two memory areas, causes the other one of the two memory areas to output a held image frame, and causes the two memory areas to alternately repeat the input and output operations, thereby switching inputting and outputting of the two memory areas, and a mode determination circuit 272 for determining whether the frame rate of the output image signal from the image sensor 12 is higher or lower than the image display rate of the image display unit 28.

Abstract: A system, apparatus, method and article to perform buffering techniques are described. The apparatus may include a buffer having a fixed number of storage slots that store reconstructed picture representations received from an image processing module. Also, the apparatus may include a buffer status unit to store a multiple information items to indicate one or more buffer characteristics of the buffer. Further, the apparatus may include a buffer control module to manage storage within the buffer.

Abstract: Systems and methods for processing signals are disclosed. The method may include, in a communication device that includes a chip operating to processing video signals, receiving video data from a camera. The received video data may include alternating YUV formatted video data and RGB formatted video data. The received video data may be separated into separate YUV images and separate RGB images. The separate YUV images may be transferred to a first device, and the separate RGB images may be transferred to a second device. The camera may be configured to generate the video data that includes alternating YUV formatted video data and RGB formatted video data. The separate YUV images may be DMA transferred to the first device. A DMA controller may be configured to alternately transfer the separate YUV images and separate RGB images. The alternate transfer via the DMA controller may occur without assistance from on-chip processor.

Abstract: A screen driver is included with other drivers provided by a vendor with a computer system The screen driver is picked up by the OS along with the other drivers at the beginning of the installation of the OS. The screen driver remains dormant until the first time a user logs into the computer system. At that time, the driver executes and retrieves screen data along with a program that displays the screen. The program also maintains the displayed screen on top of any other screens that might be generated subsequent to completion of the first log-in to maintain visibility to the user until the user has an opportunity to act on the display screen.

Abstract: Aspects of the present invention relate to methods and systems for processing image data for use on LCD displays. Some aspects relate to an adaptive image compression techniques for liquid crystal display systems. Some aspects relate to systems and methods wherein varying degrees of compression are applied based on memory availability.

Abstract: A system including a server apparatus executes an application program and a client apparatus enabling a user to utilize the application program by communicating with the server apparatus based on an instruction of the user. The server apparatus includes: an output detection section for detecting output-processing which is processing of outputting data from the application program into a shared area; and an output control section for storing instruction information in the shares area, instead of storing the output data outputted from the application program therein, in response to the detection of the output-processing, the instruction information specifying an acquisition method by which an authorized client apparatus acquires the output data.

Abstract: A method of transferring image data to a composite memory space comprises including masking data defining a reserved output area in a first memory space and containing first time-varying data having a first frame rate associated therewith. Second time-varying image data is stored in a second memory space and is associated with a second frame rate. At least part of the first image data is transferred to the composite memory space and at least part of the second image data is transferred to the composite memory. The mask data is used to provide the at least part of the second image data such that, when output, the at least part of the second image data occupies the reserved output area.

Abstract: In a stereoscopic image generation device according to the invention, an obtaining means 11 obtains sequentially a plurality of original images Ga arranged in a time line and forming a content item. A calculation means 12 calculates an image characteristic value Ng from pixel values of a plurality of pixels included in an original image Ga obtained by the obtaining means 11. A storage device 21 stores a project file Fp by which image characteristic values Nf for the original images Ga forming the content item are respectively associated with stereoscopic parameters for generating stereoscopic images Gb from the original images Ga. A retrieval means 13 compares an image characteristic value calculated by the calculation means 12 from a particular original image Ga, with each of the image characteristic values Nf stored in the storage device 21, to retrieve a stereoscopic parameter for the particular original image Ga on the basis of a comparison result.

Abstract: A display device that receives an input of video signal data including a plurality of pieces of frame data, corrects frame data representing a frame to be displayed based on frame data of a frame adjacent to the frame to be displayed, and outputs the resulting data as data to be displayed on a liquid crystal panel. The device comprises a memory unit adapted to store input frame data. The device determines a correction address used to determine a frame correction amount by comparing the stored frame data and frame data that is currently input; determines correction data that represents a correction amount of the frame data based on the stored frame data and the correction address; and corrects the frame data by adding and/or subtracting the correction amount represented by the correction data to or from the stored frame data.

Abstract: The invention pertains to an adaptive scaling technique. A look-up table of optimized filter coefficients is used to configure a multi-tap filter when scaling a video image. The look-up table reflects the scaling between standardized video source (input) resolutions and video display (output) resolutions. When an actual scaling factor does not correspond to an optimized operating point, a device driver determines which two scaling factors reflected in the look-up table are closest to the actual scaling factor. A set of interpolated filter coefficients for the multi-tap filter is then generated from the optimized filter coefficients associated with the two closest scaling factors. One advantage of the disclosed technique is that scaling operations are performed using filter coefficients interpolated from filter coefficients optimized for two similar scaling operations. Thus, the technique provides more precise filtering relative to prior art designs, resulting in higher-quality scaled video images.

Abstract: Described herein are a number of approaches for implementing a video encoder with hardware-enabled rewind functionality. In several embodiments, rewind functionality can be implemented in hardware, in a manner which allows the transform engine of the encoder to reprocess video data, without requesting data from other stages in the encoder. Such rewind functionality is useful in implementing some video standards in a pipeline architecture, such as the H.264 standard. In one embodiment, a method of encoding video data is described, which involves obtaining a first portion of video data from a first location in a buffer, and performing an encoding operation on it. The second portion of video data is obtained from a second location in the buffer, and encoding operations begin on the second portion. The first portion of video data can be retrieved from the first location, in order to reprocess the first portion if necessary.

Abstract: Image latency is reduced in a video display system where an image is displayed for a stroke video frame period. The system has a display device and a plurality of memory buffers, each of which is adapted to receive image data (in a receiving condition) or to display data to the display device (in a display condition). The stroke video frame period is divided into at least two time periods and the number of memory buffers provided is at least the number of time periods per stroke video frame period. One of the memory buffers is in the display condition for a first time period, with the remaining memory buffers in the receiving condition. At the end of the time period, the memory buffers are rotated so that the displayed memory buffer moves to the receiving condition and one of the receiving buffers moves into the display condition.

Abstract: A display device capable of saving memory storage used for an overdriving function includes a compression unit, a frame buffer, a decompression unit and a look-up table (LUT) unit. The compression unit includes a decimation filter and is used for compressing data of a received frame and reducing a size of the received frame, to generate a compression frame. The frame buffer is coupled to the compression unit and used for storing the compression frame. The decompression unit includes an interpolation filter and is used for decompressing data of the compression frame outputted by the frame buffer and reducing a size of the compression frame, to generate a decompression frame. The LUT unit is coupled to the decompression unit and used for comparing the decompression frame with a next received frame of the received frame to determine an overdriving voltage.

Abstract: A system and method for converting a pixel rate of a digital image frame is provided. The system includes a display controller with an embedded buffer and programmable input and output buffers. The input buffer writes lines of the frame at a source pixel rate while the output pointer reads out lines of the frame at a display pixel rate thereby allowing display of an image having a source pixel rate that is different, e.g., higher, than a display pixel rate.

Abstract: According to some embodiments, systems, methods, apparatus, computer program code and means are provided to set a first depth value associated with a plurality of pixels of a video image comprising a plurality of planes, create a first clear rectangle with respect to the first depth value, color render the pixels that are not associated with the first clear rectangle, and render the plurality of planes.

Abstract: A graphics system including a custom graphics and audio processor produces exciting 2D and 3D graphics and surround sound. The system includes a graphics and audio processor including a 3D graphics pipeline and an audio digital signal processor. The graphics system has a graphics processor includes an embedded frame buffer for storing frame data prior to sending the frame data to an external location, such as main memory. The embedded frame buffer is selectively configurable to store the following pixel formats: point sampled RGB color and depth, super-sampled RGB color and depth, and YUV (luma/chroma). Graphics commands are provided which enable the programmer to configure the embedded frame buffer for any of the pixel formats on a frame-by-frame basis.

Abstract: Methods and systems for processing pixels within a decoded video stream are disclosed. Processed pixels may be received within the decoded video stream and may be buffered in a buffer at a first rate. The buffered received processed pixels may be transferred out of the buffer at a second rate, where the first rate is greater than said second rate. The buffering of the received processed pixels and the transferring of the buffered received processed pixels out of the buffer may be monitored to prevent an overrun of the buffer. The first rate of the buffering of the received processed pixels may be reduced to prevent the overrun of the buffer. The second rate of the transferring of the buffered received processed pixels out of the buffer may be monitored to prevent the overrun of the buffer. Amount of the buffered received processed pixels within the buffer may be determined.

Abstract: Systems and methods for utilizing intermediate target(s) in connection with computer graphics in a computer system are provided. In various embodiments, intermediate memory buffers in video memory are provided and utilized to allow serialized programs from graphics APIs to support algorithms that exceed the instruction limits of procedural shaders for single programs. The intermediate buffers may also allow sharing of data between programs for other purposes as well, and are atomically accessible. The size of the buffers, i.e., the amount of data stored in the intermediate targets, can be variably set for a varying amount of resolution with respect to the graphics data. In this regard, a single program generates intermediate data, which can then be used, and re-used, by an extension of the same program and/or any number of other programs any number of times as may be desired, enabling considerable flexibility and complexity of shading programs, while maintaining the speed of modem graphics chips.

Abstract: System and method for reading and writing pixel aligned subframes from a frame buffer in a parallel processing system are disclosed. Optimal bandwidth access of the frame buffer requires that data be moved in bursts having multiple data words. Subframes are specified at X and Y locations within the image frame with a resolution of one pixel. In addition, subframes within a row may overlap each other and consecutive subframe rows may also overlap. Memory control logic of the invention provides pixel packing and unpacking and storing selected pixel data in a cache memory. Reading and writing to the frame buffer is provided in a manner that makes optimal use of the frame buffer internal architecture. Other capabilities of the memory control logic include decimation of pixel data during input, suppression of redundant frame buffer writes, and accessing image frame data in an interlaced manner.

Abstract: Apparatus, methods, and systems are disclosed to manage memory in an embedded system. The system registers video applications and video sources with a memory manager. The memory manager in turn provides memory to the video applications and video sources. The system has an input to receive an output from at least one video source. The memory manager receives a frame from the video source and transfers the frame to memory. Once the frame is in memory the video application may work with the frame. All of these operations are conducted with the memory manager actively managing and allocating the memory resources.

Abstract: A monitor having multiple displays within the same housing. The displays may be, for example, separate LCD panels that are placed in close proximity to one another so as to give the appearance of a single, large display. At least two of the displays may be treated by a computer connected to the monitor as a single display. A display controller divides a single frame of information that is provided by a display adapter of the computer into display information for multiple displays. By using the multiple display controller, the multiple display monitor may have more displays or panels than the number of cables linking the monitor to a computer. The special display controller also does not require a graphics card for each display. A three panel or display monitor is provided in which a central, centered work area display is framed by two side panels or displays.

Abstract: A motion estimation engine may be implemented to support multiple video encoding standards. The motion estimation engine may be designed to support two macroblock partitioning modes: one for frame type video signals and the other for mixed frame-field type video signals. Additionally, the motion estimation engine provides the mixing unidirectional option (forward/backward) and the mixing bidirectional option. Furthermore, the motion estimation engine may use a unified 4-tap interpolation filter for fractional macroblock search during motion estimation.

Abstract: A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, and graphics input. The chip includes a single polyphase filter that preferably provides both anti-flutter filtering and scaling of graphics. Anti-flutter filtering may help reduce display flicker due to the interlaced nature of television displays. The scaling of graphics may be used to convert the normally square pixel aspect ratio of graphics to the normally rectangular pixel aspect ratio of video.

Abstract: A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, and graphics input. The chip includes a single polyphase filter that preferably provides both anti-flutter filtering and scaling of graphics. Anti-flutter filtering may help reduce display flicker due to the interlaced nature of television displays. The scaling of graphics may be used to convert the normally square pixel aspect ratio of graphics to the normally rectangular pixel aspect ratio of video.

Abstract: An electronic system, an integrated circuit and a method for display are disclosed. The electronic system contains a first device, a memory and a video/audio compression/decompression device such as a decoder/encoder. The electronic system is configured to allow the first device and the video/audio compression/decompression device to share the memory. The electronic system may be included in a computer in which case the memory is a main memory. Memory access is accomplished by one or more memory interfaces, direct coupling of the memory to a bus, or direct coupling of the first device and decoder/encoder to a bus. An arbiter selectively provides access for the first device and/or the decoder/encoder to the memory. The arbiter may be monolithically integrated into a memory interface. The decoder may be a video decoder configured to comply with the MPEG-2 standard. The memory may store predicted images obtained from a preceding image.

Abstract: A relative position of each object with respect to a point of view is changed by changing at least one of information indicating a position of the point of view and information indicating a position of the object, the pieces of information being stored in a storage section. It is determined whether or not a distance from the point of view to each object in a virtual space is smaller than or equal to a predetermined distance, with reference to the information indicating the point of view and the information indicating the position of the object. Next, information indicating a transparency of an object whose distance is determined to be smaller than or equal to the predetermined distance is updated every a unit time so that the transparency of the object is gradually increased. A virtual image including the object is drawn with reference to the information indicating the transparency.

Abstract: Presented herein is a system for storing macroblocks for concatenated frames. A decoder system comprises a frame buffer. The frame buffer comprises one or more rows. A particular one of the rows stores macroblocks from a plurality of frames.