Abstract: Embodiments of the present invention include an arithmetic logic unit for use in a graphics pipeline. The arithmetic logic unit comprising a plurality of scalar arithmetic logic subunits wherein each subunit performs a resultant arithmetic logic operation in the form of [a*b “op” c*d] on a set of input operands a, b, c and d. The arithmetic logic unit also for produces a result based thereon wherein “op” represents a programmable operation and wherein further the resultant arithmetic logic operation is software programmable to implement a plurality of different graphics functions.

Abstract: A system and method for performing convolutions on image data using pre-computed acceleration data structures is disclosed. The method may include calculating intermediate convolution values for each of a plurality of blocks of pixels by performing an associative operation on the pixel values in each block. Each intermediate value may be associated with the block and indexed dependent on index values of pixels in the block. An image pyramid may include intermediate convolution values for multiple levels of acceleration by calculating intermediate convolution values for multiple block sizes. A convolution result for a kernel of an image may be produced by performing the associative operation on intermediate convolution values for non-overlapping blocks enclosed within the kernel and on pixel values associated with pixels in the kernel but not in one of the non-overlapping blocks. The methods may be implemented by program instructions executing in parallel on CPU(s) or GPUs.

Abstract: An arithmetic logic unit (ALU) in a graphics processor is described. The ALU includes circuitry for performing an operation using a first set of pixel data. The first set of pixel data is resident in a pipeline register coupled to the circuitry. A temporary register is coupled to the circuitry. The temporary register can receive a result of the operation. The temporary register allows a result generated using one set of pixel data to be used with a subsequent set of pixel data in the same ALU. The result of the operation can thus be used in a second operation with a second set of pixel data that resides in the pipeline register after the first set of pixel data.

Abstract: The printing system of the present invention enables the display of information to an operator indicating that printing has been halted even when it is the host computer that causes the halt in printing. When a print data preview is set, a print processor reads print data from a spool file, generates a preview image using a printer graphics driver and provides that preview image to a previewer. A status monitor then monitors and displays the status of a printer and the print processor.

Abstract: Disclosed are methods and apparatus for accomplishing the fetching or sampling of channels of pixels or texels such as neighboring pixels or texels or non-neighboring pixels or texels in a simultaneous operation in order to achieve optimization of the performance of a texture pipeline. In particular, logic is disclosed including selector logic configured to retrieve data including a plurality of channels from each of a plurality of pixels or texels and operable to select one channel from the plurality of channels of the data from each of the pixels or texels. The logic also includes combination logic configured to combine two or more of the selected channels into a single vector, such as an RGBA vector representing the color.

Abstract: An arithmetic logic stage in a graphics processor unit includes arithmetic logic units (ALUs) and global registers. The registers contain global values for a group of pixels. Global values may be read from any of the registers, regardless of which of the pixels is being operated on by the ALUs. However, when writing results of the ALU operations, only some of the global registers are candidates to be written to, depending on the pixel number. Accordingly, overwriting of data is prevented.

Abstract: Image acquisition refers to the taking of digital images of multiple views of the object of interest. In the processing step, the constituent images collected in the image acquisition step are selected and further processed to form a multimedia sequence which allows for the interactive view of the object. Furthermore, during the Processing phase, the entire multimedia sequence is compressed and digitally signed to authorize it viewing. In the Storage and Caching Step, the resulting multimedia sequence is sent to a storage servers. In the Transmission and viewing step, a Viewer (individual) may request a particular multi-media sequence, for example, by selecting a particular hyperlink within a browser, which initiates the downloading, checking of authorization to view, decompression and interactive rendering of the multi-media sequence on the end-users terminal, which could be any one of a variety of devices, including a desktop PC, or a hand-held device.

Abstract: A system, method and computer program product are provided for programmable vertex processing. Initially, a vertex program is identified including branch labels and instruction sequences with branch commands. The vertex program is then converted to a binary format capable of being executed by a hardware graphics pipeline. The vertex program may then be executed in the binary format utilizing the hardware graphics pipeline for transforming vertices. As an option, the vertex program is initially written in a textual format capable of being read by a human prior to being converted.

Abstract: A four-time resolution refinement of 3D-dither algorithm is provided in this present invention. A 4×2 pixel-block is treated as an observed unit in this present invention, which includes two 2×2 pixel-blocks. In order to eliminate moving lines and dithered edges, the two least significant bits (LSBs) of the pixels are treated depending on cases. For the first 2×2 pixel-block, when 2-bit LSBs being 01 and 11, the pixel being assigned a carry is an upper-left, lower-right, lower-left, and upper-right sequence in a 2×2 pixel-block for four sequential frames. For the second 2×2 pixel-block, when 2-bit LSBs being 01 and 11, the pixel being assigned a carry is a lower-left, upper-right, upper-left, and lower-right sequence in a 2×2 pixel-block for four sequential frames. For both 2×2 pixel blocks, no pixel is treated for 2-bit LSBs being 00. For 2-bit LSBs being 10, the pixel row of the 4×2 block switches between the upper and the lower row for every frame.

Abstract: A method for detecting an inappropriate video connection in an information handling system (“IHS”) that includes an integrated video controller, the integrated video controller operable to be coupled to a display device, is provided. The method includes determining if an add-in video controller is coupled to the IHS, the add-in video controller operable to be coupled to the display device. The method also includes determining whether the display device is coupled to the integrated video controller or the add-in video controller. The method further includes providing a notification that the display device is inappropriately coupled to the IHS if it was determined that both the add-in video controller is coupled to the IHS and the display device is coupled to the integrated video controller.

Abstract: An arithmetic logic stage in a graphics pipeline is described. The arithmetic logic stage includes a plurality of series-coupled scalar arithmetic logic units, each unit for performing an arithmetic logic operation on a set of input operands and for producing a result based thereon.

Abstract: An arithmetic logic unit (ALU) in a graphics processor is described. The ALU includes circuitry for performing an operation using a first set of pixel data. The first set of pixel data is resident in a pipeline register coupled to the circuitry. A temporary register is coupled to the circuitry. The temporary register can receive a result of the operation. The temporary register allows a result generated using one set of pixel data to be used with a subsequent set of pixel data in the same ALU. The result of the operation can thus be used in a second operation with a second set of pixel data that resides in the pipeline register after the first set of pixel data.

Abstract: A three-dimensional API for communicating with hardware implementations of vertex shaders and pixel shaders having local registers. With respect to vertex shaders, API communications are provided that may make use of an on-chip register index and API communications are also provided for a specialized function, implemented on-chip at a register level, that outputs the fractional portion(s) of input(s). With respect to pixel shaders, API communications are provided for a specialized function, implemented on-chip at a register level, that performs a linear interpolation function and API communications are provided for specialized modifiers, also implemented on-chip at a register level, that perform modification functions including negating, complementing, remapping, stick biasing, scaling and saturating.

Abstract: A graphics processor has elements of a graphics pipeline coupled by distributors. The distributors permit the process flow of pixel packets through the pipeline to be reconfigured in response to a command from a host.

Abstract: An ?-value ?P1 corresponding to a Z-value of each pixel in an original image and an ?-nonuniformity setting ?-value a UP which is a nonuniform ?-value in a virtual plane are synthesized into an ?-value ?P2. The color ICP of the original image and the fog color CP are synthesized into a fog image, based on the ?-value ?P2. A plurality of ?-nonuniformity setting ?-values provided for the virtual planes different in nonuniformity pattern are synthesized. The nonuniformity patterns are changed depending on the virtual camera information and time information. An ?-value used to synthesize the ?-nonuniformity setting ?-values is set based on a Z-value of each pixel in the original image. A Z-value of each pixel in the original image is used as an index number of a lookup table and the index color texture mapping is applied to a virtual object to convert the Z-value into an ?-value.

Abstract: According to one embodiment, an information processing apparatus includes a processor, a display controller which executes a graphics arithmetic process of drawing frames in a video memory in accordance with a drawing request from the processor, and executes a screen refresh process of updating a display screen of a display device by using the frames drawn in the video memory in accordance with a refresh rate which designates a number of frames to be output to the display device per unit time, a calculation unit which calculates, based on content of the drawing request, a maximum number of frames which are drawable by the display controller per unit time, and a control unit which executes an operation speed control process of decreasing an operation speed of the display controller, if the calculated maximum number of frames is greater than the number of frames designated by the refresh rate.

Abstract: A method of facilitating the reproduction of a presenter's desktop for attendees of a real-time collaboration. A bound portion of the desktop (the portion shared with the attendees) is logically divided into clusters. When the content of a cluster changes, the cluster is analyzed and one or more objects describing the content may be identified. Each object that is not already cached is cached and assigned a cache ID. Each object in the cluster is described in an object primitive to be sent to the attendees. Actions for reproducing the object on the attendees' clients are sent as action primitives. The object and action primitives allow the content of the presenter's desktop to be sent incrementally instead of sending the entire desktop.

Abstract: One embodiment of the present invention is directed to a graphics system comprising logic for generating a mask that identifies bits within a plurality of bits that are not to be impacted by a subsequent computation. The graphics system further comprises compression logic that is responsive to the mask for generating a compressed bit stream, such that the bits that are not to be impacted by the computation are not included in the compressed bit stream. Another embodiment of the present invention is directed to a graphics system comprising logic for generating a mask identifying positions within a plurality of positions of a bit stream that are to be removed during a compression operation.

Abstract: A method of performing a blending operation between a first pixel having a first pixel alpha value and a first pixel color data value and a second pixel having a second pixel alpha value and a second pixel color data value using a pre-defined set of logical operations and an associated set of pre-computed constant that includes calculating a first pixel blending factor and a second pixel blending factor based upon a selected Porter-Duff compositing equation, the first pixel alpha value, and the second pixel alpha value, such that there are no decisions to be made in an innermost calculation loop.

Abstract: Raster operations (ROPs) are executed using a few core blocks which implement the logical operations (e.g., AND, OR, XOR) forming the basis for the raster operations. In an embodiment, the core blocks are generated only for the basic Boolean operations namely AND, OR and XOR for the corresponding operands (one or two of the source, paint and destination). Each logical operation is performed by using the appropriate core block.

Abstract: In a system including a color liquid crystal panel, a drive control device for driving the panel, and a microprocessor, the drive control device reduces the burden on the microprocessor as well as power consumption. In a liquid crystal display drive control device that incorporates a memory for storing image data displayed on a color liquid crystal panel, reads out the image data sequentially from the memory, generates image signals of the three primary colors for each pixel of the panel, and outputs the image signals from external output terminals, the drive control device includes a transparency arithmetic circuit that applies calculation processing to two image data read out from built-in memory and generates data for a transparent display, supplies display data generated by the transparency arithmetic circuit to a driver, and makes the driver generate and output drive signals to the liquid crystal panel.

Abstract: Methods and systems for transparent depth sorting are described. In accordance with one embodiment, multiple depth buffers are utilized to sort depth data associated with multiple transparent pixels that overlie one another. The sorting of the depth data enables identification of an individual transparent pixel that lies closest to an associated opaque pixel. With the closest individual transparent pixel being identified, the transparency effect of the identified pixel relative to the associated opaque pixel is computed. If additional overlying transparent pixels remain, a next closest transparent pixel relative to the opaque pixel is identified and, for the next closest pixel, the transparency effect is computed relative to the transparency effect that was just computed.

Abstract: A three-dimensional API for communicating with hardware implementations of vertex shaders and pixel shaders having local registers. With respect to vertex shaders, API communications are provided that may make use of an on-chip register index and API communications are also provided for a specialized function, implemented on-chip at a register level, that outputs the fractional portion(s) of input(s). With respect to pixel shaders, API communications are provided for a specialized function, implemented on-chip at a register level, that performs a linear interpolation function and API communications are provided for specialized modifiers, also implemented on-chip at a register level, that perform modification functions including negating, complementing, remapping, stick biasing, scaling and saturating.

Abstract: A graphics processor is disclosed having a programmable Arithmetic Logic Unit (ALU) stage for processing pixel packets. Scalar arithmetic operations are performed in the ALUs to implement a graphics function.

Abstract: An image drawing apparatus includes a first data reading unit which stores a source image data into a first image data buffer. A second data reading unit reads a destination image data from a destination area of a memory device and stores the destination image data into a second image data buffer. A third data reading unit reads a transmission coefficient data from the memory device and stores the transmission coefficient data into a transmission coefficient data buffer. A transmission drawing processing control unit executes a transmission drawing processing for the source image data and the destination image data by using the transmission coefficient data to generate a processed image data. The transmission coefficient data has a block size that is the same as a block size of the source image data, and contains transmission coefficients that are varied with respect to every pixel of the source image data.

Abstract: A method and apparatus for optimizing processing of graphics data. An equation for use in processing graphics data is simplified by identifying variables in the equation that remain constant over a set of repeated operations. This simplified equation is implemented in a processing unit containing logic units, wherein the logic units are used to perform a graphics operation in which a set of constants is required for the graphics operation. A first set of connections is present in which these connections connect the logic units to each other, wherein the first set of connections are used to configure the plurality of logic units to determine the set of constants. A second set of connections connecting the logic units are present. This set of connections is used to configure the logic units to perform the graphics operation in which the graphics operation using the constants determined through the first set of connections.

Abstract: Methods and systems for transparent depth sorting are described. In accordance with one embodiment, multiple depth buffers are utilized to sort depth data associated with multiple transparent pixels that overlie one another. The sorting of the depth data enables identification of an individual transparent pixel that lies closest to an associated opaque pixel. With the closest individual transparent pixel being identified, the transparency effect of the identified pixel relative to the associated opaque pixel is computed. If additional overlying transparent pixels remain, a next closest transparent pixel relative to the opaque pixel is identified and for the next closest pixel, the transparency effect is computed relative to the transparency effect that was just computed.

Abstract: Provided are a method and apparatus for accelerating graphic data which can reduce the computational complexity of graphic processing data. The method of accelerating two-dimensional graphic data includes: receiving information regarding the width of a graphic window to be processed; reading pixel data from a memory in which pixel data in the graphic window is stored; receiving information regarding two pixel data regions which are divided from the memory area based on the width information of the graphic window, one pixel data region to be processed using a burst mode and the other pixel data region to be processed in units of bytes; and individually performing predetermined graphic processing on the divided pixel data regions.

Abstract: A system, method and computer program product are provided for branching during programmable processing utilizing a graphics application program interface in conjunction with a hardware graphics pipeline. Initially, a first instruction defined by the graphics application program interface is identified. A first operation is performed on graphics data based on the first instruction utilizing the hardware graphics pipeline. Any some point, the present technique may involve branching to an additional instruction defined by the graphics application program interface other than a subsequent sequential instruction. Next, another operation is performed on the graphics data based on the additional instruction utilizing the hardware graphics pipeline.

Abstract: A system, method and computer program product are provided for branching during graphics processing. Initially, a first operation is performed on data. In response to the first operation, a branching operation is performed to a second operation. The first operation and the second operation are associated with instructions selected from a predetermined instruction set.

Abstract: Disclosed is a division unit for use in a three-dimensional (3D) computer graphics system. The division unit can reduce an area and power consumption thereof by removing more significant bits from homogeneous texture addresses u and v by the number of leading zeros included in a homogeneous texture address w and approximately carrying out a division operation for decreased data in texture mapping of the 3D computer graphics system. Therefore, the performance of real-time texture mapping is enhanced in a portable device operating at low power and hence 3D computer graphics can be realistically implemented.

Abstract: An apparatus comprising a data modification circuit and a composite circuit. The data modification circuit may be configured to generate a first output data stream in response to a first one or more of the data streams. The composite circuit may be configured to generate a combined output data stream in response to the first output data stream and remaining data streams.

Abstract: A method and apparatus in a data processing system for performing a raster operation of graphics data. A system memory and a video memory is included in the data processing system. The system memory and the video memory are connected by a bus wherein the graphics data is organized into picture elements. A plurality of picture elements is read from the system memory. A plurality of picture elements is read from the video memory. A raster operation is performed on the plurality of picture elements to form a plurality of processed picture elements. The plurality of processed picture elements is written to the video memory.

Abstract: A three-dimensional API for communicating with hardware implementations of vertex shaders and pixel shaders having local registers. With respect to vertex shaders, API communications are provided that may make use of an on-chip register index and API communications are also provided for a specialized function, implemented on-chip at a register level, that outputs the fractional portion(s) of input(s). With respect to pixel shaders, API communications are provided for a specialized function, implemented on-chip at a register level, that performs a linear interpolation function and API communications are provided for specialized modifiers, also implemented on-chip at a register level, that perform modification functions including negating, complementing, remapping, stick biasing, scaling and saturating.

Abstract: A system and method for accessing a memory array where retrieved data is stored in a memory and upon the writing of the data in its modified form, the originally stored data is updated with the modification prior to being written back to the memory array. In this manner, a new error correction code can be calculated prior to writing the data without the need to access the memory array again.

Abstract: A graphics memory system for managing image data for a volumetric display that displays volumetric images, the system including a first buffer memory with a first predefined address space for holding image data for a three-dimensional image; a second buffer memory with as second predefined address space for holding image data for a three-dimensional image, wherein the first and second predefined address spaces are the same; and a voxel router in communication with both the first and second buffer memories, wherein the voxel router is configured to use a selectable one of the first and second buffer memories as an active memory out of which stored image data is to be read for display on the volumetric display and to use the other of the first and second buffer memories as an inactive memory into which image data is to be written.

Abstract: A three-dimensional API for communicating with hardware implementations of vertex shaders and pixel shaders having local registers. With respect to vertex shaders, API communications are provided that may make use of an on-chip register index and API communications are also provided for a specialized function, implemented on-chip at a register level, that outputs the fractional portion(s) of input(s). With respect to pixel shaders, API communications are provided for a specialized function, implemented on-chip at a register level, that performs a linear interpolation function and API communications are provided for specialized modifiers, also implemented on-chip at a register level, that perform modification functions including negating, complementing, remapping, stick biasing, scaling and saturating.

Abstract: A development environment and/or method for generating a user interface for a plurality of computing devices. The development environment and/or method may include a user interface modeling process for configuring information representing display capabilities of computing devices. The display capabilities may include a desired screen size parameter. As a function of the information configured, indicators are displayed or implemented to represent the respective screen size parameters of the computing devices. The development environment and/or method may also include an application generation process for comparing the information of the display capabilities of the computing devices with the information indicating placement location of a user interface component. If the information indicating placement location of the user interface component complies with a display capability, then the user interface component is stored in a database.

Abstract: The occurrence of an (n+m) input operand instruction that requires more than n of its input operands from an n-output data source is recognized by a programmable vertex shader (PVS) controller. In turn, the PVS controller provides at least two substitute instructions, neither of which requires more than n operands from the n output data source, to a PVS engine. A first of the substitute instructions is executed by the PVS engine to provide an intermediate result that is temporarily stored and used as an input to another of the at least two substitute instructions. In this manner, the present invention avoids the expense of additional or significantly modified memory. In one embodiment of the present invention, a pre-accumulator register internal to the PVS engine is used to store the intermediate result. In this manner, the present invention provides a relatively inexpensive solution for a relatively infrequent occurrence.

Abstract: A method, graphics engine boolean logic unit and digital video system that provide a raster operation unit capable of providing a raster and non-raster operation function(s) is provided. The raster operation may simultaneously conduct a raster function and non-raster operation function(s) by modification of at least one of a rasterop code and a pattern operand. The invention saves considerable logic since different functions are no longer executed separately and then multiplexed.

Abstract: An image processing system comprises: a plurality of operation pipelines to operate an inputted image data; a switching channel to switch a data transfer path to input operation results, which are outputted from the plurality of operation pipelines, to the plurality of operation pipeline again; and a control circuit to control switching of the data transfer path by the switching channel and to control an operation in the plurality of operation pipelines, the control circuit carrying out a scheduling of a plurality of operations, which form (n−k+1) unit operations from a unit operation k (1<k<n) to a unit operation n (n is a positive integer) of unit operations 1 to n, the plurality of operations prevented from overlapping with each other at the same predetermined operation time in the same operation pipeline when a unit operation included in the plurality of operations is executed by the plurality of operation pipelines.

Abstract: By using a unique display control technique, game images are provided, in which characters can be displayed in different poses with a limited-capacity memory area. Both image data corresponding to each of a plurality of blocks obtained by dividing a character to be displayed in a game image and further image data for representing different pictures in connection with at least part of the blocks are prepared. And the display pose of the character displayed in the game image is changed by switching a combination of the prepared image data. By way of example, color of at least part of the character displayed in the game image is changed on the basis of the combination of the same image data, thereby representing a plurality of types of characters. The color within the block mapped uppermost in the game image among the blocks constituting the character is kept unchanged regardless of changing of the color with respect to the remaining blocks.

Abstract: A graphics system comprising a programmable sample buffer and a sample buffer interface. The sample buffer interface is configured to (a) buffer N streams of samples in N corresponding input buffers, wherein N is greater than or equal to two, (b) store N sets of context values corresponding to the N input buffers respectively, (c) terminate transfer of samples from a first of the input buffers to the programmable sample buffer, (d) selectively update a subset of state registers in the programmable sample buffer with context values corresponding to a next input buffer of the input buffers, (e) initiate transfer of samples from the next input buffer to the programmable sample buffer. The context values stored in the state registers of the programmable sample buffer determine the operation of an arithmetic logic unit internal to the programmable sample buffer on samples data.

Abstract: A parallel processing processor for processing images including &agr; data indicative of pixel transparency. The parallel processing processor comprises: a plurality of execution units for executing in parallel arithmetic and logical operations under control of a single instruction; general purpose registers which are connected to the execution units via a data path, which input data to the execution units and which receive results of operations from the execution units; &agr; data dedicated registers which are connected to the execution units via another data path and which input data to the execution units; and a control circuit for directing data from the general purpose registers and &agr; data dedicated registers into each of the execution units under control of a single instruction.

Abstract: A graphic computing apparatus has a shape divider which generates a subpolygon mesh by dividing the unit shape of the surface of an object present in a three-dimensional space into a plurality of subpolygons arranged two-dimensionally and having an arbitrary size, a vertex processor which computes parameters required for drawing in units of pixels with respect to subpolygons for each vertex of the subpolygon mesh generated by the shape divider, a rendering processor for computing drawing data in units of pixels on the basis of the parameters computed by the vertex processor and picture data for texture mapping, and a frame memory which stores the drawing data as picture data, and at least data for texture mapping required for the rendering processor to compute the drawing data.

Abstract: Apparatus, methods, systems and computer program products are disclosed that optimize the application of deferred image operations on a tiled source image. The invention dynamically creates a data structure (such as a directed acyclic graph (DAG)) representing the operations performed on various instances of one or more images to create a final image. The invention analyzes the data structure to determine which source image tiles are needed when the actual image data comprising the final image is required. Each of these tiles are then separately processed by all of the deferred operations to create the final image data. This approach reduces the number of times a tile is read into memory for processing and improves the performance of deferred image operations on a tiled source image.

Abstract: A system and method for accessing a memory array where retrieved data is stored in a memory and upon the writing of the data in its modified form, the originally stored data is updated with the modification prior to being written back to the memory array. In this manner, a new error correction code can be calculated prior to writing the data without the need to access the memory array again.

Abstract: A display controller for a display apparatus having a memory function which can reduce power consumption efficiently is disclosed. A rewriting comparison circuit detects whether or not rewriting of different data by a graphic engine since the last display updating by a reflect control circuit, and stores resulting information into a TagRAM. The refresh control circuit checks the address of the TagRAM prior to the updating of the display and, only when the data at a corresponding address of a VRAM has been rewritten since the last display updating, the refresh control circuit performs reading in of the data from the VRAM and signaling of the data to the display apparatus having a memory function.

Abstract: A method and apparatus for reducing latency in pipelined circuits that process dependent operations is presented. In order to reduce latency for dependent operations, a pre-accumulation register is included in an operation pipeline between a first operation unit and a second operation unit. The pre-accumulation register stores a first result produced by the first operation unit during a first operation. When the first operation unit completes a second operation to produce a second result, the first result stored in the pre-accumulation register is presented to the second operation unit along with the second result as input operands.

Abstract: A system and method are provided for a dedicated hardware-implemented viewport operation in a graphics pipeline. Included is a transform/lighting module for transforming and lighting vertex data. Also provided is viewport hardware coupled to the transform/lighting module for performing a viewport operation on the vertex data. A rasterizer is coupled to the viewport hardware for rendering the vertex data.