Binary Weighted Patents (Class 345/692)
  • Patent number: 7456852
    Abstract: When an input detection unit has detected that no user operation has been performed to an organic EL display apparatus for a predetermined period of time or when a processing detection unit has detected that a predetermined processing is being performed, the input detection unit or the processing detection unit outputs an instruction to a reference voltage adjusting unit to modify a reference voltage referenced by a DAC unit upon conversion to an analog output signal.
    Type: Grant
    Filed: September 27, 2004
    Date of Patent: November 25, 2008
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Yukio Mori, Susumu Tanase, Atsuhiro Yamashita, Masutaka Inoue, Shigeo Kinoshita, Haruhiko Murata, Takashi Yabukawa, Hiroyuki Goya
  • Patent number: 7453477
    Abstract: An improved driving device for a display panel. In the display panel, pixel cells serving as pixels are positioned in a plurality of display lines. The driving device drives the display panel according to pixel data derived from an input image signal. The display lines are divided into a plurality of display line groups, and each group includes a plurality of neighboring display lines. The driving device has a light emission driving circuit. This circuit causes the pixel cells in each of the neighboring display lines in the respective display line groups to emit light at different brightness levels based on weighting values assigned to the display lines. The weighting values are assigned to the display lines such that bias in brightness differences between the pixel cells positioned in neighboring display lines falls within a prescribed range for all neighboring display lines in the display panel.
    Type: Grant
    Filed: June 16, 2004
    Date of Patent: November 18, 2008
    Assignee: Pioneer Corporation
    Inventors: Jun Kamiyamaguchi, Masahiro Suzuki, Tetsuya Shigeta, Hirofumi Honda, Tetsuro Nagakubo
  • Patent number: 7453478
    Abstract: A light modulator includes a control unit configured to receive an image input signal, and an array having a plurality of pixels arranged in a plurality of rows. The control unit is configured to provide a first address associated with the image input signal to the array in response to detecting a first mode of operation, and the control unit is configured to provide a second address associated with the image input signal to the array in response to detecting a second mode of operation. The array is configured to drive a first one of the plurality of rows in response to receiving the first address, and the array is configured to drive the first one of the plurality of rows and a second one of the plurality of rows in response to receiving the second address.
    Type: Grant
    Filed: July 29, 2004
    Date of Patent: November 18, 2008
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Eric T. Martin, Eugene J. Mar
  • Patent number: 7446782
    Abstract: This is an image processing device for predicting the lower-order bits of target pixel data, based on one or more pieces of pixel data constituting image data. The image processing device comprises a lower-order bit calculation unit for calculating the lower-order bits of the target pixel data, based on one or more pieces of pixel data constituting image data and specifying the data as corrected lower-order bits and a lower-order bit superimposition unit for superimposing the corrected lower-order bits calculated by the lower-order bit calculation unit on higher-order bits of the target pixel data.
    Type: Grant
    Filed: June 21, 2005
    Date of Patent: November 4, 2008
    Assignee: Olympus Corporation
    Inventors: Takashi Ishikawa, Masaki Higurashi
  • Patent number: 7443405
    Abstract: A gray-scale representation method for a plasma display panel, which method includes arranging, in time sequence, a plurality of subfields each having a brightness weight and achieving gray-scale representation by a combination of the subfields, each subfield including an address period and a sustain period. In the gray-scale representation method, the number of sustain pulses for each subfield is determined so that a light generated from the difference of the number of sustain pulses between two adjacent gray scales can be greater than a light discharged in the address period, when the number of subfields for the higher one of the two adjacent gray scales is less than that for the lower one. The reversion of gray scales that occurs when the address light is increased as high as the sustain light can be eliminated to achieve correct gray-scale representation.
    Type: Grant
    Filed: March 12, 2004
    Date of Patent: October 28, 2008
    Assignee: Samsung SDI Co., Ltd.
    Inventor: Yong-Jin Kim
  • Patent number: 7420571
    Abstract: A system and method for processing a gray level in a display device performs a random error diffusion operation on the video data using a first random coefficient value and a random dithering operation on the error-diffused video data using a second random coefficient value.
    Type: Grant
    Filed: November 24, 2004
    Date of Patent: September 2, 2008
    Assignee: LG Electronics Inc.
    Inventors: Jun Hak Lee, Dae Jin Myoung, Jung Hwan Kim
  • Patent number: 7420576
    Abstract: A display apparatus displaying gray scale by using a subfield method has a gain control circuit, a sub gain control circuit, and an error diffusion circuit. The gain control circuit has the number of gray scale levels of an input signal and outputting a first intermediate image signal with a first number of gray scale levels, and the sub gain control circuit receives the first intermediate image signal, compresses the number of gray scale levels of the first intermediate image signal, and outputs a second intermediate image signal with a second number of gray scale levels. The error diffusion circuit receives the second intermediate image signal and increase the number of gray scale levels by simulating additional gray scale levels through error diffusion.
    Type: Grant
    Filed: March 24, 2004
    Date of Patent: September 2, 2008
    Assignee: Fujitsu Hitachi Plasma Display Limited
    Inventors: Masanori Takeuchi, Masaya Tajima, Yutaka Chiaki, Shunji Ohta, Akira Yamamoto
  • Publication number: 20080198184
    Abstract: An image update scheme for an electrophoretic display reduces driving delays while allowing display of a reduced quality image when driving is interrupted. A first portion (605) of image data is transmitted to a display device (500) such as from a mobile network device (400). The first portion may include the MSB of a data word for each pixel. Each pixel (2) is driven to an associated first optical state (632) that is defined by the first portion. A second portion (606, 607) of the image data is subsequently received at the display device, and each pixel is driven to an associated second optical state (636) that is defined by the first and second portions. In another approach, the second portion includes a substantially complete representation of the image, and each pixel is driven to an associated second optical state (636) that is defined by the second portion.
    Type: Application
    Filed: May 19, 2006
    Publication date: August 21, 2008
    Applicant: KONINKLIJKE PHILIPS ELECTRONICS, N.V.
    Inventors: Nicholaas W. Schellingerhout, Edzer A. Huitema
  • Patent number: 7408527
    Abstract: A projection system is provided with a controller equipped to drive light emitting devices of a light source of the projection system in a manner that enhances the operational life of the light emitting devices, the ability to provide peak white, and/or finer gray scale.
    Type: Grant
    Filed: April 30, 2004
    Date of Patent: August 5, 2008
    Assignee: Infocus Corporation
    Inventor: David E. Slobodin
  • Patent number: 7403213
    Abstract: A method and system providing boundary dispersion to pixel values displayed on a binary spatial light modulator to reduce temporal contouring artifacts. Pixel code values are offset from a nominal value when displayed on the SLM to disperse a large bit transition for a pulse width modulation (PWM) system. The offset value varies as a function of the pixel digital code, the pixel spatial location on the screen, and pixel temporal location in time. The set of offsets applied to pixels is varied over a repeating sequence of 2 displayed frames.
    Type: Grant
    Filed: June 2, 1998
    Date of Patent: July 22, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Daniel J. Morgan, Gregory J. Hewlett, Peter F. VanKessel
  • Patent number: 7391391
    Abstract: A display apparatus divides each frame period of an input image signal into a plurality of subframes and selects the subframes according to a gray-scale level of the input signal, to display a gray-scale image. The display apparatus alternately employs two sets of tables having different gray-scale-level input/output characteristics, to move locations to cause false contours frame by frame, thereby minimizing false contours.
    Type: Grant
    Filed: November 8, 2004
    Date of Patent: June 24, 2008
    Assignee: Victor Company of Japan, Limited
    Inventor: Yoshinori Ohshima
  • Patent number: 7369144
    Abstract: A method for displaying a video image on a display screen by a scanning of the display screen along lines inclined by a first angle with respect to a reference direction by at least one electron beam modulated by a modulation signal. The method includes the steps of storing at least partly the successive initial digital video data associated with the image to be displayed in a memory; transmitting new successive digital video data corresponding to the image which would be displayed based on the stored initial digital video data for a scanning of the display screen along lines inclined with respect to the reference direction by a second angle opposite to the first angle; and providing the modulation signal based on the new transmitted successive digital video data.
    Type: Grant
    Filed: April 8, 2003
    Date of Patent: May 6, 2008
    Inventors: Benoît Marchand, Benoît D'Halluin
  • Patent number: 7365767
    Abstract: An apparatus for driving a plasma display panel and a method for processing pictures of a plasma display panel. An input video signal is converted into sub-field data. It is determined whether address consumption power of the sub-field data is high. When the address consumption power is high, interlaced scanning is carried out. It is determined whether lines having sub-field data items identical or similar in a row direction exist using the sub-field data. The lines are sequentially scanned. Accordingly, the number of times of switching address electrodes is reduced and thus the address consumption power is decreased.
    Type: Grant
    Filed: February 2, 2005
    Date of Patent: April 29, 2008
    Assignee: Samsung SDI Co., Ltd.
    Inventor: Soo-Jin Lee
  • Patent number: 7362336
    Abstract: A color display system including a display device for four or more visible color primaries and a processor for controlling the four or more color primaries to selectively render portions of an image or image sequence such that visually equivalent colors displayed in two or more image portions differ in their spectral composition.
    Type: Grant
    Filed: January 12, 2005
    Date of Patent: April 22, 2008
    Assignee: Eastman Kodak Company
    Inventors: Michael E. Miller, Michael J. Murdoch, Thomas E. Madden
  • Patent number: 7327373
    Abstract: A four-time resolution refinement of 3D-dither algorithm is provided in this present invention. A 4×2 pixel-block is treated as an observed unit in this present invention, which includes two 2×2 pixel-blocks. In order to eliminate moving lines and dithered edges, the two least significant bits (LSBs) of the pixels are treated depending on cases. For the first 2×2 pixel-block, when 2-bit LSBs being 01 and 11, the pixel being assigned a carry is an upper-left, lower-right, lower-left, and upper-right sequence in a 2×2 pixel-block for four sequential frames. For the second 2×2 pixel-block, when 2-bit LSBs being 01 and 11, the pixel being assigned a carry is a lower-left, upper-right, upper-left, and lower-right sequence in a 2×2 pixel-block for four sequential frames. For both 2×2 pixel blocks, no pixel is treated for 2-bit LSBs being 00. For 2-bit LSBs being 10, the pixel row of the 4×2 block switches between the upper and the lower row for every frame.
    Type: Grant
    Filed: March 9, 2004
    Date of Patent: February 5, 2008
    Assignee: Novatek Microelectronics Corp.
    Inventor: Richard Hung
  • Patent number: 7304621
    Abstract: An organic EL display apparatus includes: a display panel on which a plurality of pixel sections are provided; source drivers provided with pixel drivers, which includes current drivers for supplying drive currents to the pixel sections, registers for latching data signals and timing control units; signal lines for supplying the drive currents from the current drivers to the pixel sections. Each of the current drivers is controlled by the associated timing control unit to allow a current larger than or equal to a current which is set in accordance with the data signal to flow only during a given period in a current setting mode, so that the value of a current flowing in the pixel section reaches a target value in a short time.
    Type: Grant
    Filed: March 16, 2004
    Date of Patent: December 4, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tetsurou Oomori, Yoshito Date
  • Patent number: 7283113
    Abstract: A method and apparatus of driving a liquid crystal display device that is adaptive for preventing a deterioration of picture quality. More specifically, a method of driving a liquid crystal display includes dividing input data into most significant bit data and least significant bit data, delaying the most significant bit data for one frame period, and modulating the most significant bit data in accordance with a difference between the delayed most significant bit data and the current most significant bit data, wherein the modulated data have a data width not wider than that of the input data and not narrower than that of the most significant bit data.
    Type: Grant
    Filed: November 27, 2001
    Date of Patent: October 16, 2007
    Assignee: LG.Philips LCD Co., Ltd.
    Inventor: Yong Sung Ham
  • Patent number: 7256756
    Abstract: In a D/I conversion section of the semiconductor device for driving a light emission display device, a precharge circuit is provided at the rear of each 1-output D/I conversion section. A precharge signal PC is input into the precharge circuit. The D/I conversion section has two output blocks internally thereof, and a role for storing and outputting current is changed every frame to enable securing a period for driving a pixel longer. Further, at the time of driving, in the precharge circuit, current driving is carried out after a voltage corresponding to output current has been applied to the pixel, and therefore, the pixel can be driven at high speed. Thereby, output current of high accuracy can be supplied to digital image data to be input, and even where an output current value is low, the current load device can be driven at high speed.
    Type: Grant
    Filed: August 29, 2002
    Date of Patent: August 14, 2007
    Assignee: NEC Corporation
    Inventor: Katsumi Abe
  • Patent number: 7256755
    Abstract: A display apparatus displaying gray scale by using a subfield method has a main path, a sub path, a switch circuit, a motion region detection circuit, a first judging circuit, a level detection circuit, a motion detection correction circuit, and a second judging circuit. The switch circuit outputs a first image signal generated by the main path or a second image signal generated by the sub path by switching therebetween, and the first judging circuit outputs a first motion signal in accordance with an output of the motion region detection circuit. The motion detection correction circuit receives the first motion signal and a level signal, and outputs a second motion signal in accordance with the level signal, and the second judging circuit receives the second motion signal and the level signal, and outputs a switching control signal to the switch circuit.
    Type: Grant
    Filed: March 16, 2004
    Date of Patent: August 14, 2007
    Assignee: Fujitsu Hitachi Plasma Display Limited
    Inventors: Shunji Ohta, Masanori Takeuchi, Yutaka Chiaki, Masaya Tajima, Akira Yamamoto
  • Patent number: 7233342
    Abstract: To provide a display device which is capable of multi-gradation display without complicating the structure of a D/A converter circuit. Of m bit digital video data inputted from the external, upper n bit data is used as voltage gradation information and lower (m?n) bit data is used as time gradation information.
    Type: Grant
    Filed: February 22, 2000
    Date of Patent: June 19, 2007
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama
  • Patent number: 7224375
    Abstract: The invention relates to a method and a device for noise reduction in a pulse-width controlled image display device. A monitoring of whether the brightness of several sequential image points is brighter than a given brightness threshold value occurs. If not the case, the delayed but otherwise unchanged input signal is supplied to the display. If, on the other hand, the brightness of several sequential image points is less than the given threshold brightness value, a mean value generation for the brightness values of several sequential image points occurs and said mean value is supplied to the display.
    Type: Grant
    Filed: July 30, 2002
    Date of Patent: May 29, 2007
    Assignee: Grundig Multimedia B.V.
    Inventors: Udo Fischbeck, Johannes Spindler
  • Patent number: 7209152
    Abstract: A signal processor for multiple gradations for carrying out coding by replacing an input image signal with a plurality of subfields, comprising a main path for generating a primary color signal having a first number of gradations, a sub-path for generating a primary color signal having a second number of gradations, which is smaller than the first number of gradations, a switch, a movement detection circuit, a level detection circuit, a path switching control circuit for switching the switch based on the amount of movement and the level, plural subfield coding circuits for carrying out subfield coding different from each another, a superposing circuit for selecting one of the outputs of the plural subfield coding circuits, and a superposing control circuit, and thus preventing a moving false contour.
    Type: Grant
    Filed: March 16, 2004
    Date of Patent: April 24, 2007
    Assignee: Fujitsu Hitachi Plasma Display Limited
    Inventors: Yutaka Chiaki, Shunji Ohta, Masanori Takeuchi, Masaya Tajima, Akira Yamamoto, Yuichiro Kimura
  • Patent number: 7202847
    Abstract: A method and system for applying addressing voltages to pixels of a display involves receiving input data. The input data includes an indication of an addressing voltage impulse to be applied to a pixel via an electrode. One or more voltage sources are selected, to provide the addressing voltage impulse. The one or more voltage sources each have a pre-selected voltage. The selected one or more voltage sources are electrically connected to an electrode to apply the addressing voltage impulse to the pixel.
    Type: Grant
    Filed: June 27, 2003
    Date of Patent: April 10, 2007
    Assignee: E Ink Corporation
    Inventor: Holly G. Gates
  • Patent number: 7187392
    Abstract: The invention enhances gradation characteristics and realizes higher quality in a picture, in the context of subfield driving using a pixel provided therein with a memory. A method of driving an electro-optical device that divides a predetermined period of time into a plurality of subfields SF5 to SF17, performs gradational display with a combination of subfields SF corresponding to gradation data, and provides a memory storing gradation data that is provided in each of a plurality of pixels is disclosed. In the method, at least part of gradation data is written in a memory provided in each of pixels. Further, data written in the memory are repeatedly read several times based on gradation signals defining each of the subfields SF, and a voltage having time density corresponding to read data is repeatedly applied to the pixels to thereby perform gradational display in accordance with gradation data.
    Type: Grant
    Filed: June 13, 2003
    Date of Patent: March 6, 2007
    Assignee: Seiko Epson Corporation
    Inventor: Akihiko Ito
  • Patent number: 7184034
    Abstract: To provide a display device capable of allowing a light emitting element to emit light with a constant luminance while being free of an influence of deterioration over time and capable of accurate gradation display and high-speed writing of signal current to each pixel as well, in which an influence of noise causing leak current etc. is suppressed, and a driving method therefor. According to the present invention, plural pairs of switch portion and current source circuit are provided. Each of the plural switch portions is controlled in its switching operation according to a digital video signal. When the switch portion turns on, the current source circuit corresponding to the switch portion supplies current to allow the light emitting element to emit light.
    Type: Grant
    Filed: May 16, 2003
    Date of Patent: February 27, 2007
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hajime Kimura
  • Patent number: 7176863
    Abstract: A flat panel display is described having a matrix of liquid crystals, wherein the liquid crystals have a common node. A pair of voltages that are applied to the common node help determine the rms voltages that are applied to the liquid crystals. The pair of voltages are tailored to bring a maximum rms voltage that is applied to the liquid crystals so as to fall along the lower knee of a transmittance vs. rms voltage curve that characterizes the performance of the liquid crystals.
    Type: Grant
    Filed: April 23, 2002
    Date of Patent: February 13, 2007
    Assignee: Intel Corporation
    Inventor: Don Nguyen
  • Patent number: 7176948
    Abstract: A method for driving an LED backlight device using pulse width modulation with an additional timer to manage the power consumption, thermal output, and lighting level of the device with improved resolution.
    Type: Grant
    Filed: April 12, 2001
    Date of Patent: February 13, 2007
    Assignee: Honeywell International Inc.
    Inventor: Roger Lewis
  • Patent number: 7161608
    Abstract: Disclosed herein are visual display systems and methods capable of having shifted bit-weights in neutral density filtering (NDF) applications. In one embodiment, a method (200) of displaying an image comprises transmitting light through an optical filter (17) comprising at least one high transmissivity portion configured to output light at an initial intensity, and at least one low transmissivity portion configured to output light at a lower intensity than the initial intensity, where the initial intensity and lower intensity output light illuminates a spatial light modulator (14). The method also includes providing a plurality of data bits (non-ND) from a predetermined number of data bits (B0–B7), where each of the plurality comprises a pulse-width longer than a load-time for operating the spatial light modulator (14).
    Type: Grant
    Filed: January 7, 2004
    Date of Patent: January 9, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Gregory S. Pettitt, Harold E. Bellis, II, Jason R. Thompson, James F. Headley, Dana F. Segler, Jr.
  • Patent number: 7148868
    Abstract: A liquid crystal display is provided, which includes: a liquid crystal panel assembly including a plurality of pixels connected to a plurality of gate lines and a plurality of data lines; a signal controller for processing image data, the signal controller including a dynamic capacitance capture (“DCC”) block for modifying image data assigned to the pixels by selectively performing DCC on the image data based on the difference between the image data of a current frame (“current data”) and the image data of a previous frame (“previous data”); a gate driver for sequentially applying a gate-on voltage to the gate lines of the liquid crystal panel assembly; and a data driver selecting data voltages among a plurality of gray voltages in response to the modified image data from the signal controller and applies the data voltages to the data lines of the liquid crystal panel assembly.
    Type: Grant
    Filed: March 20, 2003
    Date of Patent: December 12, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Seung-Woo Lee
  • Patent number: 7142223
    Abstract: A de-interlacing methodology generates frames from interlaced video signals by incorporating data from multiple fields into an interpolation-based de-interlacing process. Pixels directly above and below a blank pixel location and pixels immediately before and after the blank pixel location (in the fields immediately preceding and following, respectively, the blank pixel field) can be used to interpolate a pixel value for the blank pixel location. The use of pixel data from multiple fields improves the resolution of the interpolation process, thereby improving output frame accuracy. Adjacent pixel values can also be adjusted to further improve the consistency of the visual display provided by the output frames.
    Type: Grant
    Filed: September 9, 2003
    Date of Patent: November 28, 2006
    Assignee: Huaya Microelectronics, Ltd.
    Inventor: Ge Zhu
  • Patent number: 7116301
    Abstract: When time division gradation display is carried out by setting a display state of an electro-optic element capable of R-gradation display A times in one frame period, the present invention determines the weights of the bit data to be such as 20:21:22:23?1: . . . , in which a conventional ratio regulation of 20:21:22:23: . . . i.e., 1:2:4:8: . . . is changed by at least one part at or later the third bit so as to satisfy the relation of B<RA where B expresses the number of display gradations. With this arrangement, it is possible to realize the time division gradation display with a desirable number of scanning lines and the desirable bit weight ratio, without significantly changing the actually-recognized image. On this account, the range of the electro-optic device, capable of setting each stage of outputs in the frame period to be a desirable value, can be enlarged with respect to a matrix display device using the time division gradation display.
    Type: Grant
    Filed: March 26, 2003
    Date of Patent: October 3, 2006
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Takaji Numao
  • Patent number: 7110010
    Abstract: A video signal is processed using dither coefficients. Dither coefficients pattern signals are generated. Each pattern signal carries positive and negative dither coefficients arranged in an (n×m) matrix where “n” and “m” being positive integers larger than zero, the sum total of the coefficients being zero. One of the pattern signal is selected for each predetermined unit of picture carried by the video signal. Or, it is selected according to locations of dither coefficients on pixels arranged on a display panel. Dither coefficients of the selected pattern signal are added to an input video signal, thus outputting a video signal to be supplied to the display panel. Instead of the dither coefficients pattern signals, dither pattern signals can be generated, each carrying positional data indicating locations of dither coefficients on the pixels on the display panel.
    Type: Grant
    Filed: October 12, 1999
    Date of Patent: September 19, 2006
    Assignee: Victor Company of Japan, Ltd.
    Inventors: Shigehiro Masuji, Hideki Aiba
  • Patent number: 7106351
    Abstract: In the driving of a subfield using a memory in a pixel, it is possible to display a higher number of gradations, while preventing the capacity of a memory from increasing. Data D0 to D2, among gradation data D0 to D5, are written in a memory provided in each of the pixels. The pixel is driven by applying voltage to the pixel with a time density in response to the data D0 to D2 written in the memory and gradation signals P0 to P2. In the same frame where the data is written, the remaining data D3 to D5 of the gradation data are written in the memory. The pixel is driven by applying voltage to the pixel with a time density in response to the data D3 to D5 written in the memory and the gradation signals P0 to P2.
    Type: Grant
    Filed: June 13, 2003
    Date of Patent: September 12, 2006
    Assignee: Seiko Epson Corporation
    Inventor: Akihiko Ito
  • Patent number: 7106290
    Abstract: A method of driving an EL display device in which pseudo contours are difficult to be seen is provided. A method of driving an EL display device in which a plurality of pixels, each having a first TFT, a second TFT, a third TFT, and an organic EL element, are formed has the following: n+m display periods (where n and m are both natural numbers) appear in one frame period; the n+m display periods each correspond to one bit of a digital video signal among n bits of the digital video signal; a plurality of display periods, among the n+m display periods, correspond to the same bit of the digital video signal; and display periods corresponding to other bits of the digital video signal, among the n+m display periods, appear during the plurality of display periods.
    Type: Grant
    Filed: September 4, 2001
    Date of Patent: September 12, 2006
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kazutaka Inukai, Mitsuaki Osame, Tomoyuki Iwabuchi
  • Patent number: 7075506
    Abstract: A method and system for performing spatial temporal multiplexing using a multi-threshold mask. A mask generator (404) outputs a threshold value for each pixel of a display. The mask generator typically creates a blue noise mask for a given pixel array that is replicated over the face of the entire display. The blue noise mask generator (404) typically is implemented as a memory lookup table. An index generator (402) provides an offset into the memory lookup table that allows the table to be shifted from time to time. The output of the blue noise mask generator (404), which may be the threshold value itself or a signal representing which threshold is being used, is an input to a selective inverter (406). The selective inverter (406) provides the option of inverting the blue noise mask. To reduce artifacts, the mask is periodically shifted and/or inverted. The value from the mask generator (404), whether inverted or not, is compared to the LSBs of the input data word to yield the fractional bit values.
    Type: Grant
    Filed: February 26, 2001
    Date of Patent: July 11, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Daniel J. Morgan, Jeffrey Kempf
  • Patent number: 7068292
    Abstract: A signal driver IC (or a display driver circuit in a broad sense) includes a signal electrode driver circuit which drives a signal electrode by using grayscale data. The signal electrode driver circuit has a precharge circuit, a DAC circuit, and a drive voltage adjusting circuit. The precharge circuit sets an output electrode connected to the signal electrode at a precharge voltage in a first stage which is a first period within one horizontal scanning period. In a second stage subsequent to the first stage, the DAC circuit sets the output electrode at a reference voltage based on the grayscale data. In a third stage subsequent to the second stage, the drive voltage adjusting circuit adjusts the voltage of the output electrode by using the grayscale data.
    Type: Grant
    Filed: January 30, 2003
    Date of Patent: June 27, 2006
    Assignee: Seiko Epson Corporation
    Inventor: Akira Morita
  • Patent number: 7061512
    Abstract: A display system 100 includes a light source 110 and a color wheel 114. An optical section 112 is arranged to receive light from the light source 110 and to direct the light toward a color wheel 114. A digital micromirror device 122 is arranged to receive the light from the color wheel 114 and to direct image data toward a display. The image data includes an array of pixels arranged in rows and columns. The array of pixels is arranged as curved color bands during a first time period and rectangular color bands during a second time period. The second time period being concurrent with but of a shorter duration than the first time period.
    Type: Grant
    Filed: June 10, 2003
    Date of Patent: June 13, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Daniel J. Morgan, Donald B. Doherty, William J. Sexton
  • Patent number: 7015883
    Abstract: In a light emission display drive method, a driver capable of performing control of three or more levels in the output brightness of each light emission element is provided and when the intermediate level is represented, a ?? modulator controls the distribution of the occurrence probability of each level, whereby multi-level gradation representation is conducted. At this time, one channel of ?? modulator is provided and a quantizer with “N-1”-value threshold, N-value output is used and the driver is controlled in response to output of the quantizer or separate ?? modulators are provided for weight multiple outputs and the input values to represent gradation are distributed through a distributor.
    Type: Grant
    Filed: March 6, 2002
    Date of Patent: March 21, 2006
    Assignee: Pioneer Corporation
    Inventor: Yoshiyuki Okuda
  • Patent number: 7006114
    Abstract: A standard voltage generating circuit generates standard voltages as many as the number of gradations. Then, the standard voltages are separated into standard voltages of high level and those of low level, by a selector circuit, regardless of polarities thereof. One of the standard voltages of high level thus separated by the selector circuit is selected by a Pch-arranged converting section of a D/A converting circuit. Then, the selected one of the standard voltages of high level is outputted as a gradation-display-use voltage. Meanwhile, One of the standard voltages of low level thus separated by the selector circuit is selected by an Nch-arranged converting section of the D/A converting circuit. Then, the selected one of the standard voltages of low level is outputted as a gradation-display-use voltage. With this arrangement, it is possible to attain miniaturization of a circuit and lower power consumption in a display apparatus which performs gradation display by a voltage modulation method.
    Type: Grant
    Filed: January 21, 2003
    Date of Patent: February 28, 2006
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Nobuhisa Sakaguchi
  • Patent number: 6985164
    Abstract: According to one embodiment of the invention, a method for displaying N-bit color on a plurality of pixels on a monitor includes, for each pixel, receiving a value indicative of one of a plurality of possible values for the level of intensity desired to be displayed on the pixel. The value is representable by N binary bits including a least significant bit. During a given time frame, the method includes providing an on state for the pixel for a continuous fractional portion of the given time frame. The fractional portion is indicative of the received value. The given time frame includes a fixed portion followed by a variable portion. For any of the possible values for the level of intensity, the time at which the pixel is turned on during the fixed portion, if at all, is independent of the least significant bit.
    Type: Grant
    Filed: November 21, 2002
    Date of Patent: January 10, 2006
    Assignee: Silicon Display Incorporated
    Inventors: Gerald D. Rogers, Ronnie N. Dunn
  • Patent number: 6980225
    Abstract: A liquid crystal display apparatus that uses a backlight for display includes a video signal time compression circuit for compressing a video signal in the time axis direction and outputting the time-compressed video signal, an LCD controller for driving a liquid crystal panel based on the time-compressed video signal, and a source driver and a gate driver. The liquid crystal display apparatus also includes a motion detection circuit for detecting the amount of motion of a display image based on the video signal, a PWM modulation pulse generation circuit for generating modulation pulses different in frequency according to the detection result from the motion detection circuit, and an inverter for lighting up the backlight based on the modulation pulses, to thereby enable reduction of image contour blurring in a moving image and reduction of flicker in a still image.
    Type: Grant
    Filed: March 20, 2002
    Date of Patent: December 27, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Taro Funamoto, Wataru Machidori, Katsuyuki Arimoto, Yoshihito Ohta, Takahiro Kobayashi, Yasuhiro Kumamoto, Tetsuo Kariya
  • Patent number: 6930693
    Abstract: In a method of signal processing for greyscale imaging in which weighted bitplanes corresponding to a greyscale image are stored as binary strings in sequential locations in a memory, in decreasing order of intended duration (weighting), a number of read passes equal to the number of weighted bitplanes are made from the set of stored bitplanes, each pass commencing with the highest order bitplanes and continuing along the stored bitplanes in sequence, the lengths of the sequences being varied and selected such that at the end of the said number of read passes each bit plane has been read out a plurality of times proportional to or equal to its duration (weighting). The method has utility in driving high speed liquid crystal matrix arrays particularly where each bitplane needs to be refreshed. A small ac potential may be applied to the array between writing steps.
    Type: Grant
    Filed: December 16, 1999
    Date of Patent: August 16, 2005
    Assignee: QinetiQ Limited
    Inventors: Timothy M Coker, William A Crossland
  • Patent number: 6930692
    Abstract: In a method of multi-level spatial light modulation, using a weighted bit plane technique where an n-digit binary number represents the intended grey level of each pixel location in an array of binary pixels, representative binary numbers are altered to closely adjacent values such as to reduce the inequality of 1s and 0s therein. The method may be applied to a single frame so modifying the gray scale somewhat, or a multi-frame method may be used in which at least some binary numbers are altered to different values in different frames for reducing the inequality of 1s and 0s over the set of frames, while maintaining or approximating the gray scale value as a time average. The methods are particularly useful for maintaining or approximating pixel-wise dc balance in liquid crystal spatial array modulators.
    Type: Grant
    Filed: December 16, 1999
    Date of Patent: August 16, 2005
    Assignee: QinetiQ Limited
    Inventors: Timothy M Coker, William A Crossland
  • Publication number: 20040263541
    Abstract: A display apparatus displaying gray scale by using a subfield method has a gain control circuit, a sub gain control circuit, and an error diffusion circuit. The gain control circuit has the number of gray scale levels of an input signal and outputting a first intermediate image signal with a first number of gray scale levels, and the sub gain control circuit receives the first intermediate image signal, compresses the number of gray scale levels of the first intermediate image signal, and outputs a second intermediate image signal with a second number of gray scale levels. The error diffusion circuit receives the second intermediate image signal and increase the number of gray scale levels by simulating additional gray scale levels through error diffusion.
    Type: Application
    Filed: March 24, 2004
    Publication date: December 30, 2004
    Applicant: FUJITSU HITACHI PLASMA DISPLAY LIMITED
    Inventors: Masanori Takeuchi, Masaya Tajima, Yutaka Chiaki, Shunji Ohta, Akira Yamamoto
  • Patent number: 6831618
    Abstract: A method for driving a display panel which enables changing of the refresh rate, without degrading display quality, of a display panel employing the matrix display scheme for carrying out gray-scale drive by using the sub-field method. By the method, the number of sub-fields to be executed within a unit display period is changed in response to the vertical synchronization frequency of an input video signal.
    Type: Grant
    Filed: March 3, 2000
    Date of Patent: December 14, 2004
    Assignee: Pioneer Corporation
    Inventors: Masahiro Suzuki, Nobuhiko Saegusa
  • Publication number: 20040246279
    Abstract: Dot inversion schemes are disclosed on novel display panel layouts with extra drivers.
    Type: Application
    Filed: June 6, 2003
    Publication date: December 9, 2004
    Inventors: Thomas Lloyd Credelle, Matthew Osborne Schlegel
  • Publication number: 20040246278
    Abstract: A system and method are disclosed for compensating for visual effects upon panels having non-standard dot inversion schemes. A display comprises a panel comprising a plurality of subpixels. The panel has at least two regions of subpixels having different electro-optical properties. The display also comprises separate quantizers for each of the at least two regions of subpixels that can correct for fixed pattern noise.
    Type: Application
    Filed: June 6, 2003
    Publication date: December 9, 2004
    Inventor: Candice Hellen Brown Elliott
  • Publication number: 20040246280
    Abstract: Systems and methods are disclosed to correct for image degraded signals on a liquid crystal display panel are disclosed. Panels that comprise a subpixel repeating group having an even number of subpixels in a first direction may have parasitic capacitance and other signal errors due to imperfect dot inversion schemes thereon. Techniques for signal correction and localizing of errors onto particular subpixels are disclosed.
    Type: Application
    Filed: June 6, 2003
    Publication date: December 9, 2004
    Inventors: Thomas Lloyd Credelle, Roger Green Stewart
  • Patent number: 6819335
    Abstract: A liquid crystal display 200 comprises a 1024-to-1021 gray scale conversion calculator 1 for converting an image data A(1024) of 1024 gray levels (=10 bits) into an image data Y(1021) of 1021 gray levels, an adjusting four-level sample storage 22 and a random number generator circuit 3 for randomly selecting and releasing on the frame-by-frame basis a group of the adjusting four gray levels &Dgr;1p to &Dgr;4p, &Dgr;1q to &Dgr;4q, and &Dgr;1r to &Dgr;4r which is determined by the least two bits Y(1021—d2) of the image data Y(1021) of 1021 gray levels at each of segments (p,q,r) of one pixel, an adder 23 for summing the upper eight bits Y(102113 d8) of the image data Y(1021) of 1021 gray levels and one group of the adjusting four gray levels to have three sets of image data of 256 gray levels D1p to D4p, D1q to D4q, and D1r to D4r which are then released in a sequence, and a 256 gray scale three-segment monochrome liquid crystal display panel 24.
    Type: Grant
    Filed: November 26, 2002
    Date of Patent: November 16, 2004
    Assignee: Totoku Electric Co., Ltd.
    Inventor: Tatumi Naganuma
  • Patent number: 6784898
    Abstract: A method for generating a grayscale representation for a display combines analog and digital techniques to produce images of optimal quality. The grayscale representation is not limited by frame frequency compared to digital techniques and not limited by small voltage differences between pixel electrodes. In the method, a frame is first divided into sub-frames of most significant bits and least significant bits. The sub-frame time can either be weighted or uniform. An analog voltage is then applied to the sub-frames to produce a reduced grayscale. The number of sub-frames and the brightness are two parameters that can be optimized for a best possible display result.
    Type: Grant
    Filed: November 7, 2002
    Date of Patent: August 31, 2004
    Assignee: Duke University
    Inventors: Sangrok Lee, Kristina M. Johnson