Abstract: A method for converting a sink device and an apparatus for providing a content using the same are provided. The method for converting the sink device includes receiving a sink device conversion command from a first sink device, transmitting the content to a second sink device if a conversion approval of the sink device is received from the second sink device, and transmitting a control authority related to a content provision from the first sink device to the second sink device.

Abstract: There is provided a display device including a video display portion that displays video, and a video signal control portion which performs signal control on an input signal such that a plurality of video streams formed of a plurality of chronologically arranged unit videos are input and there is a case in which display periods of the plurality of video streams are different with respect to an interval of the input signal that includes the plurality of video streams, and which sequentially switches in a time division manner the video streams included in the signal controlled input signal, and outputs the video streams to the video display portion.

Abstract: An imaging system having an imaging device for producing images of objects and picture signals and an imaging controller connected to the imaging device through a transmission line. The imaging device includes a vertical synchronizing signal-producing circuit to produce an internal vertical synchronizing signal for the production of images of objects. The imaging controller includes a delay-measuring circuit and a vertical-synchronization phase-advancing circuit. In the system, the imaging controller transmits a test signal to the imaging device and receives the test signal returned from the imaging device. The delay-measuring circuit measures a delay of a phase of the returned test signal relative to a phase of the transmitted test signal. The vertical-synchronization phase-advancing circuit then advances a phase of an external vertical synchronizing signal by the delay and transmits the external vertical synchronizing signal to the imaging device.

Abstract: An image processor for a robot system, performing image processing for a video signal output from a camera. The camera can output a first video signal including obtained image data as well as internal vertical and horizontal synchronization signals, and output a second video signal including image data obtained based on external vertical and horizontal synchronization signals as well as the external vertical and horizontal synchronization signals.

Abstract: The present invention discloses a video system provided with a display device for displaying a video image including a first video image and a second video image and an eyeglass device for assisting a viewer in viewing the video image, wherein the display device includes: a display for displaying the first and second video images; a first generator for generating a synchronizing signal in synchronization with the first video image; and a transmitter for transmitting the synchronizing signal to the eyeglass device, and the eyeglass device includes: a receiver for receiving the synchronizing signal; a second generator for generating an internal signal in synchronization with the second video image, based on the synchronizing signal; an optical filter portion for adjusting amounts of incident light to left and right eyes, respectively; and a controller for controlling the optical filter portion based on the internal signal.

Abstract: A programmable fractional phase-locked loop for generating a 148.50000 MHz high-definition television reference clock and a 148.35164 MHz high-definition reference clock from a 27 MHz crystal is disclosed. To generate the 148.50000 MHz reference clock, the fractional phase-locked loop is multiplied by 11/2, and to generate the 148.35164 MHz reference clock, the fractional phase-locked loop is multiplied by 500/91. Inside the fractional-phase locked loop however, the fraction 11/2 is represented by a denominator that is an integral power of 2, and the fraction 500/91 is represented by a denominator that is an integral multiple of 91.

Abstract: When a vertical sync pulse detection circuit mistakenly detects a vertical sync pulse in an inputted video signal, a sync stability detection circuit detects whether a detection signal of the vertical sync pulse detection circuit and a timing signal generated from a count value of a first frame cycle counter are in accordance, and the accordance confirmation detection result becomes one of discordance. When this occurs, the count value of the first frame cycle counter is not loaded to a second frame cycle counter so, due to the operation of the second frame cycle counter, a timing generating decoder circuit and a vertical sync signal generating circuit, a vertical sync signal at the previously detected normal phase can be generated.

Abstract: A method and an apparatus for synchronizing a data stream are disclosed. The method includes: decoding the data stream to generate a decoded data stream and program clock references; generating a local clock reference; generating a simulated clock reference according to the program clock references and the local clock reference; comparing the local clock reference with the simulated clock reference to generate a comparison result; adjusting a processing timing of the decoded data stream according to the comparison result; and processing the decoded data stream according to the processing timing.

Abstract: A video synchronization signal generating circuit includes a sample and hold circuit, a voltage divider and an amplifier. The voltage divider produces an adaptive voltage level based at least in part on an output of the sample and hold circuit. The amplifier, which receives a video signal, is connectable by switches in different configurations. In a first configuration the amplifier acts as a comparator to compare the adaptive voltage level with the video signal. An output of the amplifier in the first configuration is an output of the video synchronization signal generating circuit. In a second configuration the amplifier forms part of the sample and hold circuit.

Abstract: A system and method are used to generate pseudo MPEG information from digital video information. An artificial time stamp module and a data transport device can be used to generate the pseudo MPEG information, including associating an artificial time stamp with the digital video information. This pseudo MPEG information can be decoded as MPEG information.

Abstract: A circuit for generating a timing signal, the circuit having a memory and a pulse generator, the timing signal consisting of a number of pulses. The memory stores pulse count data, including an indication of the number of pulses in the timing signal, and rising edge and falling edge position data of the timing signal. The pulse generator produces the timing signal in accordance with the pulse count data and has a first circuit for generating rising edge signals, a second circuit for generating falling edge signals, an active control circuit for setting, in correspondence only with the pulse count data, corresponding rising edge signals as active state rising edge signals, and corresponding falling edge signals as active state falling edge signals, and a third circuit for generating said timing signal corresponding to the active state rising edge signals and the active state falling edge signals.

Abstract: The invention concerns receive circuitry for extracting horizontal and vertical synchronization signals from a digital synchronization signal associated with a video signal, the digital synchronization signal having a plurality of pulses, the receive circuitry including detection circuitry arranged to determine a first value indicative of the time delay between a timing edge of a first pulse and a timing edge of a second pulse of the digital synchronization signal; and a synchronization extraction block arranged to determine that one of the plurality of pulses is a vertical synchronization pulse based on a comparison between the first value and a reference value.

Abstract: A highly integrated data structure for synthesizing a waveform is provided for facilitating integrated handling of the data. The data structure for waveform synthesis data or use in generation of a target waveform comprises, at a macro level, a macro waveform value data field for storing a waveform value data section including source waveform value data for use in the generation of the target waveform, and a macro (first) header including control data for forming a macro waveform in the target waveform using the source waveform value data included in the data field. At a micro level, the data structure according to the present invention comprises a micro waveform value data field, and a micro (second) header for generating a micro waveform in the target waveform using the waveform value data included in the micro waveform value data field.

Abstract: A signal processing method by adding odd and even field SYNC data for neutralized effects including the steps of receiving an odd field SYNC data of an odd field, which is different at a certain data segment when compared with an even field SYNC data of an even field, and the even field SYNC data of the even field; adding the odd field SYNC data and the even field SYNC data to neutralize the odd and even field SYNC data so as to generate a combined odd and even field SYNC data; and performing a predetermined signal processing on an input signal according to the combined odd and even field SYNC data.

Abstract: Sync positions are detected from a video signal. The detected sync positions are processed (e.g., averaged) to generate modified sync positions. The detected sync positions and the modified sync positions are selectively used to sample and synchronize a color signal derived from the video signal. For example, the detected sync positions and the modified sync positions may be selectively used to sample and synchronize the color signal responsive to differences between the modified sync positions. The invention may be embodied as apparatus and/or methods.

Abstract: Video signal processing systems and methods for detecting horizontal synchronization signals within video signals. Digital filtering methods are implemented for processing analog video signals to determine time varying characteristics of video signals to detect the starting and ending positions of horizontal synchronization pulses in a video signal with increased accuracy. In addition, adaptive methods are implemented for dynamically determining various video signal parameters over time, such as blanking level BL, threshold value (slice) level and synchronization level SL using information extracted from digitally filtered video signals.

Abstract: A sync separation section separates an external horizontal synchronizing signal from an input video signal. A line locked PLL receives the external horizontal synchronizing signal as a reference signal and generates an internal horizontal synchronizing signal. A determination section computes a time integral value of a phase difference between the external horizontal synchronizing signal and the internal horizontal synchronizing signal and determines whether or not the time integral value exceeds a threshold value. A control section performs the control of switching an output frequency of the line locked PLL based on a determination result from the determination section.

Abstract: A video signal synchronization signal generating apparatus for making a display reference synchronization signal Vb that serves as a reference of video display and has a first frequency and an input synchronization signal Vi that constitutes images and has a second frequency synchronized with each other, the apparatus including: a frequency ratio generating section configured to divide a frequency that is double the first frequency by the second frequency to calculate a frequency ratio n; a Vx generation comparator circuit section configured to generate coincidence signal Vx? having pulses that are inserted by equally dividing one period of the input synchronization signal Vi by the frequency ratio n; and a Vx generation circuit section configured to remove the alternate pulses of the coincidence signal Vx? to generate synchronization signal Vx of a same phase as the phase of the input synchronization signal Vi.

Abstract: A video switcher includes: a video signal switching device for switching a video signal to be transmitted to a video display unit from a first video signal supplied from a first video input unit into a second video signal supplied from a second video input unit; and a synchronization signal switching device for switching a synchronization signal to be transmitted to the video display unit from a first synchronization signal supplied from the first video input unit into a second synchronization signal supplied from the second video input unit. The synchronization signal switching device starts transmission of the second synchronization signal to the video display unit after stops transmission of the first synchronization signal to the video display unit.

Abstract: System and method for digitally correcting time base errors in video display systems. A preferred embodiment comprises 1) correcting time base errors in a first portion of a horizontal line of video information, wherein the first correcting makes use of an error estimate for the horizontal line of video information and a preceding horizontal line of video information, 2) correcting time base errors in a second portion of a horizontal line of video information, wherein the second correcting makes use of an error estimate for the horizontal line of video information, and 3) repeating the first correcting and the second correcting for remaining horizontal lines of video information in the digitized video signal.

Abstract: An image-data output device that outputs image data and a signal for an output control device to load the image data, the output control device taking control of outputting the image data to a device, is provided and includes: a first signal generating section that generates a vertical synchronizing signal for the output control device to load the image data; a second signal generating section that generates a horizontal synchronizing signal; a third signal generating section that generates an outputting-image-data synchronizing signal for the output control device to load the image data, the outputting-image-data synchronizing signal having a suspension period in a duration that the vertical synchronizing signal is effective and the horizontal synchronizing signal is ineffective; a first output terminal that outputs the vertical synchronizing signal to the output control device; and a second output terminal that outputs the outputting-image-data synchronizing signal to the output control device.

Abstract: A first frame of data is encoded and a first timestamp associated with the first frame of data is generated. The first timestamp includes complete timing information. The first frame of data and the associated first timestamp is transmitted to a destination. A second frame of data is encoded and a second timestamp associated with the second frame of data is generated. The second timestamp includes a portion of the complete timing information. The second frame of data and the associated second timestamp is then transmitted to the destination. Additional frames of data are encoded and additional timestamps associated with the additional frames of data are generated. The majority of the additional timestamps include a portion of the complete timing information.

Abstract: A digital video signal transmitter is provided that comprises a digital video supplier, a synchronization signal generator, and a signal generator. The digital video supplier supplies a digital video signal including effective pixel signals comprised of pixel data from an effective pixels area and blanking signals comprised of data from a blanking area. The synchronization signal generator outputs a synchronization signal which is synchronized with the digital video signal. The signal generator generates a compound video signal in which a plurality of synchronization-indication signals that indicate the timing of the synchronization signal is incorporated into the blanking signals with respect to the digital video signal and the synchronization signal.

Abstract: A synchronization signal detection circuit and method of a digital TV (DTV) receiver are provided. The synchronization signal detection circuit determines a precise main path by determining powers in consideration of the influence of multiple paths near signals located at a peak value location and guarantees a stable operation of an equalizer by using error values output from a decoder to generate a synchronization locking control signal. A power signal based on the correlation of the received signal with a PN511 sequence is filtered to compensate for a dynamic multipath distortion (e.g., due to other multipath signals near signals located at a peak value location). The magnitude of the filtered power signal is then compared (e.g., with a predetermined threshold value) to determine the position of the main path (e.g., at the peak value location, or at a pre or post multipath signal location).

Abstract: The invention relates to a method and to a device for synchronizing the image capture by cameras. For this purpose, a duplex-capable network is provided. Within the network, one or more hardware-supported synchronization modules with a logical channel of a first type are provided, wherein the synchronization module or modules transmit, via the logical channel, image-capture signals that control the capture time of image sensors, wherein the image-capture signals are received by image-capture devices, and wherein the image-capture devices each capture an image as a response to the reception of an image-capture signal, and wherein the image data is then transmitted via the network by the image-capture devices via a logical channel of a second type.

Abstract: A system and method for providing digital AV signal to multiple displays where the digital AV signal is displayed simultaneously and sychronized. Exemplary embodiments utilize serializers, de-serializers, and clock cleaners to transmit the data to a chain of display nodes. The display nodes convert the serial data stream into a parallel data stream. The parallel data stream is de-jittered and used to drive a display and optional audio system. The parallel data stream is then converted back into a serial data stream and sent to the next display node in the chain. A clock present in the data stream allows synchronization of all the displays in the chain. A distribution display node may be used at any display node location to increase the number of chains in the data delivery system.

Abstract: A buffer control device is provided with a nearly flow detecting section, a vertical cycle control section and a vertical synchronization signal generating section. The nearly flow detecting section compares the amount of data accumulated in a buffer and predetermined thresholds and detects the result of the comparison as nearly overflow or nearly underflow. The vertical cycle control section adjusts the length of a vertical synchronization cycle according to the result of the comparison by the nearly flow detecting section. The vertical synchronization signal generating section generates a new vertical synchronization signal from the result of the adjustment by the vertical cycle control section.

Abstract: When a start recording instruction or an end recording instruction is transmitted from a terminal device, a DTMF detector (106) detects a DTMF signal and supplies the detection results to a control module (107). The control module (107) supplies the received start recording instruction or end recording instruction to an image data converter (105) and a switch (108). When a start recording instruction is received as input, the image data converter (105) converts the reception image data (103) to image data that have undergone intramode coding and supplies the result to the switch (108). The switch (108) supplies a storage device (110) with the image data that were supplied from image data converter (105) at the time that a start recording instruction is received as input, and supplies the storage device (110) with reception image data (103) from the time that recording has started until the input of an end recording instruction.

Abstract: An apparatus for adjusting a pixel clock frequency based on a phase locked loop (PLL) includes: a pixel clock generator (11) for generating an actual pixel clock having an actual frequency; a division frequency counter (12) for dividing the actual pixel clock into several pixel clocks having different frequency ranges by means of multiplying the actual frequency of the actual pixel clock by a multiplier; a reference frequency counter (13) for dividing the actual pixel clock by means of lowering the actual frequency of the actual pixel clock, and generating a reference frequency; a reactive frequency counter (14) for dividing the actual pixel clock by means of heightening the actual frequency of the actual pixel clock, and generating a reactive frequency; a PLL circuit (16) for integrating the reference frequency and the reactive frequency to generate a required pixel clock having a required frequency. A related method is also disclosed.

Abstract: An integrated receiver with dual channel transport stream decoding and delivery substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides multiple time-base clocks for two transport streams. Transport processor circuitry uses multiple PCRs to track transport streams through decoding, storage and or delivery of the decoded signals for display. Provision of a multiple time-base clock for decoding and delivering multiple transport streams allows display of the two decoded audio-video signals on independent monitors.

Abstract: A timing generator and method of developing drive signals which, when input sync signals are present, delivers the leading and trailing edges of the input pulses directly to a drive output and which generates a free-running signal when input sync pulses are not present.

Abstract: An apparatus and method of interfacing video information which can provide an accurately displayed video picture irrespective of the type of a video input signal by interfacing the video display information between a main body and a monitor, and thus maintaining the optimum picture state. The apparatus includes a main body for outputting a video signal and information on a display type of the video signal, and a monitor for detecting the display type of the corresponding video signal in accordance with the display type information outputted from the main body and displaying on a display screen the video signal outputted from the main body to match the detected display type.

Abstract: A video synchronization signal detector for detecting occurrences of single and double frequency synchronization signal pulses present during a vertical synchronization interval.

Abstract: The present invention provides a synchronization system comprising a base unit and at least one video camera. The base unit includes a master time-base adapted to set a time period that samples a frame of video data, a memory, and a base unit communications transceiver. The base unit communications transceiver is adapted to transmit a frame synchronization signal to a video camera communications transceiver. The video camera includes an image sensor adapted to store the video data, an exposure control adapted to control an exposure level of the image sensor, and a camera time-base adapted to receive the frame synchronization signal from the video camera communications transceiver. The camera time-base is further adapted to receive the frame synchronization signal, reset its time and initiates its internal timing sequence, transmit signals to the exposure control to control a length of the exposure, and transmit timing signals to the image sensor to read the video data.

Abstract: An apparatus for transmitting a video signal includes a signal detector, a multiplexer and a transmitter. The signal detector detects the video signal from the source to determine whether the horizontal sync signal and the vertical sync signal of the video signal are independent or composite. The multiplexer generates a composite sync signal by combining the horizontal sync signal and the vertical sync signal with reference to timing characteristics of the horizontal sync signal and the vertical sync signal while the horizontal sync signal and the vertical sync signal are detected as independent signals, and bypasses the composite sync signal while the horizontal sync signal and the vertical sync signal are detected as the composite sync signal. The transmitter transmits the video signal with the composite sync signal to the destination via a media. A method for transmitting the video signal is also disclosed.

Abstract: A video data stream containing picture video and a vertical synchronization signal is processed in a microprocess that performs statistical evaluation of the frequency of the vertical synchronization signal of the video data stream. The statistical evaluation includes producing the statistical mean value and variance of the frequency of the vertical synchronization signal.

Abstract: The present invention relates to a separating device of sequential interlaced video scenes, which comprises the following components: one separating unit of interlaced video scenes; one input unit of interlaced scene video signals, which electrically connects with the separating unit of interlaced video scenes, and provides one interlaced scene video signal to the separating unit of interlaced video scenes; in which, the interlaced scene video signal is integrated by one first scene video signal and one second scene video signal and interlaced combined by time; the separated unit of the interlaced video scenes is able to separate the interlaced scene video signals to the first video scene video signal and the second scene video signal.

Abstract: A digital television (DTV) receiver is provided, comprising: a demodulator that demodulates television signals and outputs equalizer training signals in the form of real (I) and imaginary (Q) data; a sync signal detector, and a phase compensator that offsets the phase of the I and Q data based on the phase offset signal and outputs phase adjusted I data under control of the lock control signal. The sync signal detector comprises: a correlator that correlates the equalizer training signals including the I and Q data; a power calculator that calculates the sum of the power of the correlated I and Q data; a comparator that compares (the sum) against a preset threshold and outputs a compare indication signal; a sync lock controller that monitors the compare indication signal and outputs a lock control signal; and a phase calculator that calculates a phase of the equalizer training signals based on the I and Q data and outputs a phase offset signal based on the compare indication signal.

Abstract: A display system comprising a video signal supplier supplying a video signal with a first video signal standard comprising a predetermined sync signal and a data range; a display apparatus supporting one of the first video signal standard and a second video signal standard comprising a sync signal and a data range which are at least being partially different to the first video signal standard and a data range being equal to the first video signal standard and outputting the video signal from the video signal supplier; a selector selecting the display apparatus supporting one of the first video signal standard and the second video signal standard; and a sync signal converter receiving a sync signal in the video signal from the video signal supplier according to a selection of the selector and converts the received sync signal into either the first video signal standard or the second video signal standard, which the selected display apparatus supports, to output the selected display apparatus.

Abstract: In order to reduce the circuit scale and the manufacturing cost by decreasing the amount of data to be stored, a synchronizing signal data generating circuit outputs, at each timing, relative synchronizing signal data showing the ratio of a synchronizing signal level to an amplitude level of the synchronizing signal, a multiplier multiplies synchronizing signal amplitude level data, a divider divides by the maximum value N of image signal data which can be outputted from the synchronizing signal data generating circuit, thereby the synchronizing signal data showing actual synchronizing signal level is provided, and an adder adds input image signal data thereto, whereby output image signal data, in which the synchronizing signal data is superposed on the input image signal data, is generated.

Abstract: A flat display device includes, vertical synchronization lock means which generates an internal vertical synchronization signal, a window signal generating circuit which generates a window signal by use of the internal vertical synchronization signal, a detecting circuit which detects whether or not an external vertical synchronization signal is present in a period of the window signal, and a determination circuit which determines whether a preset condition that a plurality of detection signals are present in a preset period is satisfied or not and controls an output inhibition circuit to inhibit a gate signal from being output when the preset condition is not satisfied.

Abstract: An imaging apparatus includes a camera device, a signal processor that receives a video signal from the camera, and a connection cable connecting the camera device and the signal processor. The camera device includes a first phase controller that compares the phase of a synchronization signal transmitted from the signal processor with the phase of an internal signal generated by the camera device, and that synchronizes the phase of the internal signal with the phase of the synchronization signal, a video synchronization signal generator that generates a video synchronization signal for the video signal based on the internal signal, and a signal transmitter that transmits the video signal. The signal processor includes a second phase controller that compares the phase of the video synchronization signal with the phase of the synchronization signal, and that synchronizes the phase of the video synchronization signal with the phase of the synchronization signal.

Abstract: In a sync processor for determining safety of signals on the basis of a horizontal/vertical sync signal generated according to a data enable signal, the sync processor includes a digital horizontal/vertical signal generator, a selector, a digital horizontal/vertical signal detector, a horizontal/vertical polarity determination unit, and a horizontal/vertical frequency determination unit. The digital horizontal/vertical signal generator generates a digital horizontal/vertical sync signal from the data enable signal. The digital horizontal/vertical signal detector detects a signal received from the selector and generates a digital horizontal/vertical signal. The horizontal/vertical polarity determination unit counts the number of low and high durations of a horizontal/vertical sync signal and generates a horizontal/vertical polarity signal in response.

Abstract: A data processing apparatus constituting a low-cost audio/video data transmission and reception system is disclosed. A reception buffer monitoring circuit 21 monitors the size of receiver data being accumulated in a reception buffer 6. When the size of accumulated data is found to become higher than a high threshold, the circuit 21 causes a reception clock generation circuit 8 to generate a reception clock with a higher frequency. When the accumulated data size becomes lower than a low threshold, the reception clock is generated with a lower frequency. Based on the reception clock fed from the reception clock generation circuit 8, an audio/video decoder 7 decodes the audio/video data coming from the reception buffer 6. This invention applies advantageously to a television transmission and reception system for transmitting and receiving TV broadcast signals.

Abstract: A video synchronization signal removal circuit in which a synchronization signal component of an incoming video signal is detected whereupon a reference signal corresponding to a black video level is substituted substantially during the synchronization signal interval.

Abstract: A method for synchronizing the recordings of two video cameras which are operated in parallel for the three-dimensional representation of an image sequence includes fading a light signal into the image area of the two cameras and simultaneously recording the light signal by both cameras. Playback of the recordings are synchronized using the recorded signals. The two video cameras may be two digitally recording video recorders.

Abstract: The clocks of one or more edgeQAM devices are synchronized with a master clock at the remotely located CMTS. A master clock signal may be transmitted via a dedicated gigabit Ethernet link. Alternatively, master clock information contained in a time synchronization message may be transmitted for use in adjusting local oscillators that drive local clocks at respective edgeQAM devices. In another embodiment, the downstream sample rate to particular edgeQAM devices may be sampled and used to lock a local clock at respective canary modems dedicated to each edgeQAM device. A canary modem's clock is compared to the master clock, and a resulting phase error is communicated to the respective edgeQAM device for use in adjusting its local clock. Or, TDMA upstream ranging burst average trends are used to estimate edgeQAM clock error. Each respective edgeQAM uses this error to adjust its clock.

Abstract: Systems, methods, and/or techniques (“tools”) for optimizing execution of high-definition digital versatile disk (HD-DVD) timing markup are described herein. The tools may receive timing markup read from an HD-DVD disk, and optimize the processing of the timing markup using one or more of the optimization strategies described herein.

Abstract: This invention is a method and apparatus for identifying and separating the synchronizing signal component of video like signals by identifying or detecting the arrangement or sequence of the known occurances of events or patterns of the sync. The invention also provides for establishing data slicing references in response to the levels of known portions of the sync component.

Abstract: The present invention provides a synchronizing signal separation. In accordance with the present invention, a sync pulse processing circuitry slices a video signal and senses the peaks of the synchronizing pulse. A reference generating circuitry divides the output from the sync pulse processing circuitry into a plurality of reference signals that are compared with the video signal, thereby producing logic level outputs. A sync restoring circuitry combines the logic level outputs to provide precisely reconstructed synchronizing pulses of the video signal. The present invention incorporates different standard functions with superior performance because it may be applied for different types of video signals.