Abstract: A method and apparatus for converting a digital video signal, to a signal having a resolution that matches a display device, by using simple hardware alone. When a digital video signal is input together with a data enable (DE) signal and a dot clock (DCLK) signal, the number of clocks of the DCLK signal generated during an active period of the DE signal is counted and, based on the thus counted number of clocks, the resolution of the input video image is identified; then, based on the resolution thus identified, the pixel density of the input video signal is converted so as to form a video signal having a resolution that matches the display device. Alternatively, the resolution of the input video signal may be identified by counting the number of pulses of the DE signal generated during one vertical synchronization period.

Abstract: A circuit for generating video synchronization timing signals includes a negative peak detector (FIG. 5) for following variations of a composite video signal (FIG. 1), rather than clamping the most negative voltage of the composite video signal. The negative peak detector provides a voltage level VTIP representative of the voltage at the synchronization tip of the composite video signal. A sample and hold circuit (700, 702, 704) is used to add an offset VSLICE to VTIP, VSLICE being a voltage level of the breezeway, color burst, or back porch segments of the composite video signal, or a combination of these segments. The sample and hold circuit generates a signal VREF, and is connected by a resistor divider (708,710) to the negative peak detector to form the signal VTIP+VSLICE provided to an amplifier (606) functioning as a comparator. The signal VSLICE+VTIP is compared in comparator (606) with the composite video signal to provide an overall circuit output.

Abstract: A method and apparatus for distributing time and frequency information to a plurality of studios such that the studios can then use the time and frequency information frequency and timelock their studio components to the global reference. The apparatus includes various embodiments for facilitating the distribution of time and frequency depending upon the type of digital network that is used for distributing the television signals.

Abstract: An apparatus and method for processing a synchronizing signal of a monitor is disclosed, in which an abnormal synchronizing signal is detected to avoid poor picture quality and any error in proceeding to a DPM mode. The apparatus for processing a synchronizing signal of a monitor includes a synchronizing signal processor for separating a synchronizing signal from SOG signal, a detector for detecting a synchronizing signal width and a horizontal line width output from the synchronizing signal processor, a microcomputer for determining abnormality of the synchronizing signal using relative ratio of the detected synchronizing signal width and horizontal line width, and a clock generator for generating a clock in accordance with a control signal of the microcomputer and outputting the clock to the detector.

Abstract: An ITU-R BT.656 (or similar) digital video signal is converted to analog at which point a simple 7-state state machine in combination with a 6 bit binary counter generates tri-level synchronized video. The state machine receives vertical and horizontal synchronization signals as well as End-Active-Video and Start-Active-Video signals from the ITU-R BT.656 video. A pixel clock clocks the 6 bit binary counter. Active video is passed directly to the output. Horizontal and vertical sync signals are mirrored at the output with the state machine generating a positive tri-level signal immediately following the horizontal synchronization signal. The high level signal is generated for a period of 44 pixel counts as counted by the 6 bit counter.

Abstract: A device and method for processing a sub-picture in a TV receiver is disclosed. The present invention allows a viewer to freely move the position of a sub-picture in both left⇄right and top⇄bottom directions, such that even a portion of the sub-picture may be displayed on the screen.

Abstract: A method and/or apparatus is capable of performing high accuracy digital level restoration with a high degree of noise immunity provided by a passive clamping stage.

Abstract: The invention provides a clock frequency generator for the use of converting the format of the video signal, which generates a clock of an unified frequency, in order to obtain the horizontal and the vertical synchronizing signals for the video signal after the format conversion without changing the field frequency and the scanning lines of the standard video signal. By using the clock generated by multiplying by a factor of 4740 the horizontal synchronizing signal for the SD format interlace scanning signal in the first multiplier (0009) and the second multiplier (0003), the horizontal synchronizing signal for the HD format interlace scanning signal is generated from the output terminal (0007) and the vertical synchronizing signal for the HD format interlace scanning signal is generated from the output terminal (0008) without changing the standard number of the scanning lines and the field frequency.

Abstract: An apparatus and method for detecting a vertical synchronizing signal in a digital TV receiver using a VSB system is disclosed. The present invention includes a vertical obtaining the correlation between a received signal and a previously set vertical synchronizing signal, detecting the position of a symbol having a maximum correlation in every field to output the detected position, and checking the reliability of the output of the maximum value position detector.

Abstract: Disclosed is a system for inserting indicators, such as tags and markers, in a video stream. The tags and markers can be inserted automatically using a database, or manually using an operator input station that supplies standard tags and markers for easy insertion. The information can be accessed with the database functioning as a look-up table, or using a comparator that compares a time code with stored table information. Also disclosed is the generation of supplemental video signals that can be combined with a video signal to provide supplemental information that varies on a regional basis. The present invention also discloses the use of indicators to access Internet web sites to generate enhanced video signals. The indicators can be transmitted by embedding them in the streaming video, in the video blanking interval, encoding them as a separate data PID or placing them on a back channel.

Abstract: In transmitting ten-bit word string data including synchronous word data converted, at a transmitting side, from eight-bit word string data, representing signal information data synchronization required for reproducing the signal information is reliably established at a receiving side. An additional word data group containing eight-bit synchronous word data is inserted between words of the eight-bit word string data. Then, 8B-10B conversion is performed on the eight-bit word string data, thereby obtaining ten-bit word string data. In this case, the additional word data group is selected so that a running disparity of the ten-bit synchronous word data contained in the additional word data group of the composite ten-bit synchronous word data is consistently positive or negative.

Abstract: The signal processing apparatus for setting a vertical blanking signal of the television set that allows to set the beginning position and end position of a horizontal blanking signal irrespective of the numbers of lines in the vertical synchronous signal interval, comprising: an up counter for counting the vertical synchronous signal interval, synchronizing with the horizontal synchronous signal to lock forcedly the interlace signal to become a non-interlace signal; and a down counter for loading and down counting the count value of the up counter, wherein the down counter loads the data of the up counter immediately before the up counter is reset at a timing of the vertical synchronous signal and down counts the data which is loaded in the down counter as the initial value.

Abstract: System and method for processing HDTV format video signals have been disclosed. A disclosed embodiment comprises a HDTV timing generator having as inputs a vertical sync and a horizontal sync. The HDTV timing generator outputs a digital HD level signal. The disclosed embodiment further comprises a DAC interface. The DAC interface can include an encoder channel, or more than one encoder channel. The encoder channel can receive a digital HD level signal, a SCART level signal, an NTSC level signal, a PAL level signal, and a SECAM level signal. The encoder channel can further receive a HDTV format data input, a SCART format data input, an NTSC format data input, a PAL format data input, and a SECAM format data input. The output of the DAC interface can be coupled to a DAC which in turn generates an output suitable for display on a monitor.

Abstract: A vertical synchronization separation circuit eliminates distortion in a television picture produced when the synchronization signal is complex and includes a copy guard signal.

Abstract: A sync signal generator circuit comprises a first counter which is reset each time it detects a reference edge of the input sync signal, a first register for holding a first value immediately before the first counter is reset, a reset signal generator for generating reset pulses, a second counter which is reset each time it receives a reset pulse, a second register for holding a second value immediately before the second counter is reset, and a sync pulse generator for generating an output sync signal on the basis of the reset pulses. The reset pulse is generated each time the counted value of the second counter matches a predetermined value or each time the first counter detects the reference edge while an absolute value of a difference between the counted value of the second counter and the second value held in the second register is not greater than a permissible value of period fluctuations.

Abstract: A timing data table in which timing data is registered for respective types of video signals defined by frequency and polarity of a respective synchronizing signal is provided in a nonvolatile memory. A main control part retrieves the timing data table with the type of the video signal as a retrieval key to acquire pertinent timing data, and, using this timing data, necessary adjustment parameters (that is, horizontal position adjustment parameter, horizontal size adjustment parameter, vertical position adjustment parameter and vertical size adjustment parameter) are calculated by operations and outputted to a horizontal deflection control circuit and to a vertical deflection control circuit. Thereby, a video display apparatus and a video display method capable of reducing time required to make adjustments and performing correct and highly responsive video display regardless of the types of video signals are provided.

Abstract: A first counter counts a first clock signal repeatedly in accordance with an external synchronous signal. A second counter counts a second clock signal repeatedly in every predetermined cycle, and generates an internal synchronous signal having the predetermined cycle. A controller adjusts the cycle of counting performed by the second counter by controlling the second counter. By doing so, the controller controls the internal synchronous signal to synchronize with the external synchronous signal in each horizontal period.

Abstract: A special synchronization frame generator is used for creating simultaneous easily visible synchronization markers as part of a multi-channel image generating system. It does not rely upon any external objects or markers being simultaneously present in the field of view of several cameras in a multi-camera system, or upon a separate synchonization signal being recorded simultaneously along with the image information, or upon any post-processing of the recorded image to add synchronization markings common to the various channels of the system. The generation of synchronization frames can be applied to either multichannel video or film systems.

Abstract: A coded signal synchronizing device includes a first and a second signal synchronizing circuit. The first and second signal synchronizing circuits respectively feed a first and a second coded signal to a coded signal processor while synchronizing them to each other in accordance with a reference synchronizing signal. A synchronization control circuit compares the phases of frame synchronizing signals output by the decoding of the coded signals and the phase of the reference synchronizing signal. So long as a phase difference between either one of the frame synchronizing signals and the reference synchronizing signal lies in a preselected range, the synchronization control circuit reads the coded signal sequentially stored. If the phase difference is smaller than a first preselected value, the synchronization control circuit repeatedly reads an I (Intra-coded) picture two times.

Abstract: A receiver for processing a VSB modulated signal containing terrestrial broadcast high definition television information and a pilot component includes a carrier recovery network (22; FIG. 3) that produces a demodulated baseband signal. The carrier recovery network additionally responds to a locally generated control signal (Ph. Offset; 360) representing an unwanted phase offset of the pilot signal due to multipath distortion, for example. The control signal is used to compensate for the pilot phase offset before the demodulated signal is equalized. The control signal is produced by correlating received sync values with both a reference sync value (362) and a Hilbert transform of the reference sync value (363). The output of the carrier recovery network signal is phase compensated twice.

Abstract: A sync signal generating apparatus and method for video signal processor are disclosed comprising an image processor processing either an input digital television video signal or an input analog television video signal to display one of the signals; a display unit displaying an output signal of the image processor; a frame rate detector detecting a frame of the digital video signal and generating a frame rate signal; a display mode detector detecting whether an image to be currently displayed is a digital television image or an analog television image and generating a display mode signal; a clock generator generating a clock signal according to the display mode signal and the format signal to the image processor; a sync signal compensation unit generating a sync compensation signal based upon the display mode signal, the clock signal, and a vsync signal of the analog television video signal; and a sync signal generator resetting and compensating a sync signal based upon the sync compensation signal and the cl

Abstract: A method for obtaining line synchronization information items from a video signal is proposed. To that end, the following improvement measures are proposed: a) an accurate determination of the position of a line synchronization pulse is effected by carrying out a convolution operation between the video signal for the video line and a pattern function. The exact position is then established by analysis of the result function (&phgr;sv(k)) of the convolution operation. B) time-domain filtering of the established positions of the line synchronization pulses is carried out, in which a linear or non-linear estimation for the purpose of determining the corrected positions of the line synchronization pulses is carried out in each case. The invention also relates to an apparatus for carrying out the method.

Abstract: A synchronization pulse detector for detecting a synchronization pulse within an input signal. The input signal has “level” portions (i.e., substantially non-time varying portions) and “transition” portions (i.e., substantially time varying portions). The pulse detector includes a pulse shape detector for determining each time the input signal has a sequence of a first “level” portion, followed by a first “transition” portion, followed by a second “level” portion, followed by a second “transition” portion followed by a third “level” portion, one of the first and second “transition” portions being positive and the other one of the first and second “transition” portions being negative. Each time such sequence is determined a pulse_shape detected pulse is produced. An evaluator is provided to reject invalid pulse_shape detected pulses.

Abstract: A level is preset into a counter. The level held in the counter is compared with the minimum value of the present video signal by a level detecting circuit. When the minimum value of the present video signal is lower than the level of the counter, the intermediate value between the value of the counter so far and the minimum value of the present video signal is obtained by an intermediate value calculating circuit, thereby presetting the counter and updating the level. Thus, the value of the counter gradually approaches a sync chip level. The video signal is sliced by a slice level formed on the basis of the value of the counter by a slice circuit, thereby extracting the sync signal. Further, in a mask signal generating circuit, the updating of the level is inhibited for a predetermined time after the updating of the level was performed for a predetermined period of time, thereby preventing the level from being influenced by the noise for the video period.

Abstract: An apparatus comprises a source of a first signal synchronized to deflection, the first signal including a first portion representative of a retrace interval, means coupled to a first video signal and responsive to a second signal representative of the retrace interval for generating a second video signal having a blanking interval, and, means responsive to a third signal representative of the blanking interval and to the first signal for generating the second signal so as to control the phase of the blanking interval relative to the retrace interval.

Abstract: A video signal processing apparatus comprising an oscillating unit for outputting a signal of a stable frequency, a counting unit for counting the period of a cycle of a signal supplied from the outside based on the signal output by the oscillating unit, a clock number calculating unit for calculating the number of clocks in a line based on a result of counting by the counting unit, a comparing unit for comparing the number of clocks calculated by the clock number calculating unit with a threshold to decide which is larger, a switching unit for deciding the number of clocks in the next operation by switching to the number of clocks calculated by the clock number calculating unit if the calculated number of clocks is larger than the threshold, or deciding the number of clocks in the next operation by holding the number of clocks in a line in the current operation as it is, and a synchronizing signal generating unit for, based on the number of clocks in operation decided by the switching unit and the signal out

Abstract: A clock generation circuit for use in a television system displaying images encoded in television signals and images represented by network application data. The clock generation circuit generates a clock signal synchronized with HSYNC signals of the television signals. The clock generation circuit includes a phase-lock-loop (PLL) circuit and a tracking block. PLL circuit includes an oscillator (e.g., VCO) driven by an error signal to generate an internal periodic signal having frequency substantially equal to the frequency of the desired clock signal. The tracking block includes a resettable VCO (RVCO) driven by the error signal. A restart signal is asserted prior to the expected arrival time of the HSYNC edge to cause the RVCO to stop generating the desired clock signal. The restart signal is deasserted on receiving the HSYNC edge to cause the RVCO to start generating the clock signal. Accordingly, the clock signal is synchronized with the HSYNC signal.

Abstract: This invention provides a method of generating multiple frequencies for use in a digital data transmission system including a remote transmitter and receiver. The reference frequency used in the transmitter is replicated in a remote receiver. A single crystal oscillator is used to generate a reference frequency similar to that used in the transmitter. The receiver reference frequency is manipulated by dividing the frequency into required multiple frequencies for use within the receiver. A constant comparison is made between the clock signal received in the transmitted data stream with the receiver reference frequency and the divisors are adjusted accordingly to maintain the clock frequency in the receiver within a predetermined tolerance range. This allows the output signal for display from the receiver to match the quality of the input display provided to the transmitter.

Abstract: The present invention relates to processing of a video signal in a computer display and the like, and aims at providing a synchronizing signal generator which can obtain a vertical synchronizing pulse whose phase is stable with respect to the horizontal synchronizing signal and in which a counter for counting a clock synchronized with the horizontal synchronizing signal has a small counted value. It comprises a counter (8R) for detecting the vertical synchronization period (N) on the basis of the horizontal synchronizing signal (Hsync) and an output switching unit (14) which outputs a vertical synchronizing pulse (Vd) synchronized with the vertical synchronizing signal (Vsync) when the input vertical synchronizing signal (Vsync) has a vertical synchronization period of a given range, and which selects and outputs a pulse (Sq) having a given vertical synchronization period when the input vertical synchronizing signal does not have a vertical synchronization period of the given range.

Abstract: A horizontal sync separator that is capable of operating with horizontal sync signals of differing durations. A monostable is operated by the leading inverted negative edge of the horizontal sync pulse and generates a minimum duration horizontal pulse. The minimum duration horizontal pulse is applied along with the inverted negative horizontal pulse to an OR gate which outputs the longer of the two pulses. The arrangement assures proper video clamping during the horizontal back porch interval.

Abstract: A field decision unit capable of solving a problem involved in a conventional field decision unit in that an internal synchronizing signal can be erroneously synchronized with the equalizing pulses of a video signal owing to noise because the output halt period of a phase comparator is set rather short considering that this will facilitate the synchronization of the internal synchronizing signal with the video signal when starting the system or the like, and hence an incorrect field decision can be made. The present field decision unit includes an output controller which sets output halt pulses with a longer output halt period in a particular interval consisting of the synchronizing cycles containing the equalizing pulses and a synchronizing cycle previous thereto, and which employs output halt pulses with a shorter output halt period outside the particular interval as in the conventional system.

Abstract: In a horizontal scanning pulse control circuit, a reference clock generation circuit generates a reference clock signal in synchronization with a horizontal synchronization signal. First and second horizontal position reference pulse generation circuits generates first and second horizontal position reference pulse signals, respectively, whose phases are different with reference to the horizontal synchronization signal and corresponding to first and second pulses of said reference clock signal. First and second saw-tooth wave generation circuits generate first and second saw-tooth wave signals in response to the first and second horizontal position reference signals, respectively. First and second comparators, compare the first and second saw-tooth wave signals with a horizontal position selection voltage to generate first and second comparison signals, respectively. An RS-type flip-flop is set and reset by the first and second comparison signals, respectively.

Abstract: A method and an apparatus for control a timing in a flat panel display system are disclosed. In an alternating current plasma display system for respectively driving a plurality of subfields at every field in three steps such as a) entering and for eliminating a whole pixel for a first predetermined time, b) entering data for a second predetermined time and c) maintaining a discharge at every subfield for times which are different from one another, a first clock generator generates a first clock signal having a high frequency. A second clock generator generates a second clock signal having a low frequency. A first counter counts the second clock signal in response to a vertical synchronizing signal, and generates both a first pulse signal which sets the first and second predetermined times respectively in steps a) and b) in the respective subfield sections and a second pulse signal which sets times in step c) in the respective subfield sections which are different from one another.

Abstract: The invention presents a method of frame synchronization of Digital Video Broadcasting (DVB) data using a temporary storage area (regfile) of substantially smaller dimension than the repetition rate of the sync pattern. Synchronization is achieved by detecting the sync pattern by correlation and determining if the pattern has a fixed repetitive separation. The synchronization scheme of the invention is simple and easily implementable as an integrated circuit, using software and a microprocessor, or as discrete circuitry.

Abstract: A sync signal generator with a signal discriminator comprising an input terminal supplied with a fist signal or a second signal of a higher frequency; a clock signal generating circuit; a first counter reset by the first or second signal received from an input terminal, and caused to halt counting the clock signal when the count thereof has reached a predetermined value MC4; a first detector for outputting a detection signal relative to the first or second signal during the counting action of the first counter; a second counter reset when the count of the first counter has reached a predetermined value MC1, and caused to halt counting the clock signal when the count of the first counter has reached a predetermined value MC2 (MC2<MC4), and to output a detection signal (SMAX) when the count thereof has reached another predetermined value SC1 (SC1<MC2); a second detector for outputting a detection signal relative to the second signal in response to the detection signal (SMAX) from the second counter; and a

Abstract: A system and method for distribution of a clock signal of a new timing reference which may employ an existing NTSC distribution network present in a conventional NTSC studio. NTSC-compliant horizontal, vertical, or other composite synchronization signals are generated from an HDTV primary reference clock, and are synchronized and locked to the HDTV primary reference, for distribution over the existing NTSC distribution network. HDTV studio components receive the horizontal, vertical, or other composite synchronization signals and generate a local HDTV clock signal using a phase-locked loop frequency synthesizer. The signal generated by the phase-locked loop frequency synthesizer is synchronized and locked to the HDTV primary reference.

Abstract: A sync signal processing device for a combined video appliance capable of directly processing a personal computer (PC) signal through a television (TV) receiver circuit to achieve the horizontal and vertical driving and deflection. The device can prevent the vertical trembling phenomena of the displayed picture and on-screen display by compensating for the sync frequency difference between the PC signal and the TV signal. According to the devices either a TV sync signal or a PC sync signal is selected in accordance with a selected TV/PC mode after the PC sync signal is frequency-converted and the selected PC sync signal is processed through the TV sync signal processing circuit. Either the horizontal driving pulse signal form the TV sync signal processing circuit or the horizontal driving pulse signal produced from a separate horizontal oscillation circuit is selected and outputted to a horizontal output circuit in accordance with the selected TV/PC mode.

Abstract: A current source and threshold voltage generation circuit generates a current, through a ratio of devices, and a corresponding threshold voltage signal, to be utilized by a timing circuit for generating a timing ramp and determining when the timing ramp crosses the threshold voltage signal. The current is generated through a current generation circuit, using a ratio of matched devices. Preferably, the matched devices are transistors. The current is then utilized by a timing circuit to charge a charge storage device to a level above the level of the threshold voltage signal. The current is also mirrored, appropriately increased and used to generate the threshold voltage signal which is compared to the charge stored on the charge storage device. Accordingly, any errors in the generation of the current are also reflected in the level of the threshold voltage signal, thereby eliminating the potential for errors in the timing ramp signal generated by the timing circuit.

Abstract: A current source and threshold voltage generation circuit generates a current, through a ratio of devices, and a corresponding threshold voltage signal, to be utilized by a timing circuit for generating a timing ramp and determining when the timing ramp crosses the threshold voltage signal. The current is generated through a current generation circuit, using a ratio of matched devices. Preferably, the matched devices are transistors. The current is then utilized by a timing circuit to charge a charge storage device to a level above the level of the threshold voltage signal. The current is also mirrored, appropriately increased and used to generate the threshold voltage signal which is compared to the charge stored on the charge storage device. Accordingly, any errors in the generation of the current are also reflected in the level of the threshold voltage signal, thereby eliminating the potential for errors in the timing ramp signal generated by the timing circuit.

Abstract: The invention features the generation of timing signals for use in the generation of a video signal. Vertical timing codes and horizontal timing codes are stored in a memory. The horizontal timing codes define regions of at least two types of horizontal timing signals of the video signal, and the vertical timing codes define the timing of the horizontal timing signals. The vertical and horizontal timing codes are stepped through to generate at least one signal indicative of the timing of the horizontal timing signals.

Abstract: A control circuit (100) which receives horizontal synchronising pulses (265) and generates a horizontal drive output signal (455) for a cathode ray tube (CRT) display. The horizontal control circuit (100) generates two ramp signals. A first ramp signal (410) for horizontal position adjustment of an image on the CRT display, and a second ramp signal (440) for propagation delay compensation of a deflection circuit (155) coupled to the CRT display. The control circuit (100) also provides digital of control of the duty cycle of the horizontal drive signal (455).

Abstract: A horizontal synchronization pulse generation circuit generates a horizontal synchronization pulse to be added to an encoded composite video signal. An input receiving circuit receives an encoded input video signal representing video information received from input video signals. An output video signal represents the encoded input video signal in all portions of the signal except the horizontal synchronization period. During the horizontal synchronization period a current is switched through a path resistor and used to generate the voltage level of the horizontal synchronization pulse. The voltage drop across the path resistor during the horizontal synchronization period is applied directly to the output video signal thereby generating a horizontal synchronization pulse. The current switched through the path resistor is generated by a voltage drop across a current resistor.

Abstract: A phase locked loop for synchronizing decoding clocks with encoding clocks in a Moving Picture Experts Group (MPEG) system. The phase-locked loop circuit includes a voltage controlled oscillator for converting a decoding clock into an encoding clock, a register unit for storing multiplexing program clock reference signals, each input with a desired number of bits, a counter being initialized by a first program clock reference signal output from the register unit, thereby generating a local program clock reference signal, and a phase error control unit for combinationally operating the program clock reference signal stored in the register unit and the local program clock reference signal, thereby generating a phase error signal for controlling the voltage controlled oscillator.

Abstract: A video signal processor for use in a multi-color standard color video apparatus including a horizontal synchronizing signal generator and a baseband circuit provided on a same LSI chip as a video signal processor. The baseband circuit includes a switched capacitor filter having a switched capacitor array. A driving pulse generator for driving the switched capacitor filter is included on the same LSI chip and synchronizes to horizontal signals in a received video signal of a particular color-standard.

Abstract: A synchronizing signal generator produces a PAL standard horizontal synchronizing signal using a PAL standard subcarrier signal as a timing reference. The synchronizing signal period is not an even multiple of the subcarrier signal period. To produce the synchronizing (sync) signal, the generator first frequency multiplies and divides the input signal to produce a reference signal having a period that is a rational multiple of the subcarrier signal period but smaller than the desired sync signal period. The generator then delays each successive pulse of the reference signal by increasingly longer delay times to produce the sync signal.

Abstract: A circuit for detecting a data segment sync signal of data segment consisting of a plurality of symbols in a high-definition television, includes a correlator for detecting a correlation value from a received data segment signal, a segment integrator for accumulating the detected correlation value by segments and attenuating the accumulated correlation value in response to an overflow prevention signal, a maximum-value detector for detecting a maximum accumulated correlation value in the segment from the segment integrator output, an overflow prevention circuit for generating the overflow prevention signal by comparing the detected maximum accumulated correlation value with a predetermined reference value, a sync position detector for detecting a symbol position having the detected maximum accumulated correlation value, and a synchronization signal generator for generating a synchronization signal at the symbol position corresponding to the detected maximum accumulated correlation value.

Abstract: Sync separator and video detector circuits, including a sync tip clamp having symmetrical and non-symmetrical clamps. The symmetrical clamp clamps the input video signal to a reference voltage during composite sync pulses, so the coupling capacitor discharge current is kept small between composite sync pulses. For startup, the non-symmetrical clamp employs an operational amplifier, diode and controllable current source to charge the coupling capacitor to a minimum desired level, and to discharge the capacitor e.g. when there is a change in DC level so that the output level is too high. A sync slicing detector is also provided, using two comparators. One comparator compares the slicing level with the clamped video and produces a properly sliced composite sync output, while the other compares the clamped video with a small reference voltage and produces a fixed sync output.

Abstract: A horizontal synchronization signal generating circuit self-generates a horizontal synchronization signal if an actual horizontal synchronization signal fails to be detected in a composite video signal. Each time an edge-detection circuit detects an actual horizontal synchronization pulse, a counter and decoder are reset. An actual horizontal synchronization signal has a period of 63.5 .mu.s. If the edge detection circuit fails to detect the actual horizontal synchronization signal, then the decoder outputs a self-generated horizontal synchronization signal at 64 .mu.s and a selector circuit disables the edge detection circuit for approximately 35 .mu.s. In contrast, if the edge-detection circuit detects an actual horizontal synchronization signal, the decoder is reset before it can output the self-generated signal and the selector disables the edge detection circuit for approximately 60 .mu.s. Accordingly, a period of 35 .mu.

Abstract: An apparatus for detecting a field sync signal in a HDTV includes a sign bit selector for selecting only a sign bit from a received HDTV signal; a correlation portion for determining the correlation value of the selected sign bit and a predetermined reference signal; a detector for comparing the correlation value with a threshold value, to thereby determine a field sync timing signal; and a generator for generating a field sync signal which has a logic "HIGH" level during one field sync segment interval in response to the field sync timing signal. Here, only one MSB of input data is selected and then correlation with the reference signal is determined. Accordingly, a field sync signal which has a logic "HIGH" level during one field segment interval in each field can be accurately detected, and thus a hardware structure is simplified.

Abstract: A clamp pulse generating circuit comprising a synchronizing decision circuit for deciding whether an external synchronizing pulse is being input or not; an exclusive-OR circuit, a change-over switch and a pulse width detecting circuit for deciding whether a video signal containing a synchronizing pulse is being input or not; and a pulse generating circuit for generating a clamp pulse at the front or rear edge of the external synchronizing pulse output from a synchronizing separator circuit, and outputting the clamp pulse at the front edge selected by a selection switch when the external synchronizing pulse is being input and forcing to select and output the clamp pulse at the rear edge of the synchronizing pulse irrespective of the presence of the external synchronizing pulse when the video signal containing the synchronizing pulse is being input.