Abstract: The present invention relates to the domain of video equipment. It relates to a phase-locked loop able to recover the timing of a synchronization signal comprising a temporal discontinuity of amaximum amplitude equal to PCR_Modulus, the loop comprising: a sample comparator comparing the samples and the local samples of a synthesized signal, means for producing the synthesized signal from a corrected signal, a corrector receiving a comparison result delivered by the comparison means and delivering the corrected signal, According to the invention, the comparison means comprises the means to determine a difference in value between the local samples and the samples of the synchronization signal and in that the comparison result has a value that depends on the value ? and on the difference between the value ? and the value PCR_Modulus/2.

Abstract: A method and device regenerating a pixel clock signal, the method comprising, and the device being configured for: determining a first drift value D1 representative of a first time difference between a reference clock signal RC and a local clock signal LC based on a local pixel clock signal LPC; adjusting the local pixel clock signal LPC according to an adjustment command to provide a regenerated pixel clock signal RPC; determining a second drift value D2 representative of a second time difference between the reference clock signal RC and a regenerated clock signal based on the regenerated pixel clock signal RPC; and providing the adjustment command to the adjustable clock generator 32; 132; 316 for adjusting the local pixel clock signal LPC, wherein the adjustment command is based on the difference between the determined first and second drift values.

Abstract: Methods of generating a pixel clock signal for a multimedia source are provided in which a transmission clock signal having a first frequency is generated from a reference clock signal that has a second frequency. The generated transmission clock signal is multiplied by a multiple to generate the pixel clock signal. The pixel clock signal has a third frequency that is the product of the second frequency and the multiple.

Abstract: A method provides a bidirectional communication protocol for data communication between a first device and a second device. The method includes: during a first time interval, transmitting data from the first device to the second device; and during a second time interval, (a) after the occurrence of a first event, (i) suspending data transmission from the first device to the second device; and (ii) transmitting control data from the second device to the first device; and (b) after the occurrence of a second event, transmitting control data from the first device to the second device.

Abstract: An image-clock adjusting circuit is provided and includes a phase comparator, a clock controller, and a timing generator. The phase comparator receives a power source signal and a vertical synchronous signal and compares a phase of the power source signal with that of the first vertical synchronous signal for producing at least a phase comparison signal. The clock controller receives the phase comparison signal and the vertical synchronous signal, produces a pixel clock signal and intermittently adjusts a clock width of the pixel clock signal. The timing generator receives the pixel clock signal and adjusts the vertical synchronous signal into an adjusted vertical synchronous signal being nearly in phase with the power source signal. Therefore, The effect suppressing the phenomenon of the color rolling with the simpler circuit is accomplished.

Abstract: In one disclosed embodiment, the present test structure for determining gate-to-body current in a floating body FET includes a floating body FET situated over a semiconductor layer, where the floating body FET includes a first gate and first and second source/drain regions. The floating body test structure further includes a second gate and a first contact situated over the first source/drain region. A gate-to-channel current measured between the second gate and the first contact is utilized to determine the gate-to-body tunneling current. The gate-to-body tunneling current can be determined by subtracting the gate-to-channel current from twice a source/drain current of the floating body FET. The test structure may also include a second contact situated on a doped region in the semiconductor layer, where a diode current flow through the doped region determines a body voltage for the floating body FET.

Abstract: A method, and apparatus, and logic encoded in one or more computer-readable media to carry out a method. The method is to sample analog video at a sample clock rate and at a phase selected from a set of phases based on a quality measure determined from the sampled video. The quality measure is based on statistics of pixel to pixel differences in a coordinate of the generated digital video that have a magnitude exceeding a pre-determined threshold.

Abstract: A receiver for receiving signals in a plurality of transmission schemes, reducing the circuit size thereof successfully. The receiver for receiving a baseband signal and a modulated signal, includes a first PLL circuit configured to generate a first internal clock based on an external clock synchronized with the baseband signal; a demodulator configured to demodulate the modulated signal to output the demodulated signal; a selector configured to select one of the baseband signal or the demodulated signal; and a first CDR circuit configured to generate a recovered clock and recovered data from the signal selected by the selector, by using the first internal clock.

Abstract: Disclosed is a scaling process system including a replay apparatus and a video output apparatus which are connected via a HDMI, wherein each of the video output apparatus and the replay apparatus respectively comprises a between-pixel interpolation method table, wherein the video output apparatus including a request signal transmission device to transmit a request signal, a between-pixel interpolation method information receiving device to receive the between-pixel interpolation method information, a determining device to determine which of between-pixel interpolation method information of the replay apparatus or between-pixel interpolation method information of the video output apparatus is more high-performance, a deciding device to decide an apparatus to be used for the scaling process, and a control device to control the apparatus which is decided by the deciding device so as to carry out the scaling process, and wherein the replay apparatus including a request signal receiving device to receive the reque

Abstract: A method and system for supplying a digital video signal from a source to a sink are described. The digital video signal includes digital video data for three different colours and a pixel clock signal, such as DVI and HDMI. The digital video data and the pixel clock signal are received at a transmitter which sends a signal representative of the frequency of the pixel clock signal over a cable connecting the transmitter and a receiver. Digital video data for three different colours is sent over three different twisted wire pairs of the cable to the receiver. A local pixel clock signal is generated at the receiver using the signal representative of the frequency of the pixel clock signal. The local pixel clock signal is used to process the received digital video data and recovered digital video data and the local pixel clock signal are output.

Abstract: An asynchronous timing detector 3 detects and measures a specific pattern (sync pattern) of audio and video reproduced signals having a digital value form an A/D converter 2 and its appearance interval based on an asynchronous clock generated by an asynchronous clock generator 4, and calculates a cycle ratio of the measured sync pattern appearance interval (the number of clock pulses of the asynchronous clock) to a normal value (the number of clock pulses of a synchronous clock obtained by measuring a sync pattern appearance interval using the synchronous clock). A pseudo-synchronous clock generator 7 thins the asynchronous clock based on the cycle ratio to generate a pseudo-synchronous clock which is pseudo-synchronous with channel data. Therefore, even when an initial frequency error is large, frequency and phase pull-in is relatively quickly performed until a timing recovery operation becomes stable.

Abstract: A method of sampling phase calibration and a device thereof is suitable for an analog-to-digital converter and phase lock loop (ADC-PLL). The ADC-PLL conducts sampling on a periodic analog signal according to a sampling phase so as to produce a plurality of digital signals. The sampling phase calibration device includes a storage unit, a motion-detecting unit and a control unit. The motion-detecting unit is to calculate the number of motion data corresponding to a sampling phase. The control unit is coupled to the motion-detecting unit for changing the sampling phase so as to obtain the number of motion data corresponding to each sampling phase and selecting the sampling phase corresponding to the minimum number of motion data as an optimal sampling phase. The ADC-PLL can correctly sample an analog signal by using the optimal sampling phase and reduce the influence of clock jitter to the minimum.

Abstract: A signal transmission system includes a transmitting device and a receiving device. The transmitting device includes a superimposition portion that superimposes at least one synchronizing signal on at least one video signal among a plurality of video signals, and outputs the synchronizing signal and the video signal as a superimposition signal to a receiving device. The receiving device includes a separation portion that separates the superimposition signal into the synchronizing signal and the video signal, a first adjustment portion that adjusts an amount of delay of the separated video signal to another video signal, and a second adjustment portion that adjusts an amount of delay of the separated synchronizing signal.

Abstract: Provided is a video signal processing device capable of judging the viability of phase locking at a PLL circuit and, in accordance with the judgment, automatically switching between the PLL circuit and a DLL circuit to use to generate a sampling clock of an input analog video signal, the device including an AD converter for AD converting an analog video signal, and a clock signal generating circuit for supplying a clock signal to the AD converter. The clock signal generating circuit includes: a PLL circuit for generating a first clock signal on the basis of a horizontal synchronous signal acquired from the analog video signal; a DLL circuit for generating a second clock signal on the basis of a composite synchronous signal acquired from the analog video signal; and a clock selecting portion for selecting and outputting either the first clock signal or the second clock signal on the basis of output of a PLL-dedicated phase comparator.

Abstract: A method for deformable registration of 2 digital images includes providing a pair of digital images, including a fixed image and a moving image, extracting a set of edge images from each image of the pair of images, each edge set being extracted at a different resolution, selecting a pair of edge images with a lowest resolution, determining a mapping from edge points of the fixed image to edge points of moving image using a geodesic thin plate spline interpolation, applying the mapping to a next higher resolution edge point image of the moving image, selecting a pair of edge images at a next higher resolution, where a moving edge image is the moving edge image to which the mapping has been applied, repeating the steps at a next higher resolution for all edge images in the set of edge images, and applying the mapping to an entire moving image.

Abstract: Provided herein is a method for synchronizing audio and video clock signals in a system. The method includes comparing, within a comparison module, a system video signal with the determined mathematical relationship to produce an adjustment signal. A system video reference signal is updated with the adjustment signal to produce an updated intermediate signal.

Abstract: A method for generating an audio clock includes: receiving a reference clock; receiving a received signal from a multimedia interface of a receiver, wherein the received signal comprises a video signal and an audio signal; utilizing one of the reference clock and a video clock of the video signal to count the other of the reference clock and the video clock and determining a ratio signal; and generating an output clock according to the ratio signal and the reference clock.

Abstract: A receiver for use in a system for transmission from a transmitter to a receiver, the receiver includes a first frequency divider for outputting a first signal by dividing a signal with a frequency corresponding to a pixel clock or an integral multiple thereof by a reciprocal of an integral multiple of a first natural number, the integral multiple of the first natural number being greater than or equal to 1; and a cycle control portion for outputting a second signal having first and second cycles included within a cycle of the first signal by controlling a cycle of the pixel clock.

Abstract: A digital image converting apparatus with auto-correcting phase and a method thereof are provided. The digital image converting apparatus includes a phase controller, a delay locked loop (DLL), an analog-to-digital converter (ADC) and a position adjuster. The phase controller selects one of preset phases for outputting and continuously changes the output preset phase for controlling a clock signal produced by the delay locked loop. The ADC converts an analog display frame according to the adjusted clock signal. After all the preset phases are output in sequence, the phase controller can obtain an optimal phase for converting the display frame according to the smallest front porch of horizontal scan line and the smallest back porch of horizontal scan line of a digital display frame produced by the position adjuster.

Abstract: A frequency adjusting method comprises steps of: generating a first adjusting signal according to a frequency of a first output signal; adjusting a frequency of an input signal by using the first adjusting signal to generate the first output signal, so as to adjust the frequency of the first output signal into a first range; generating a second adjusting signal according to a frequency of a second output signal; adjusting the frequency of the first output signal by using the second adjusting signal to generate the second output signal, so as to adjust the frequency of the second output signal into a second range; and adjusting the first adjusting signal and the second adjusting signal according to the second adjusting signal.

Abstract: A synchronizing signal control circuit includes: a phase detecting section configured to detect a phase difference between a display synchronizing signal and an input synchronizing signal; an adding section configured to add a set value for setting a synchronization compensation period and the detected phase difference; a synchronization phase correcting section configured to correct the phase of the input synchronizing signal on the basis of the output signal of the adding section; a gate signal generating section configured to generate a gate signal representing the synchronization compensation period based on the display synchronizing signal; a synchronization determining section configured to determine whether the synchronization can be effected, by detecting whether the input synchronizing signal exists within the synchronization compensation period; and a selecting section configured to perform switching to the corrected input synchronizing signal on the basis of the determination result of the synchron

Abstract: A method of generating a spread spectrum clock signal for a line imaging device including receiving a line length value of the line imaging device, receiving a first clock signal indicative of a system timing signal in the line imaging device, generating a spreading waveform having a frequency as a function of the line length value and having a total number of clock cycles matching the line length value, and modulating the first clock signal using said spreading waveform to generate the spread spectrum clock signal where the spread spectrum clock signal is used for driving the imaging, data sampling and digitizing, and data transfer operation of the line imaging device. The spread spectrum clock has the same clock frequency variation for each scan line of the line imaging device.

Abstract: A method for stabilizing delay during conversion between Standard Definition (SD) video and High Definition (HD) video includes the step of establishing an integer divide ratio (M/N) corresponding to a ratio of clock rates with the output and input formats. The output clock rate is generated from the input clock rate by a Phase Lock Loop (104) using the M/N divide ratio to provide a known phase relationship between the two clocks rates at a repetitive interval. The video frame can be transferred at the known repetitive interval to provide coarse control over the input-to-output video delay. A separate fine tuning control (delay block) is provided to enable any programmable delay in video throughput to be accommodated to an accuracy of ±0.5 output pixel periods.

Abstract: A phase for an analog-to-digital converter sampling clock is determined. The analog-to-digital converter samples a video signal to generate pixel values. Differences of successive pixel values are compared to a threshold. The number of times the threshold is exceeded is counted for multiple phase values to create a phase profile. The threshold may be dynamic.

Abstract: A method of operating a line imaging device including receiving a first clock signal indicative of a system timing signal in the line imaging device, generating a second clock signal based on the first clock signal and being unmodulated where the second clock signal being used for driving the imager timing, data sampling and digitizing operations of the line imaging device, and generating a third clock signal based on the first clock signal and being modulated using a spreading waveform where the third clock signal being a spread spectrum clock signal and being used to drive the data transfer operation of the line imaging device.

Abstract: The invention relates to systems and methods for calibrating an analogue video interface. Due to the lack of pixel clock signal (206) information in the video-handling unit, a sample clock signal (202) needs to be generated, which should correspond with the unknown pixel clock signal (206). The types of signals transmitted to the video-handling unit may correspond with strange display formats and no up-front information may be present. The present invention provides methods and systems for automatic calibration of an analogue video interface. These are based on obtaining an analogue video signal (208) that is based on a pixel clock signal (206), generating a sample clock signal (202) having a first frequency by means of a PLL feedback divider having a value, determining a phase-relation between the video signal (208) and the sample clock signal (202) and evaluating the phase-relation to determine if the correct sample clock signal (202) is generated.

Abstract: A method and apparatus for an analog-to-digital video signal converter. The converter is controlled by a clock with controllable frequency and phase for sampling an analog signal. A circuit corrects the clock frequency using a period of a columnar frame differences as a function of columnar location. The sampling clock frequency is changed by an amount dependent on the period of the columnar differences. A second measure of the difference between successive frames is computed for a sequence of clock phases. The frequency of the clock is verified using a characteristic of the second measure. The characteristic can be the ratio of the maximum to the minimum of the second measure over selected clock phases. Other characteristics can be used such as a difference of a maximum and a minimum measure.

Abstract: A method and system of automatically correcting a sampling clock in a digital video system are disclosed. Sampling clocks with different phases are generated and subjected in turn to analog-to-digital conversion (ADC). A difference of at least a pair of neighboring data out of the ADC with respect to each phase is determined. A maximum difference is determined, and the sampling clock with the phase corresponding to the maximum difference is thus generated.

Abstract: A circuit is used to process video signal from a video sensor. The video signal includes video content signal and synchronization signals. The circuit includes a status register, a data register, and a processor. The status register provides a sampling clock signal to the data register and the video sensor. The sampling clock signal is synchronized with the synchronization signals to sample the video signal. The status register stores the synchronization signals. The data register storing the video content signal. The processor is coupled to the status register and the data register. The processor reads the video content signal from the data register according to the synchronization signals in the status register.

Abstract: A method for recovering pixel clocks based on an iDP interface includes selecting a prime factor closest to VA or HA from prime factors of X, and selecting a value obtained by subtracting VA from the selected prime factor, as VB, in Mvid = ( HA + HB ) × ( VA + VB ) X , where HA indicates a horizontal active period, HB indicates a horizontal blank interval, VA indicates a vertical active period, and VB indicates a vertical blank interval, fixing the selected VB value, and selecting a total of HB within one frame period and the number of lanes under a condition that Mvid has an integer value, and recovering pixel clocks by multiplying a frequency of link symbol clocks of data received via the lanes by a multiplication of Mvid/48.

Abstract: A method of sampling phase calibration and a device thereof is suitable for an analog-to-digital converter and phase lock loop (ADC-PLL). The ADC-PLL conducts sampling on a periodic analog signal according to a sampling phase so as to produce a plurality of digital signals. The sampling phase calibration device includes a storage unit, a motion-detecting unit and a control unit. The motion-detecting unit is to calculate the number of motion data corresponding to a sampling phase. The control unit is coupled to the motion-detecting unit for changing the sampling phase so as to obtain the number of motion data corresponding to each sampling phase and selecting the sampling phase corresponding to the minimum number of motion data as an optimal sampling phase. The ADC-PLL can correctly sample an analog signal by using the optimal sampling phase and reduce the influence of clock jitter to the minimum.

Abstract: A correction sampling signal generation circuit is disposed subsequent to a plural-stage sampling signal generation circuit for sequentially generating sampling signals in response to an input timing signal, an extended sampling circuit is disposed subsequent to a plural-stage sampling circuit for sampling a video signal at timing of the sampling signal, and a data signal is sampled at timing of the sampling signal generated by the extended sampling circuit. In a timing adjustment period, the data signal for adjustment is generated, the phases of the data signal and the timing signal are relatively shifted, the outputs of the sampling circuits are supplied to a common output line through respective switches, and the phase of the optimum timing signal or the video signal is determined based on the output from the common output line.

Abstract: A signal synchronization device and signal synchronization method are provided. The method comprises determining whether a receiving device can receive data output from an output device synchronously and adjusting the dummy period of the signal, which will be received by the receiving device, when the data output from the output device cannot be received by the receiving device synchronously.

Abstract: In an HDMI system, the clock regenerator proposed by the HDMI specification may suffer external noise because the input clock of a phase lock loop circuit in a sink device of the HDMI system is too slow. This slow input clock causes the phase lock loop circuit unable to adjust and reduce the jitter of an audio clock regenerated in the sink device. Therefore, one embodiment of the present invention provides a clock regenerator to extract the relationship between the regenerated audio clock and a video clock received by the sink device from other source devices. The clock regenerator may comprise a phase lock loop circuit, a recovery circuit, a crystal oscillator and a tracking circuit. The crystal oscillator generates a crystal clock. The phase lock loop circuit receives the crystal clock and regenerates an audio clock. The recovery circuit extracts the relationship between the audio clock and the received video clock.

Abstract: An integrated video clock signal generator in which a master phase-locked loop (PLL) control circuit uses an off-chip voltage-controlled oscillator (VCO) to produce an on-chip oscillator signal in synchronization with a horizontal reference signal related to a horizontal video synchronization signal. This on-chip oscillator signal drives one or more slave PLL circuits which provide respective one or more on-chip PLL signals synchronized with the on-chip oscillator signal. In accordance with a preferred embodiment, each on-chip PLL signal is a pixel clock signal with a plurality of clock signal pulses which is synchronized with a vertical reference signal related to a vertical video synchronization signal.

Abstract: An apparatus having a complex sine wave generating circuit (3) that generates a complex sine wave, a multiplying circuit (4) that multiplies an input signal by the complex sine wave, a first integrating circuit (5) that integrates the product obtained by the multiplying circuit (4) in the time direction, a first squaring circuit (6) that takes the square of the absolute value of a complex signal output by the first integrating circuit (5), a second squaring circuit (7) that takes the square of the absolute value of the instantaneous amplitude of the input signal, a second integrating circuit (8) that integrates the results obtained by the second squaring circuit (7) in the time direction, and a frequency difference calculating circuit (9) that finds the difference between the frequency of the input signal and the oscillation frequency of the complex sine wave on the basis of the ratio between the output signal level of the first squaring circuit (6) and the output signal level of the second integrating circui

Abstract: A method for removing color noise on a slowly varying component contained in color difference component image data of image data which is imported from an image sensor and converted to brightness and the color difference component image data, includes the steps of: sampling pixels of said color difference component image data by thinning out according to a first defined sampling format when not performing a color noise removal process on the slowly varying component; determining if the color noise removal process is necessary to be performed or not; producing the color difference component image data, corresponding to a compressed image data size smaller than an image data size without said color noise removal process, by thinning out according to a second defined sampling format when performing said color noise removal process; and recording the color difference and brightness component image data.

Abstract: A digital video system (2) is disclosed, in which an analog input video signal is sampled at an optimum sample phase (Pnc), and converted to a digital datastream for display. A phase-locked loop (12) generates a plurality of sample clock phases. One of the sample clock phases (Pnc) is applied to an analog-to-digital converter (10), which digitizes the analog input video signal accordingly. Phase alignment circuitry (20) is provided that includes three sample-and-hold circuits (22b, 22c, 22a) that sample the analog input video signal, in parallel with the analog-to-digital converter (10), at times before, at, and after the current sample clock phase used by the analog-to-digital converter (10). The earlier and later sampled voltages are compared against the current sampled voltages to generate difference voltages that are each compared against a threshold voltage (Vthr).

Abstract: The present invention provides a method and apparatus for synchronizing wireless video data. The method involves first synchronizing the pixel clock of a video output device with the pixel clock of a video input device. This is accomplished by latching video counters in the input and output devices (creating a transmit and receive timestamp) for each wireless video data packet and adjusting the pixel clock frequency of the output device according to differences between these timestamps. Once the pixel clocks are synchronized, video frames from the video output device are synchronized with video frames from video input device such that only a fraction of a video frame is buffered at any time. The video frames are synchronized by offsetting the data stream from the video input device N lines ahead of the data stream from the video output device, wherein N is less than the total number of lines in a single video frame.

Abstract: The method adjusts the phase of a quantization clock signal for a video signal automatically based on a received analogue video signal. The method includes a step of determining a horizontal start position and a horizontal end position of a pixel-level transition within the analogue video signal, a step of determining a stable-period start position and a stable-period end position at each transition by sequentially changing an adjustable phase of the quantization clock signal, a step of calculating an appropriate phase of the quantization clock signal based on the determined timings of the beginning and end of the stable periods within the analogue signal, and a step of setting the phase of the quantization clock signal to the calculated appropriate phase.

Abstract: A video signal receiver including a display synchronizing signal generation device and control method are disclosed. The video signal receiver includes: a video processor converting an input analog video signal into a digital signal; a display processor scaling the video signal converted at the video processor with an output resolution; a displaying unit displaying the video signal scaled by the display processor; a detecting unit detecting whether an input vertical synchronization signal (In V-sync) and an output vertical synchronization signal of the analog video signal match; a PLL (Phase Locked Loop) adjusting a pixel clock according to a detection result of the detecting unit; and a timing generating unit generating an output horizontal synchronization signal and the output vertical synchronization signal by use of the pixel clock adjusted by the PLL, and providing the generated output horizontal and output vertical synchronization signals to the display processor and the detecting unit.

Abstract: A video signal converting device is capable of converting an analog composite signal into a proper digital signal with a small delay even if the analog composite signal contains much jitter. The video signal converting device has a sampling clock output unit for outputting a sampling clock signal having a frequency which is 4n times the frequency of a burst signal contained in the analog composite signal (n represents a positive integer of 2 or greater), and an analog-to-digital converting unit for converting the analog composite signal into a digital signal based on the sampling clock signal output from the sampling clock output unit.

Abstract: An apparatus for driving a light scanner and method thereof are disclosed. The present invention includes an apparatus for driving a light scanner, which scans an image on a screen, the apparatus comprising the light scanner driven by a drive signal, a sensing unit sensing a driving of the light scanner, a pixel clock signal generating unit generating a pixel clock signal by detecting a 90-degree phase difference between the drive signal and a sensing signal sensed by the sensing unit, a sync signal adjusting unit adjusting vertical and horizontal sync signals of an input video according to the pixel clock signal and a driving unit driving the light scanner according to the adjusted horizontal and vertical sync signals.

Abstract: A display drive integrated circuit is for driving a display panel. The display drive integrated circuit includes a division rate output unit which outputs as a division rate corresponding to a quotient obtained by dividing by M a total number of clock cycles of a dot clock signal corresponding to a clock cycle of a horizontal synchronization signal, where M is a natural number, and a system clock generating unit which generates a system clock signal by dividing the dot clock signal using the division rate.

Abstract: A method for generating a video clock and an associated target image frame is disclosed. The method generates an output clock signal for outputting a target image frame to a panel according to a frame pixel number and a vertical synchronization signal (Vsync). The target image frame corresponds to a source image frame. The frame pixel number is the number of total pixels included in a predetermined frame format, and the Vsync signal is an input Vsync signal or an output Vsync signal. The period of the output clock signal is the result of the period of the Vsync divided by the frame pixel number. In this manner, the format of the target image frame can remain substantially fixed, and is substantially equal to the predetermined frame format.

Abstract: A method and system of automatically correcting a sampling clock in a digital video system are disclosed. Sampling clocks with different phases are generated and subjected in turn to analog-to-digital conversion (ADC). A difference of at least a pair of neighboring data out of the ADC with respect to each phase is determined. A maximum difference is determined, and the sampling clock with the phase corresponding to the maximum difference is thus generated.

Abstract: A receiver is enabled to perform self-configuration of the main data link to receive and display video data. A video data signal is received through a data link having multiple channels or lanes at a specific bit rate. No link configuration data normally associated with the video signal is received. It is then determined which one or more of the channels of the data link are active in transmitting the data signal. A symbol pattern in the data signal is then identified. The symbol rate of the data signal is then synchronized with the local clock frequency. The local clock frequency is set to correspond to the actual bit rate of the data signal, thereby creating a signal-based clock frequency. This local clock frequency is set using only the data signal since no link configuration data associated with the signal is received. In this manner, the receiver configures or trains the link itself using only the video data signal and therefore, the receiver may be described as self-sufficient.

Abstract: A method and apparatus for an analog-to-digital video signal converter. The converter is controlled by a clock with controllable frequency and phase for sampling an analog signal. A circuit corrects the clock frequency using a period of a columnar frame differences as a function of columnar location. The sampling clock frequency is changed by an amount dependent on the period of the columnar differences. A second measure of the difference between successive frames is computed for a sequence of clock phases. The frequency of the clock is verified using a characteristic of the second measure. The characteristic can be the ratio of the maximum to the minimum of the second measure over selected clock phases. Other characteristics can be used such as a difference of a maximum and a minimum measure.

Abstract: A clock recovery circuit in a digital display unit for recovering a time reference signal associated with analog display data. The clock recovery circuit includes a phase-locked loop (PLL) implemented in digital domain and an analog filter to eliminate any undesirable frequencies from the output signal of the PLL. The PLL includes independent control loops to track long term frequency drifts of the time reference signal and the transient phase differences respectively. By providing such independent control loops, the generated clock can be better synchronized with the time reference signal. Scaling a source image formed of a number of source image elements to provide a destination image formed of a number of destination image elements using a line buffer and no frame buffer.

Abstract: A clock recovery circuit in a digital display unit for recovering a time reference signal associated with analog display data. The clock recovery circuit includes a phase-locked loop (PLL) implemented in digital domain and an analog filter to eliminate any undesirable frequencies from the output signal of the PLL. The PLL includes independent control loops to track long term frequency drifts of the time reference signal and the transient phase differences respectively. By providing such independent control loops, the generated clock can be better synchronized with the time reference signal. This invention is directed to a method of scaling a source image formed of a number of source image elements to provide a destination image formed of a number of destination image elements using a line buffer and no frame buffer.