Abstract: A synchronization signal correcting apparatus and method for a digital TV is disclosed. The present invention allows an output of a stable analog image in a digital TV by compensating for the difference between an input sync and a display sync that may be generated during a digital processing of an input analog image signal. Essentially, a sync signal correcting apparatus includes an image processing unit, a sync control signal generating unit for generating a sync control signal to lock a display sync of an image signal from the image processing unit with a sync of an input image signal; and a sync signal correcting unit for correcting a sync signal of the image processing unit in accordance with the sync control signal from the sync control signal generating unit. Thus, an output image signal is synchronized with the input image signal.

Abstract: The present invention provides a technique that facilitates A-D conversion and D-A conversion of high-frequency image signals. Three A-D converters 71 through 73 successively carry out A-D conversion of an analog image signal AV1, in response to three sampling clock signals SAD1 through SAD3, which respectively have a frequency that is ⅓ of a frequency of a dot clock signal DCLK1 and phases that are sequentially shifted by a period of the dot clock signal DCLK1, thereby generating three digital image signals D1 through D3 with respect to three consecutive pixels. The digital image signals for the three pixels are written into consecutive storage areas in a frame memory 26. Reading operation of an image signal from the frame memory 26 is also carried out at a frequency that is ⅓ of a frequency of a read dot clock signal. The working number of A-D converters and the working number of D-A converters are regulated according to the frequency of the analog image signal.

Abstract: A timing recovery device in a digital television receiver using a VSB system is disclosed. In the present invention, the timing recovery device independently determines whether the detected hsync signal is reliable and operates if the detected hsync signal is reliable.

Abstract: A clock generating apparatus is provided for producing an output clock signal responsive to a source clock signal with a source frequency and a reference clock signal with a reference frequency. The clock generating apparatus includes a counting sequence generator, a measuring value generator and a ratio counter. The counting sequence generator is used for outputting a series of counting values in response to a triggering signal with a specified period determined by the source frequency of the source clock signal and a predetermined counting value. The measuring value generator generates a measuring value by operating the series of counting values according to a predetermined formula. The ratio counter produces the output clock signal with a frequency determined by the source frequency of the source clock signal and the measuring value.

Abstract: A color demodulation apparatus having color demodulation capabilities as the conventional ones, with its size reduced by sharing part of processing circuit therein is provided. An adder circuit 10 and a SW circuit 11 shift the phase of a ramp wave generated by a VCO circuit 9 alternately 90 degrees and 180 degrees for each clock. A SIN data generator circuit 12 generates a phase alternate SIN wave signal from the shifted ramp wave. A multiplier circuit 3 performs R-Y and B-Y demodulation through multiplexing based on the phase alternate SIN wave signal. An accumulator circuit 6 accumulates burst signals of each of R-Y and B-Y signals of the demodulated, multiplexed signal. A second load hold circuit 8 separately outputs an R-Y burst signal to the VCO circuit 9, and a B-Y burst signal to a comparator circuit 13, constituting two feedback loops. A first load hold circuit 5 separates R-Y and B-Y signals from the multiplexed signal, and outputs these two signals.

Abstract: To provide a video signal transmission apparatus capable of correctly transmitting a digital video signal. A PLL circuit 5 has a first cutoff frequency lower than the frequency of a horizontal synchronization signal contained in a digital video signal S9. has the characteristics of causing attenuation of a signal of the frequency higher than the first cutoff frequency, performs PLL processing for a dot clock signal S14 for identifying one pixel's worth of data of the digital video signal S9, and generates a transmission clock signal 55 of the frequency N (integer of 2 or more) times the first dot clock signal S14. The PLLL circuit 6 has a second cutoff frequency higher than the frequency of the horizontal synchronization signal, tracks a signal of a frequency lower than the related second cutoff frequency, performs the PLL processing on the serial signal S2 input via the transmission cable 4, and generates a transmission clock signal S6.

Abstract: A video projection display system (10) of this invention employs histograms to detect an active video region (2) of a video frame (1). A microcontroller (16) loads registers (27) in an ASIC (26) to accumulate histograms of low pixel values occurring within columns (70-74) of video data. The microcontroller scans the histograms to, identify the left-most column in which a set (80) of black pixel values is clustered, which column marks the left edge of the active video region. The right edge of the active video region is detected in a similar manner. The video signal may also include overshoot and noise. When an ADC (24) digitizes the video signal, the overshoot and noise causes many bright pixels to be converted to below their maximum digital values. Therefore, the microcontroller programs the ASIC such that a histogram (90) of the highest pixel values is collected from within the active video region.

Abstract: A circuit for providing a sufficiently accurate clock signal for reconstruction of an image from a video signal can function with or without receiving an incoming video signal containing clock data. In this way, a clock signal for supporting an on-screen display can be created in the absence of an incoming video signal. Control data used to control a voltage controlled oscillator generating a clock signal is recorded when the control logic of the oscillator is locked to the timing data in an incoming video signal. In the absence of an incoming video signal, the recorded control data is retrieved and resubmitted to the control logic so that the oscillator can be made to output an appropriate clock signal even in the absence of an input video signal.

Abstract: A method and apparatus for compensating for time base or phase errors in video and audio signals that are separately stored or processed. A ring oscillator provides a plurality of clock signals, each having a same frequency and slightly different phase. Each of the clock signals is applied to a multiplexor for allowing an appropriate one of the clock signals to be selected. By selecting appropriate ones of the clock signals in a sequence, the frequency and phase of an output clock signal formed by the multiplexor can be continuously and precisely controlled. Sync pulses separated from a video signal having a varying time base are applied to a video timing generator circuit which generates a series of digital values representative of timing differences between an expected occurrence of a sync pulse and an actual occurrence of the sync pulse. A phase accumulator accumulates the digital values over time for generating appropriate addresses for the multiplexor.

Abstract: A clock generating device for use in a digital video apparatus generates display clock matching an input video format. The clock generating device generates a clock of a frequency which is a predetermined number of times greater than the clock necessary for displaying video signals having a respectively different format, frequency-divides the generated clock, phase-locks the obtained stable frequency and supplies corresponding display clock. Video signals of a respectively different format can be displayed into a single display format, to thereby provide an effect of displaying a video signal without degeneration of a picture quality.

Abstract: A method of recovering a pixel clock for generating a digital image from an analog video signal is presented. The on and off-transition times for the active video portion of a digital image and the image size defined in a video standard are used to generate a pixel clock. The analog video signal is digitized according to the pixel clock and the image size of the resulting digital image is compared with the image size defined in the video standard. The pixel clock frequency is adjusted in response to the image size comparison. The optimum phase of the pixel clock relative to the analog video signal is determined through a repetitive phase adjustment technique. A first image coordinate is determined for a pixel clock at one phase and a subsequent image coordinate is determined for a pixel clock after decrementing the phase of the pixel clock. The first image coordinate and the subsequent image are compared.

Abstract: A clock generator is provided which comprises a reference signal generator; a voltage controller/generator to generate a dot clock signal; a frequency divider to divide the frequency of the dot clock signal supplied from the voltage controller/generator; a phase comparator to detect a phase difference between the reference signal supplied from the reference signal generator and a signal supplied from the frequency divider; a frequency division ratio setter to set the frequency division ratio in the frequency divider to less than a quotient resulted from division of a total number of horizontal pixels in each of the video signals by a greatest common divisor of the total of horizontal pixels in the video signal having one format and total number of horizontal pixels in the video signal having the other format; and a frequency division ratio selector to select a frequency division ratio set by the frequency division ratio setter correspondingly to a format of a video signal.

Abstract: An apparatus and method for extracting vertical (V-SYNC) and horizontal (H-Blank) sync signals from a digital composite sync signal (C-SYNC) of a master video source for use in controlling a second video source, which allows for an adjustable delay relationship between the C-SYNC from the master source and the generated H-Blank. The present invention also provides a system and method for varying the responsiveness or gain of the genlocking circuit used to synchronize the system pixel clock frequency of the second video source to that of the master video signal.

Abstract: A pixel clock frequency is adjusted in response to periodically monitoring the relative positions between a video signal to be displayed and a video signal captured. Image shear of the display signal may be avoided quickly. Adjustments are made to the color burst signal where dramatic changes in the pixel clock frequency result.

Abstract: A system includes a signal reconstruction controller (110) electrically coupled to at least one analog-to-digital converter (ADC) (112) and to a phase adjustable clock source (108). A sampling clock signal (116) is electrically coupled from the clock source (108) to the at least one ADC (112). The at least one ADC (112) samples an electronic signal according to the sampling clock signal (116) to provide a digital representation of the electronic signal. The controller (110) samples data from the ADC (112) at different sampling points in the electronic signal and determines the edges (140) of the electronic signal and the noisy samples (142, 144) that are away from the edges (140) of the electronic signal. By finding the least noisy sample (146, 148) that is away from the edges (140) of the electronic signal the controller (110) adjusts the phase of a sampling signal clock (116) to a sampling point that is the most reliable to sample the electronic signal to provide a digital representation thereof.

Abstract: A monolithic integrated circuit for use in a digital display unit. The circuit may include an analog-to-digital converter (ADC), a scaler and a clock recovery circuit. The present invention enables the integration of at least these components into a single monolithic integrated circuit while maintaining reasonable display quality. Specifically, the monolithic integrated circuit is designed for substantial immunity from noise, which may otherwise result from integration.

Abstract: A method and circuit generates a sampling clock signal that digitizes an analog video signal. The sampling clock signal is generated by a clock divider coupled to the horizontal synchronization signal of the analog video signal. A divisor calculator calculates a divisor for the clock divider to control the frequency of the sampling clock signal. Specifically, the divisor calculator selects an initial divisor for the clock divider. Then the divisor calculator calculates a new divisor based on the target pixel value provided by a mode detector and the measured pixel value from a counter. Some embodiments of the present invention provides fine tuning of the frequency by testing other possible divisors with a plurality of different phases. In addition, some embodiments of the present invention calibrate the phase of the sampling clock signal to generate a phase shifted sampling clock signal.

Abstract: A clock-recovery system is used to align a clock-phase with the RGB-signals. A frequency-synthesizing loop is applied for receiving a reference clock signal (CKREF) to generate a synthesized frequency. A fine-tuned frequency-synthesizing loop then receives a horizontal synchronization signal (HSYNC) to fine-tune the synthesized frequency into a fine-tuned synthesized frequency. A phase divider subdivides the fine-tuned synthesized frequency into a multiple phase segments for inputting to a multiplex controller. An analog sensor, receives and senses the RGB signals for generating encoded sensing data corresponding to voltage transitions of the RGB signals. A transition detector then applies the encoded sensing data for generating transition-detection data. A threshold triggering circuit compares the transition-detection data with a threshold data and triggering a RGB-phase data upon detecting the threshold data is exceeded by the transition detection data.

Abstract: A receiver for processing a VSB modulated signal containing terrestrial broadcast high definition television information includes an input analog-to-digital converter (19) for producing a digital datastream. A symbol timing recovery and segment sync recovery network (24; FIG. 3, 4) develops a properly timed sampling clock for the digital converter (19). The symbol timing recovery network (310) responds to an output from the segment sync recovery network (328), which in turn responds to an equalized signal from an adaptive channel equalizer (34). A controlled oscillator (336) generates the sampling clock for the digital converter. A control network (340, 344, 348; FIG. 3) shifts the frequency range of the oscillator to maintain desired linear operation to enhance symbol timing acquisition.

Abstract: The proposed phase lock technique uses various feedback loops to lock the frequency and phase of a CATV modulator output signal to that of an off-air signal without directly measuring the output frequency. One embodiment includes a tuner for receiving the off-air signal and generating an intermediate frequency signal and a phase-frequency detector for comparing the frequency and phase of the intermediate frequency signal generated by the tuner with the frequency and phase of an intermediate frequency signal generated by the modulator based on a reference input signal. The output of the phase-frequency detector is used to control the reference input signal into the modulator and the reference input signal to the tuner such that the frequency and phase of the modulator output signal is locked to the frequency and phase of the received off-air signal.

Abstract: A PLL circuit which outputs an oscillation clock signal synchronous with a reference clock includes a phase lock detector for detecting if the oscillation lock signal is synchronous with the reference clock. If the phase lock detector detects a phase difference between the oscillation clock signal and the reference clock, a charge pump circuit is used to alter the oscillation clock signal so that the oscillation signal is placed back in sync with the reference clock. The charge pump selects one of a ground potential and a power supply potential in response to a comparison result of the oscillation clock signal and the reference clock. The charge pump pulls a constant current to ground from an output terminal of the charge pump ,circuit when the ground potential is selected and supplies a constant current to the output terminal of the charge pump circuit when the power supply potential is selected, thereby producing an output which alternately repeats the ground potential and the power supply potential.

Abstract: A receiver to recover data encoded at high speed in a signal over a serial communication channel. A static phase determination circuit indicates whether the signal is early, late or neutral relative to a sampling clock. The sampling clock is used to oversample the signal to generate multiple samples. A token analyzer examines the transitions around a current symbol to determine any short term phase shifts of the boundaries between symbols. The short term phase shifts and the static phase together may be used to accurately select the samples representing the symbols without requiring extensive processing.

Abstract: In a video signal processing device, an input video signal VO representing a test pattern having two gradations of black and white is converted to 8-bit data by an AID converter 4 in synchronism with sampling clocks generated in a write-in control circuit 5, and then stored in a memory 6. An MPU 9 reads out picture element data in an effective area of the video signal stored in the memory 6, and calculates the difference AT between the average value of White-level picture element data whose values are larger than a predetermined value and the average value of black-level picture element data whose values are smaller than a predetermined value, and the total variance VT between the variance of the white-level picture element data and the variance of the black-level picture element data. The MPU 9 controls the phase of the sampling clocks generated in the write-in control circuit 5 so that the AT is maximum and the VT is minimum.

Abstract: A signal of a vestigial sideband modulated wave is generated by use of a first oscillator, an amplitude-modulator and a surface acoustic wave filter for vestigial sideband filtering at a frequency being higher than the carrier frequency of a video signal, the signal is frequency-converted to a given transmission channel by use of a first PLL frequency synthesizer, a first control circuit, a frequency converter and a filter.

Abstract: A Time Based Correction (TBC) method for digital synchronization of video signals. The time based correction method may be used for satellite based communications to keep clocks synchronized in a multimedia system. Digital receiver clock phases are compared to measure synchronization. The method includes an initialization procedure (tbcInit) that initializes algorithm variables and sets up an initial phase; a measurement procedure (tbcGetPhase) that measures the current phase; and a tracking procedure (tbcAdjust) that makes periodic adjustments to the output clock (VO_CLOCK).

Abstract: A method for driving a plasma display panel which can perform a good image display even if a video signal having a jitter is supplied is provided. At least one of the execution time of a pixel data writing step in each sub-field, the execution time of a light emission sustaining step, and the number of sub-fields to be executed during a display period of one field is adjusted in accordance with the jitter of a vertical sync signal in the input video signal.

Abstract: The present invention provides a technique for appropriately adjusting a dot clock for video signals by a simple process. A process of adjusting a phase of the dot clock first obtains two image data by two dot clocks having different phases, carries out a certain operation for the two image data to calculate a phase-related index representing the relative phase of the dot clock to a video signal with respect to the two image data, and determines a delay that gives a desirable phase to the dot clock based on these phase-related indexes. A first process of adjusting the frequency of the dot clock first obtains image data by a dot clock that has been generated with a provisional factor, calculates a length of an effective signal area on one line of the image data, and determines a desirable factor based on the ratio of a known length to the measured length of the effective signal area.

Abstract: An embodiment of the present invention provides a signal generator for generating a signal with a predetermined frequency. The signal generator includes a first comparator for generating a first error signal and a second comparator for generating a second error signal. The first and second comparators are coupled to an oscillator configured to receive the first and second error signals and generate the signal having a predetermined frequency. Another embodiment of the present invention provides a signal generator for generating a signal with a predetermined frequency. The signal generator includes a counter for generating a first count, Q_last. The counter is coupled to a ratio counter which generates a signal having a value less than or equal to Q_last. The contents of the ratio counter represent the phase of the signal having a predetermined frequency. The ratio counter outputs the signal having a predetermined frequency.

Abstract: An apparatus and method for synchronizing sampling of a video signal to a video synchronization signal of the video signal are provided. The frequency-divided output of an oscillator (or other controllable frequency source) is applied as one input to a phase detector, while the other input to the phase detector is supplied by the video synchronizing signals. The error signal voltage output of the phase detector is applied to correct the frequency, and thereby the phase, of the oscillator output through a dynamically-tuned phase-locked loop filter until the phases of the two input signals are in perfect agreement and no error voltage is produced. After a delay for this phase correction, during which time all video amplification is suspended, an output of the oscillator is then applied to sample the image without the presence of phase disparities while video amplification is restored. Full dynamic range digital acquisition then proceeds with extremely high accuracy at any desired resolution.

Abstract: A clock recovery circuit in a digital display unit for recovering a time reference signal associated with analog display data. The clock recovery circuit includes a phase-locked loop (PLL) implemented in digital domain and an analog filter to eliminate any undesirable frequencies from the output signal of the PLL. The PLL includes independent control loops to track long term frequency drifts of the time reference signal and the transient phase differences respectively. By providing such independent control loops, the generated clock can be better synchronized with the time reference signal.

Abstract: The circuit recovers teletext signals, notably VPS, TXT, WSS and similar signals, from a video signal with concurrent production of the standard scanning frequency of the respective teletext signal. The recovery circuit has a single phase locked loop circuit which generates a reference frequency from a basic frequency supplied by an oscillator circuit. The reference frequency is a multiple of the scanning frequency in question. To scanning frequency is extracted from the reference frequency with a frequency divider.

Abstract: A phase-locked loop is provided which is operable to lock the sampling clock (pixel clock) to the incoming horizontal sync pulse contained within composite video information. Two modes of operation, coarse lock mode and fine lock mode, are used in controlling the phase-locked loop. In the coarse lock mode, coarse corrections are made to a horizontal discrete time oscillator so that a fast lock may be achieve using the fine lock mode. Coarse corrections are based on a normalized sum of weighted pixels collected within a narrow gate window. Lock is achieved when the falling edge is centered within the window.

Abstract: A process of clock recovery during the sampling of computer-type signals, wherein the sampling clock is generated from a phase locked loop or PLL which multiplies a given frequency by an integer number, includes gauging the position of the edges of the computer-type signals with respect to the sampling clock with the aid of an analog ramp triggered by the rising edges of the said signals in such a way as to obtain a first position-dependent value, carrying out a sampling clock phase correction and then carrying out a sampling clock frequency correction by using a processor.

Abstract: When short MPEG2 data transfer streams, such as those used for commercials, are sequentially distributed within a short period of time, a decoder method synchronizes the transfer and prevents accumulation of data in a buffer and data losses. The synchronization method extracts sync data originating at the transmission source from a received data stream; acquires sync data for a decoder based on a reference clock; compares the sync data originating at the transmission source with the sync data for the decoder in order to sequentially obtain control values, sequentially updates the frequency of the reference clock for transfer synchronization for the received data stream; determines whether or not a data stream that differs from the received data stream has been received; and employs, when a different data stream has been received, the reference clock obtained when the received data stream has been received, to initiate transfer synchronization for the different data stream.

Abstract: A signal processing method for an analogue picture signal is proposed. In this case, the analogue picture signal originates from a computing unit (10) in which the signal was generated digitally in accordance with a graphics standard such as, for example, EGA or VGA and was subsequently converted into analogue form. The method consists in subjecting the analogue picture signal to analogue/digital conversion at a first chosen sampling frequency, after which the sampled picture is then investigated for picture disturbances, in order to determine a corrected sampling frequency. Further measures relate to the determination of the optimum sampling phase and the determination of the exact position of the active picture relative to the horizontal and/or vertical synchronization pulses.

Abstract: A periodic multi-bit digital signal is synthesized having a frequency that is specified by the frequency of a periodic reference signal that is asynchronous with respect to a sampling clock of the periodic digital signal. In a digital video system, for example, a digital color subcarrier is synthesized and synchronized to a reference frequency of a crystal oscillator that is asynchronous with respect to a digital system clock for the digital video system. The periodic digital signal is generated by an adjustable digital oscillator clocked by the sampling clock. The frequency or phase of the periodic digital signal is compared to the frequency or phase of the periodic reference signal to produce an adjustment value for adjusting the periodic digital signal to synchronize the periodic digital signal with the periodic reference signal. The digital oscillator, for example, generates the periodic digital signal at the sampling rate by periodically incrementing an accumulator with the adjustment value.

Abstract: A method and circuit generates a sampling clock signal that digitizes an analog video signal. The sampling clock signal is generated by a clock divider coupled to the horizontal synchronization signal of the analog video signal. A divisor calculator calculates a divisor for the clock divider to control the frequency of the sampling clock signal. Specifically, the divisor calculator selects an initial divisor for the clock divider. Then the divisor calculator calculates a new divisor based on the target pixel value provided by a mode detector and the measured pixel value from a counter. Some embodiments of the present invention fine tune the frequency by testing other possible divisors with a plurality of different phases. In addition, some embodiments of the present invention calibrate the phase of the sampling clock signal to generate a phase shifted sampling clock signal.

Abstract: The present invention provides a technique for appropriately adjusting a dot clock for video signals by a simple process. A process of adjusting a phase of the dot clock first obtains two image data by two dot clocks having different phases, carries out a certain operation for the two image data to calculate a phase-related index representing the relative phase of the dot clock to a video signal with respect to the two image data, and determines a delay that gives a desirable phase to the dot clock based on these phase-related indexes. A first process of adjusting the frequency of the dot clock first obtains image data by a dot clock that has been generated with a provisional factor, calculates a length of an effective signal area on one line of the image data, and determines a desirable factor based on the ratio of a known length to the measured length of the effective signal area.

Abstract: An output timebase corrector converts orthogonal sampled video (VS) into asynchronous sampled video (VOS) with asynchronous sample values occurring at clock instants (TC) of a clock signal (CLK). The asynchronous sampled video (VOS) is displayed on a display screen of a display device (DD). A discrete time oscillator (DTO) of a time-discrete phase-locked loop (PLL) supplies a time base signal (OS). The time-discrete phase-locked loop (PLL) determines a phase difference (PE) between the time base signal (OS) and reference instants (FB) indicating a timing of a line deflection of the display device (DD) to obtain the time base signal (OS) being locked to the reference instants (FB). The time base signal (OS) controls a sample rate converter (SRC) such that the asynchronous video values (VOS) which occur at the clock instants (TC) are interpolated from the orthogonal sampled video (VS) by the sample rate converter (SRC) such that the video signal is displayed on the correct position on the display screen.

Abstract: A delay detecting section detects the phase difference between a first detection signal as a reference and a second detection signal produced by delaying the first detection signal with part of a data signal line driving circuit itself or part of a circuit formed by the same process as the data signal line driving circuit. A phase adjusting section presumes an internal delay of the data signal line driving circuit, and adjusts the phase difference between a clock signal and start signal, and a video signal so that the data signal line driving circuit samples the video signal at an appropriate timing. These structures prevent a lowering of the image quality due to a difference in the timings of the video signal and sampling signal, and provide an image display device capable of displaying a good-quality image with a simple circuit structure.

Abstract: A systolic video encoding system processes image data from a frame buffer at a core clock rate that is independent of the sample rate of the image data. The video encoder of this invention uses the core clock rate of the host image processing system to process image from the frame buffer at this core clock rate. The image data is pumped out of the frame buffer, processed by each of the processes of the video encoder when the data reaches each of the processes, and the encoded samples are stored in a raster sample buffer for subsequent processing. The image data is continually pumped out of the frame buffer at the core clock rate until the raster sample buffer is full. As the samples are extracted from the raster sample buffer, subsequent image data is pumped into the video encoding system, producing a systolic processing effect.

Abstract: An apparatus for performing a generator locking for a video signal including a first video processing circuit for processing an input video signal, an expansion module having a second video processing circuit and a delay circuit having a delay time introduced by said second video processing circuit, a synchronizing signal separating circuit for separating a synchronizing signal from an external reference signal, and a phase-lock loop circuit for generating a reference control signal for said first video processing circuit as well as a phase comparison signal. Said phase comparison signal is fed-back to the phase-lock loop circuit by means of said delay circuit. Although the expansion module is connected to the expansion slot, a phase of a finally obtained video signal is remained in a same fixed relationship as a phase relationship when a connection board is connected to the expansion slot.

Abstract: The preferred embodiments generalize the Band Edge Component Maximization (BECM) timing recovery method and provide blind timing recovery in Quadrature Amplitude Modulation (QAM) using all the available information rather than sampling the BECM output at the symbol rate.

Abstract: An automatic sampling control system for digital monitors. A clock generation circuit generates a sampling clock. A phase controller modifies the phase of the sampling clock by a phase amount. An ADC samples a frame of an analog display signal to generate digital samples. A value which is a function of the samples is generated. The function generally generates a larger value with correspondingly large sample values. The phase amount is modified for successive image frames until a maximum function value is generated. When successive image frames do not change substantially in image content, the phase amount represents the optimal phase change for the sampling clock. If the image content is changing substantially, the phase adjustment may be disabled.

Abstract: An image display device is arranged to convert analog video signals into digital video signals and display the corresponding image to the digital video signals. The image display device provides a variable delaying circuit for delaying an analog video signal of each color or a clock variable delay circuit for delaying a dot clock for generating each color dot clock and supplying each color dot clock as a conversion timing signal of an analog-to-digital converting circuit of the corresponding color. This kind of delay circuit is served to adjust a phase of the analog video signal or the dot clock of each color, thereby suppressing color blur even if the analog video signal contains skews among the colors.

Abstract: Apparatus for processing video signals and which can be connected with a personal computer for further processing. An analog to digital converter samples and converts input NTSC composite video signal into digital signal for subsequent processing. A phase-locked loop provides sampling clock signal to the ADC, and also ensures accurate sample phase. Based on a theory that human eye is more sensitive to the luminance component of video signals, a double sampling circuit is included which double samples the luminance component of a video signal to improve the overall resolution of an image.

Abstract: A clock generation circuit for use in a television system displaying images encoded in television signals and images represented by network application data. The clock generation circuit generates a clock signal synchronized with HSYNC signals of the television signals. The clock generation circuit includes a phase-lock-loop (PLL) circuit and a tracking block. PLL circuit includes an oscillator (e.g., VCO) driven by an error signal to generate an internal periodic signal having frequency substantially equal to the frequency of the desired clock signal. The tracking block includes a resettable VCO (RVCO) driven by the error signal. A restart signal is asserted prior to the expected arrival time of the HSYNC edge to cause the RVCO to stop generating the desired clock signal. The restart signal is deasserted on receiving the HSYNC edge to cause the RVCO to start generating the clock signal. Accordingly, the clock signal is synchronized with the HSYNC signal.

Abstract: A digital PLL circuit employs a fixed-frequency output signal from a fixed-frequency oscillator, to provide a signal synchronized with an external reference signal. The digital PLL circuit has a counter and an adjuster. The counter counts clock periods (clock pulses) of the fixed-frequency output signal. The adjuster increments or decrements a value counted by the counter a predetermined number of times in a predetermined period according to a deviation of the fixed-frequency output signal from the reference signal. This digital PLL circuit is inexpensive because it employs no DA converter nor VCO.

Abstract: A synchronize processing circuit offers a stable supply of synchronizing signal to control circuits in display devices.

Abstract: A video signal sampling circuit searches the optimum sampling frequency and phase of the sampling clock signal by detecting level changing points in the sampled video signal in the horizontal direction with the sampling frequency varied every predetermined phase. The saturated maximum count of the level changing point provides the optimum sampling frequency and optimum phase of the sampling clock signal. The video signal sampling circuit automatically sets the optimum sampling frequency and phase of the sampling clock signal in accordance with the result of searching. The video display including the video signal sampling circuit is also disclosed.