Abstract: A system for phase-locking a clock to a digital audio signal embedded within a digital video signal uses an audio extractor, frequency dividers, and an adjusted bandwidth loop filter to prevent phase jitter associated with the digital audio signal preventing the functionality of the phase-lock loop or having unacceptable effects on the generated audio sample frequency signal. Extracted audio samples are divided down and input to a phase detector. The signal is then filtered using a series of loop filters, one of which has an adjusted bandwidth to reject phase jitter. A clock then outputs the generated synthesized audio sample frequency using the output from the series of loop filters, and the synthesized frequency signal is looped back through a second frequency divider to the phase detector.

Abstract: A multiple format video signal processing system operating in conjunction with a display device timing system to produce synchronized video and timing signals suitable for use by a fixed horizontal scanning frequency display device.

Abstract: The present invention provides a technique for appropriately adjusting a dot clock for video signals by a simple process. A process of adjusting a phase of the dot clock first obtains two image data by two dot clocks having different phases, carries out a certain operation for the two image data to calculate a phase-related index representing the relative phase of the dot clock to a video signal with respect to the two image data, and determines a delay that gives a desirable phase to the dot clock based on these phase-related indexes. A first process of adjusting the frequency of the dot clock first obtains image data by a dot clock that has been generated with a provisional factor, calculates a length of an effective signal area on one line of the image data, and determines a desirable factor based on the ratio of a known length to the measured length of the effective signal area.

Abstract: An MPU changes the phase of a sampling clock signal by one step for each frame until the change in the phase reaches 360 degrees. An image quality detector portion sequentially receives a digital image signal to detect a maximum one of data about the absolute value of a difference between adjacent pixels in one frame as an image quality judgement data signal. The MPU detects a maximum one of all image quality judgement data to determine a phase at that time as an optimum phase of the sampling clock signal. The MPU then periodically checks image quality on a screen, and makes a real-time correction to the phase of the sampling clock signal if a temperature drift or the like occurs.

Abstract: A periodic multi-bit digital signal is synthesized having a frequency that is specified by the frequency of a periodic reference signal that is asynchronous with respect to a sampling clock of the periodic digital signal. In a digital video system, for example, a digital color subcarrier is synthesized and synchronized to a reference frequency of a crystal oscillator that is asynchronous with respect to a digital system clock for the digital video system. The periodic digital signal is generated by an adjustable digital oscillator clocked by the sampling clock. The frequency or phase of the periodic digital signal is compared to the frequency or phase of the periodic reference signal to produce an adjustment value for adjusting the periodic digital signal to synchronize the periodic digital signal with the periodic reference signal. The digital oscillator, for example, generates the periodic digital signal at the sampling rate by periodically incrementing an accumulator with the adjustment value.

Abstract: The present invention provides a special designed circuit in which some low-cost CPUs (low-level CPUs such as 8051 or 6805) and some simple circuit elements are incorporated to achieve the object of converting analog video signals output from a VGA card into digital video signals. Such circuit is advantageous in that the cost is very low and the conversion from analog signal to digital signal can be performed accurately.

Abstract: Device and method for generating a clock in an HDTV receiver is disclosed, the device including a clock generating part for generating a plurality of clock signals and selecting one clock signal from the clock signals in agreement to a frame rate of a presently received video signal having a reference clock signal in response to a provided clock selecting signal, and a controlling part for providing the clock selecting signal at a time when phases of the selected one clock signal of just prior video signal and the reference clock signal of the presently received video signal are in agreement to each other, whereby a stable supply of display clock signal is made possible even when a video format of a received video signal is changed.

Abstract: In a video signal processing device, an input video signal VO representing a test pattern having two gradations of black and white is converted to 8-bit data by an A/D converter 4 in synchronism with sampling clocks generated in a write-in control circuit 5, and then stored in a memory 6. An MPU 9 reads out picture element data in an effective area of the video signal stored in the memory 6, and calculates the difference AT between the average value of white-level picture element data whose values are larger than a predetermined value and the average value of black-level picture element data whose values are smaller than a predetermined value, and the total variance VT between the variance of the white-level picture element data and the variance of the black-level picture element data. The MPU 9 controls the phase of the sampling clocks generated in the write-in control circuit 5 so that the AT is maximum and the VT is minimum.

Abstract: A delay correction circuit includes a source of a clock signal and a source of a timing signal asynchronous with the clock signal. A timing signal detector is responsive to the clock signal and the timing signal, and is properly operative only when the timing signal is stable for a predetermined time period around the clock signal. A control circuit conditions utilization circuitry to operate after a delay time after the timing signal is detected. Adjusting circuitry conditions the control circuit to adjust the delay time if the timing signal was not stable within the predetermined time period.

Abstract: An image data modification technique addresses certain image defects characteristic of still images derived from original video sources, such as television or videotape. A lack of vertical alignment of pixels in a single frame, causing a "wobble" or "jitter" artifact in the image, is detected and corrected by a series of algorithms.

Abstract: A display control apparatus for forming dot clocks for display corresponding to a video signal from a first sync signal and executing a display control is constructed by a comparator for comparing the first sync signal and frequency division signals, a clock forming circuit for forming the dot clocks for display on the basis of a result of the comparator, a memory in which frequency division parameters of the dot clocks for display have been stored, a frequency division signal forming circuit for forming the frequency division signals from the frequency division parameters and the dot clocks for display, a counter for counting the first sync signal, and a changing circuit for changing the frequency division parameters stored in the memory in the case where a count value of the counter reaches a predetermined value.

Abstract: A video transmission system and method including a technique for deriving clock information in a receiver from a transmitted analog video signal to decipher digital data encoded on the video signal. A phase-locked loop in the transmitter is used to phase-lock a color burst subcarrier in the video signal to a local oscillator in the phase-locked loop to phase-lock a data clock to the subcarrier. A phase-locked loop in the receiver is also used to phase-lock the subearrier of the transmitted video signal to a local oscillator in the phase-locked loop to again phase-lock a data clock to the subcarrier. By phase-locking a data clock to the subcarrier in both the transmitter and receiver, the data clock and the receiver can be synchronized to the data clock and the transmitter to provide for effective digital data recovery without the use of additional data bits for clock phase information.

Abstract: The invention presents a dot clock reproducing apparatus for automatically reproducing the dot clock easily, by setting the dot clock frequency of a video signal source, and correcting the phase difference of the dot clock occurring in the transmission route or the like, and also presents a dot clock reproducing method comprising, in dot clock reproduction, a step of sampling at a frequency different from the dot clock of video signal, a step of detecting the aliasing frequency component occurring at this time, and a step of reproducing the dot clock so as not to cause this aliasing frequency component, and as an apparatus employing such method, the invention further provides a dot clock reproducing apparatus comprising A/D converting means for receiving an adjusting signal delivered from a video signal source, and sampling this adjusting signal to convert into a digital signal, PLL means for dividing a specified synchronizing signal and generating a sampling clock for the A/D converting means, frequency anal

Abstract: An A/D converter samples an analog video signal, having a frequency corresponding to various types of image supply apparatus, and converts the signal into a digital signal. A sampling clock signal supply circuit supplies a sampling clock signal to the A/D converter, and comprises an edge detection circuit for adjusting the phase of the sampling clock signal. The edge detection circuit subjects the video signal and a delayed video signal to subtraction processing to generate edge pulses. A processor selects a sampling clock signal of a desired phase based on edge information determined by these edge pulses. The present device can also adjust a threshold voltage that is input to the comparator, and the phase of the sampling clock signal based on a digital signal, and supply a dedicated video signal for phase adjustment from a personal computer.

Abstract: A sync signal correction circuit generates a corrected sync signal which is obtained by correcting a timing of a sync signal on the basis of a time axis variation component (jitter component) of the sync signal separated from a picture signal. The corrected sync signal is used as the sync signal to cause a variation of time axis error of the picture signal to follow a variation of time axis error of an output signal of an automatic frequency control (AFC) circuit which constitutes a monitor device for reproducing and displaying the picture signal, such that the variation of time axis error of the output signal of the AFC circuit and the variation of time axis error of the picture signal of the reproduced picture signal are cancelled each other to prevent jittere from appearing on a display screen.

Abstract: A clock signal generator and method for generating a clock signal which is synchronized with an input composite video signal. The generator comprises a synchronizing separator for separating a horizontal synchronizing signal from an input composite video signal; a burst separator for separating a color burst signal from the input composite video signal; a phase error detector for receiving the horizontal synchronizing signal, detecting a phase error and outputting a phase error signal for a previous horizontal period; a phase change detector for receiving the color burst signal, detecting a phase change of the color burst signal, and outputting a phase change signal for a present horizontal period; an adder for adding the phase error signal and the phase change signal; and a clock signal generator for receiving an output of the adding means and generating a clock signal which is synchronized with the input composite video signal.

Abstract: A slow Phase Locked Loop (PLL) is utilized to prevent an abrupt change to a video display containing multiple images, when the source of the synchronization is changed. Such displays include Picture in Picture (PIP) television systems and computer displays. By appropriate buffering and memory management, visual disruptions can be minimized by slowly synchronizing the display synchronization signals to the new synchronization source. The slow synchronization also produces a less disruptive visual image when the source, or channel, of a single image display is changed, and allows for smooth visual transitions on displays having inertial elements, such as color wheels.

Abstract: In a CRT display and a television set having the same, horizontal/vertical synchronizing signals are separated from a video synchronizing signal in a synchronizing separation circuit, and position information S of a vertical frame is generated on the basis of the horizontal/vertical synchronizing signals in a count-down processor and then converted to corrected vertical frame information W in a function circuit to output a vertical deflection waveform signal and a horizontal deflection correcting waveform signal. Further, the corrected vertical frame information W is compared with predetermined voltages in comparators to detect an effective frame range in the vertical direction.

Abstract: Vertical and horizontal sync signals are separated from an NTSC signal inputted from an outside by an external input circuit and a luminance signal (Y) and chrominance signals (B-Y, R-Y) are extracted and converted into RGB data. External RGB data and RGB data formed by a software are processed and the resultant data is supplied to an output converting circuit. The RGB data is converted into analog signals of the luminance signal and chrominance signals of a television signal by using individual system clock signals and outputted. A clock generating circuit generates two kinds of dot clocks which are used for the output converting circuit. The dot clock which is generated from the clock generating circuit and is used for conversion of the luminance signal is phase matched so as to follow a jitter of a horizontal sync signal (H) separated by an external video input circuit.

Abstract: A QAM/VSB digital receiver is disclosed which includes a source of a QAM/VSB signal. An analog-to-digital converter is coupled to the QAM/VSB signal source, and is further responsive to a sample clock signal. A filter/complement is coupled to the analog-to-digital converter and has a first output terminal which produces a low-pass filtered QAM/VSB signal, and a second output terminal which produces a high-pass filtered QAM/VSB signal complementary to the low-pass filtered QAM/VSB signal. A sample clock generating circuit is coupled to the second output terminal of the filter/complement and produces the sample clock signal in response to the high-pass filtered QAM/VSB signal.

Abstract: A symbol timing recovery circuit and method of a digital television is disclosed including: an analog-to-digital converter (10) for sampling a received analog signal by a symbol clock to be converted to digital data; demodulator (20) for recovering a carrier wave, demodulating the digital data to a baseband signal and generating a segment signal; a segment synchronizing signal detector (40) for detecting a segment synchronizing signal from the segment signal; a phase error detector (50) activated by the segment synchronizing signal, for receiving the segment signal and detecting a phase error of synchronizing symbols of the segment synchronizing signal; and a symbol clock is phase adjuster (60) for adjusting the phase of the symbol clock according to the phase error of the synchronizing symbols to be supplied to the analog-to-digital converter as the symbol clock.

Abstract: When the margin between a write frequency-divided clock signal and a read frequency-divided clock signal becomes remarkably decreased, a clock phase difference detecting circuit outputs a reset execution command. While a reset execution command is being output in a blanking interval, a reset signal generating circuit supplies a reset signal to an input side counter corresponding to a reset execution command so as to reset the phase of the write frequency-divided clock signal to an initial state.

Abstract: A synchronization system aligns video signals without the use of a phase locked loop. One embodiment includes a delay line and a selection circuit. A clock signal with a desired frequency for a pixel clock is applied to the delay line to generate a series of delayed signals at taps on the delay line. When a transition in a horizontal sync signal occurs, the selection circuit senses delayed signals and selects a delayed signal having a transition aligned relative to the transition in the horizontal sync signal. This delayed signal is a pixel clock signal which is not subject to frequency fluctuation of a phase locked loop. Selecting a new delayed signal at each horizontal blanking period keeps the pixel clock for each line of video aligned to the horizontal sync signal.

Abstract: In a video frame grabber for digitizing analog video signals which have a pure analog video signal component and a synchronization signal component, the synchronization signals are digitized along with the pure analog video signals. Video gain and offset, sync gain, and sync threshold can be adjusted electronically. A variable time delay can be imposed on the sampling clock signals and on horizontal reference signals. Optimal values can be determined for the various parameters.

Abstract: An apparatus and method for generating a clock signal phase-locked to a horizontal synchronization signal of a digital video signal in which noise superposed on the horizontal synchronization signal is eliminated or reduced. To eliminate or reduce such noise, a noise suppressing device located prior to a phase comparator may be utilized. Such noise suppressing block may include a slice circuit and/or a spike removing circuit.

Abstract: An H-sync to pixel clock phase detection circuit comprising: a programmable delay line for delaying an H-sync signal; a differential clock driver circuit for producing a pixel clock signal and a pixel clock/signal from a pixel clock signal input; a first D flip-flop having D and CLK inputs and a Q output; a second D flip-flop having D and CLK inputs and a Q output; wherein the delayed H-sync signal from the programmable delay line is applied to the respective D inputs of the first and second D flip-flops, wherein the pixel clock signal from the differential clock driver circuit is applied to the CLK input of the first D flip-flop, and wherein the pixel clock/signal from the differential clock driver is applied to the CLK input of the second D flip-flop; and a third D flip-flop having D and CLK inputs and a Q output; wherein the Q output of the first D flip-flop is applied to the D input of the third D flip-flop, wherein the Q output of the second flip-flop is applied to the CLK input of the third D flip-flop;

Abstract: A periodic multi-bit digital signal is synthesized having a frequency that is specified by the frequency of a periodic reference signal that is asynchronous with respect to a sampling clock of the periodic digital signal. In a digital video system, for example, a digital color subcarrier is synthesized and synchronized to a reference frequency of a crystal oscillator that is asynchronous with respect to a digital system clock for the digital video system. The periodic digital signal is generated by an adjustable digital oscillator clocked by the sampling clock. The frequency or phase of the periodic digital signal is compared to the frequency or phase of the periodic reference signal to produce an adjustment value for adjusting the periodic digital signal to synchronize the periodic digital signal with the periodic reference signal. The digital oscillator, for example, generates the periodic digital signal at the sampling rate by periodically incrementing an accumulator with the adjustment value.

Abstract: A method for producing a digital video signal from an analog video signal, the analog video signal including an analog video data signal that is raster scanned in lines across a CRT screen to form consecutive frames of video information, the raster scanning controlled by use of a horizontal synchronizing signal (H.sub.snyc) that controls a line scan rate, and a vertical synchronizing signal (V.sub.snyc) that controls a frame refresh rate, to produce consecutive frames of video information, wherein the digital video signal is produced by generating a pixel clock signal with pixel clocks for repetitively sampling instantaneous values of the analog video data signal, and digitizing the analog video data signal based on the pixel clock sampling. An expected width E, measured in number of pixel clocks, of a video image producible by the analog video signal is estimated, and an actual width W, measured in number of pixel clocks, of the video image producible by the analog video signal is calculated.

Abstract: In apparatus that measures the characteristics of the read-out signals from memory media, in the prior art, phase control of the clock signals for synchronized sampling of the measurement apparatus was performed by using the read-out signals. Synchronization discrepancies and inability to perform synchronization were produced due to the quality of the read-out signals. In the invention, a Logical processing part generates selection signals that control the selection of samples with phase information, for performing synchronization, from test signals of a recording part, which records the same signal train as the test signal train written onto the memory medium. By the control of these selection signals, samples with phase information for performing synchronization are selected from the sample train output from an A/D converter through an equalizer; these samples pass through a selection part and a control clock generating part by means of the processing of a feed-back processing part.

Abstract: An adaptive clock recovery apparatus.

Abstract: A clock recovery circuit in a digital display unit for recovering a time reference signal associated with analog display data. The clock recovery circuit includes a phase-locked loop (PLL) implemented in digital domain and an analog filter to eliminate any undesirable frequencies from the output signal of the PLL. The PLL includes independent control loops to track long term frequency drifts of the time reference signal and the transient phase differences respectively. By providing such independent control loops, the generated clock can be better synchronized with the time reference signal.

Abstract: A synchronizing signal creating circuit which can feed stable synchronizing signals even after input signals stop. it is constituted of gate circuit 804 makes signal (G) into logic level 1 and outputs to switching circuit 818 when the still picture creating apparatus which executes processing with the synchronizing signals created by synchronizing signal creating circuit 80 executes creation or output of still pictures, and when frame synchronizing signal (IFP) and the frame pulse do not synchronize. Switching circuit 818 selects contact point b and outputs numerical value (V.sub.DC) to digital/analog converting circuit 816 so the operation of PLL loop stops. Consequently, in this case, voltage control oscillating circuit 820 creates signals (HCK) with a frequency corresponding to numerical value (V.sub.DC) and in other cases, creates signals (HCK) with a frequency determined by the operation of the PLL loop.

Abstract: An apparatus and method for accurate synchronization with inbound audio data which packets at relatively low sampling rates. By using previously known information such as the time of arrival of the beginning of the data packet, a reference timer in a digital signal processor can be used to calculate a number of samples and/or portions thereof between a beginning reference time and the beginning of a data packet, and then calculate the timing error between the first sample point after the arrival of the data packet and the beginning of the data packet. Using this information, the actual arrival of the data packet can be derived and utilized to very accurately, within very small margins of error, synchronize the beginning of the data packet with the scrambling algorithm used in the receiver.

Abstract: A video decoder is provided wherein digitized samples of an input video signal are produced at a fixed sampling rate and, from such digitized samples, a fixed number of re-sampled digitized samples are produced for each detected sync pulse included in the video signal. The re-sampled digitized samples are stored in a buffer memory and are retrieved from such buffer memory at a rate synchronized to the sync pulse. With such an arrangement, the analog to digital converter operates at a fixed sampling rate, and overflow situations are avoided.

Abstract: In a video frame grabber for digitizing analog video signals which have a pure analog video signal component and a synchronization signal component, the synchronization signals are digitized along with the pure analog video signals. Video gain and offset, sync gain, and sync threshold can be adjusted electronically. A variable time delay can be imposed on the sampling clock signals and on horizontal reference signals. Optimal values can be determined for the various parameters.

Abstract: In a video frame grabber for digitizing analog video signals which have a pure analog video signal component and a synchronization signal component, the synchronization signals are digitized along with the pure analog video signals. Video gain and offset, sync gain, and sync threshold can be adjusted electronically. A variable time delay can be imposed on the sampling clock signals and on horizontal reference signals. Optimal values can be determined for the various parameters.

Abstract: A method for producing a digital video signal from an analog video signal, the analog video signal including an analog video data signal that is raster scanned in lines across a CRT screen to form consecutive frames of video information, the raster scanning controlled by use of a horizontal synchronizing signal (H.sub.sync) that controls a line scan rate, and a vertical synchronizing signal (V.sub.sync) that controls a frame refresh rate, to produce consecutive frames of video information, wherein the digital video signal is produced by generating a pixel clock signal with pixel clocks for repetitively sampling instantaneous values of the analog video data signal, and digitizing the analog video data signal based on the pixel clock sampling. An expected width E, measured in number of pixel clocks, of a video image producible by the analog video signal is estimated, and an actual width W, measured in number of pixel clocks, of the video image producible by the analog video signal is calculated.

Abstract: The process consists in carrying out, via a phase-locked loop controlling a clock frequency, a slaving of a comparison signal to the falling edge of the line synchronization pulse, in decoding at the output of a dot counter integrated into the loop and controlled by the clock, on the one hand a value N triggering the comparison signal and corresponding to a specified position inside the line synchronization pulse relative to its falling edge, on the other hand values triggering the rezeroing of the counter and time signals synchronous with the clock and clocking the digital processing of the video signals sampled at the clock frequency.

Abstract: A dual VCO phase-locked loop in which one VCO forms part of a standard phase-locked loop, the VCO being controlled by a loop control voltage and its output being divided and compared with an input reference signal for maintaining lock. A second VCO is indirectly controlled by the loop control voltage and tracks the output of the first VCO within .+-.5% over combined variations in power supply voltage from 3.0 V to 3.6 V, in ambient temperature from 20.degree. C. to approximately 125.degree. C., and in manufacturing process variations over 5 process corners (typical, fast-fast, slow-slow, slow-fast and fast-slow). A control current is developed for the VCO forming part of the closed loop and is coupled to the second VCO using a current mirror. An offset current is combined at the second VCO with the coupled control current. The offset current is intentionally made a compensating function of the variations in power supply voltage, ambient temperature and manufacturing process.

Abstract: An apparatus and method are provided for automatically adjusting a pixel sampling clock frequency and phase of a video display to match the frequency and phase of a pixel clock used to generate an incoming video signal being received by the video display. Voltage transitions are detected between pixel intensities in a video signal. The voltage transitions are compared with pixel sampling clock pulse signals of the video display in order to correctly match the frequency and phase of the video signal, and thus produce a more stable and noise-free image on the video display.

Abstract: A method and system for synchronizing to an incoming Hsync signal, and for generating a phase locked clock signal in response thereto. The Hsync signal and an incoming clock are coupled to a sequence of modules. Each module includes a latch for sampling the incoming clock on a transition of the Hsync signal, whose output is combined (using an XOR gate) with the Hsync signal. Each module includes a time delay for generating a delayed clock signal, incrementally delayed from the previous module in the sequence, so that the clock signal for each module is phase-offset from all other modules. The latch outputs are summed using a resistor network, to produce a triangle-shaped waveform which is phase locked to the Hsync signal and which is frequency locked to the incoming clock. The triangle-shaped waveform is compared with a constant voltage to produce a square wave.

Abstract: In a video frame grabber for digitizing analog video signals which have a pure analog video signal component and a synchronisation signal component, the synchronisation signals are digitized along with the pure analog video signals. Video gain and offset, sync gain, and sync threshold can be adjusted electronically. A variable time delay can be imposed on the sampling clock signals and on horizontal reference signals. Optimal values can be determined for the various parameters.

Abstract: A CRT display device capable of displaying a signal from the existing image signal source, in which a vertical frequency is approximately fixed and a horizontal frequency is widely distributed beyond a ratio of 3:1, on one image screen. The CRT display device includes a scan converter unit and a display unit. The scan converter unit includes an output horizontal frequency unifying circuit, a horizontal blanking period ratio converting circuit, a vertical frequency converting unit and a vertical blanking period ratio converting circuit. The display unit includes a vertical deflection circuit and a circuit for correcting a vertical S-shaped distortion. In a phase synchronous circuit, a lock-out detector is connected to an output of a three state output digital phase detector, and on the basis of an output thereof, a switch is subjected to the "ON"/"OFF" control.

Abstract: A system and method for jointly determining initial tap coefficients for a maximum likelihood sequence estimating equalizer and a timing error of an incoming signal, in one embodiment, receives the incoming signal into a receiver, and locates a known portion within a time frame of the incoming signal. The known portion is compared with a stored representation of the known portion, and with a stored representation of a derivative of the known portion. The initial tap coefficients and timing error of the incoming signal are jointly determined based on the comparing of the known portion with the stored representations, and a subsequent known portion is located within a subsequent time frame of the incoming signal based on the timing error. The initial tap coefficients are passed to a maximum likelihood sequence estimating equalizer.

Abstract: A television signal receiver for processing an HDTV signal transmitted in a vestigial sideband (VSB) format with a one-dimensional data constellation includes a first carrier recovery network (18), an equalizer (20), and a second carrier recovery network (22, 30, 62). A multiple stage quantizer network (50, 66) exhibiting progressively finer resolution is associated with the operation of the equalizer for providing blind equalization without need of a "training" signal. The second carrier recovery network includes a phase detector (30) wherein a one-symbol delayed (312) input signal and a quantized (310) input signal are multiplied (316), and an unquantized input signal and a quantized (310) one-symbol delayed (314) input signal are multiplied (316), and an unquantized input signal and a quantized (310) one-symbol delayed (314) input signal are multiplied (318). Signals produced by the multiplication are subtractively combined (320) to produce an output signal representing carrier phase error.

Abstract: A motor control unit (15c) for synchronizing a color wheel (15) to an incoming video signal and for re-synchronizing the color wheel after a channel change. The motor control unit (15c) has an error control unit (31), which detects an out-of-phase condition, and derives a color wheel sync signal from the pixel sample clock adjusted by any phase error. A drive unit (33) phase locks this sync signal to an index signal provided by the color wheel. The result is a tightly controlled re-synchronization that minimizes perceived effects.

Abstract: It is an object of the present invention to restrict EMI radiation at a specific frequency by inserting a delay time that is effective for that frequency. The feature of the present invention is to provide a delay generator that can selectively alter delay times. The delay generator comprises: delay means, which is connected to a plurality of data input lines, and which has a plurality of delay paths for the generation of a plurality of alternative delay times; a register for storing a digital value of pre-determined bit; and selection means for selecting one of the delay paths in consonance with the digital value and for providing the selected delay path for the signal lines.

Abstract: A video clock input signal is applied to a delay line comprising a cascade connection of a plurality of delay elements formed in an integrated circuit for providing a plurality of delayed clock signals at respective taps of the delay line. A selection circuit, responsive to a horizontal synchronizing signal supplied thereto, couples a selected one of the taps to an output for providing a delayed output clock signal that is edge-aligned with the synchronizing signal. For reducing the number of taps required to provide a given minimum delay step resolution and a given minimum total delay for delay elements which may vary in delay, from one integrated circuit to another, the taps are spaced one element apart for a first group of the delay elements and are spaced more than one element apart for at least one second group of the elements.

Abstract: A tuner selects one of channels at different locations in a frequency band used for transmitting VSB HDTV signals including symbol codes descriptive of digital signals. The tuner also includes mixers for performing plural conversion of the selected channel to a final intermediate-frequency signal, which is digitized by an analog-to-digital converter. A phase tracker, operative on narrow-bandpass filtered portions of the digitized final intermediate-frequency signal centering on its carrier frequency, suppresses an imaginary portion of the final intermediate-frequency signal, arising from multipath distortion or from phase incoherence in local oscillations used during frequency conversion(s).

Abstract: An effective video interval detector detects an effective video interval of a digital video signal from an A/D converter, and outputs differential data indicative of the difference between the detected effective video interval and a required video data interval. A video signal supply interval controller produces frequency-dividing ratio control data depending on the differential data supplied thereto and supplies the frequency-dividing ratio control data to a programmable frequency divider to vary its frequency-dividing ratio. An output signal frequency from a voltage-controlled oscillator is now controlled to eliminate the difference between the effective video interval and the required video data interval.