Abstract: Successive pixels representing video data in successive lines in a raster scan are buffered. Each of the lines has a sync pulse defining the line beginning. A phase adjustment is determined between the sync pulse, preferably at a particular level in the sync pulse, and an adjacent one of system adjacent clock signals at a particular frequency. The actual or expected phase adjustment between the pixels at the end of each line is also determined. The difference between the phase adjustments at the beginning and end of each line is then determined. Progressive adjustments are made in the phase of each successive pixel in the line relative to the system clock signals in accordance with the number of system clock signals in the line and the determined difference in the phase adjustment between the line beginning and end. In this way, the pixels of video data are synchronized with the system clock signals.

Abstract: The present invention is a system for inexpensive phase coherent subcarrier generation. The subcarrier sequence has a fairly short periodicity (two lines), allowing a relatively short lookup table to hold coded values precisely representing the sampled subcarrier. A variety of modulation techniques may be employed to minimize the error between the reconstructed subcarrier sine wave and an "ideal" subcarrier sine wave. The SCH phase may be easily varied by using a different table of subcarrier sine wave values.

Abstract: Disclosed herein is an oscillator circuit used for a PIP system which displays a child picture image without distortion even when the image method of the child picture image is different from that of a parent picture image. The oscillator circuit employed in such a system includes a programmable frequency divider for frequency dividing an output of a voltage-controlled oscillator with a frequency dividing ratio to produce a frequency-divided signal and a control circuit for controlling the oscillation frequency of the oscillator 201 according to a phase difference between the frequency-divided signal and a horizontal synchronizing signal. The frequency dividing ratio for the frequency divider is changed according to the image method of the child picture image.

Abstract: A color television signal, digitized by a sampling clock asynchronous with respect to the television signal's horizontal synchronizing pulses, is applied to a dynamically programmable digital filter which upsamples or downsamples the received digitized television signal over short time periods in response to time-base disturbances in the signal. The user may also select a higher or lower long-term clock frequency. Resampled digital samples are applied to a FIFO memory for readout at a clock rate which follows the time-averaged horizontal frequency of the received digitized television signal, or, alternatively, at a substantially fixed clock rate, asynchronous with respect to the horizontal line frequency of the received digitized color television signal.

Abstract: Only the data sampled by a correct sampling clock is data processed. A PLL circuit 5 generates a sampling clock locked with a sync signal in a video signal and supplies to a sampling circuit 4. A lock flag indicating whether the generated sampling clock is correctly synchronized with the sync signal or not is also generated. The data multiplexed to the sync signal is sampled by the above sampling clock. The data is stored in a memory 7. The lock flag is supplied to a controller 2 and the data that is outputted from the memory 7 is made valid or invalid according to the level of the lock flag.

Abstract: A composite synchronization extraction circuit is particularly suited for receiving composite video signals containing closed captioning data in raster scan line 21 by means of a signal CMOS integrated circuit device. A dual mode voltage clamp is realized in CMOS technology. The clamp includes temperature compensated current sources in the form of complementary current mirrors through which a clamped composite synchronization node of is charged and discharged, the output of which controls a transistor for charging the composite synchronization node. Detected pulse amplitude is set by slicing the incoming pulse at the back porch level and then doubling the amplitude with an amplifier and comparing that level with the back porch level as derived from a sample-and-hold device. The slice voltage level is maintained without an off-chip capacitor by an analog-digital-analog conversion process.

Abstract: An apparatus for generating a clock signal phase-locked to a sync signal of a video signal. The apparatus comprises an error detector for detecting a phase error between the sync signal of the digitized video signal and a comparison signal produced internally; a clock signal generator whose oscillation frequency is variably controlled in response to the output of the error detector; a counter for counting the output of the clock signal generator; and a circuit for producing the comparison signal in response to the count value of the counter. The phase error is detected by integrating the level data of the digitized video signal, and the output of the error detector is replaced with a fixed value when the comparison signal has a predetermined phase. The apparatus is capable of preventing occurrence of a great phase error even at a head switching time or during the vertical blanking interval, so that mislock is preventable and a pull-in action can be executed fast.

Abstract: In order to enable sampling of high definition still video signals in addition to common video signals, a function is added for sampling video signals with every other plurality of picture elements as an interval to an image processing apparatus without using a sampling circuit which requires high speed operations. The invention is also intended to change over between two circuits that is, a circuit for using a picture element clock regenerated by a PLL circuit as a sampling clock for analog to digital converters and a circuit for using a clock obtained by dividing the picture element clock as a sampling clock for the analog to digital converters to sample video signals with every other plurality of picture elements as an interval. Thus, it is possible to carry out sampling of high definition video signals with high frequencies in addition to common video signals without necessity of raising the operating speed of the sampling circuit.

Abstract: A dot clock generation system has a voltage-controlled oscillator (VCO) for generating a dot clock signal for an analog-to-digital convertor (ADC). A dot clock synchronization (sync) generator counts cycles of the dot clock signal and generates a dot clock sync signal. An analog video signal is passed through a first differential buffer to create an analog video sync signal. The analog video sync signal is passed through a first flip-flop storage element to a phase detector. The dot clock sync signal is passed through a second storage element and then through a second differential buffer to the phase detector. The second storage buffer insures that the edge of the dot clock sync signal which is used by the phase detector is tightly tied with the sampling edge of the dot clock signal which is used by the ADC to sample the analog data within the analog video signal.

Abstract: Direct synthesis of a digital audio sample clock from a digital video sample clock is achieved by using a numerically controlled oscillator driven by the digital video sample clock. A phase accumulator increments a phase increment at the frequency of the digital video sample clock, the phase increment being a function of a desired frequency for the digital audio sample clock, the frequency of the digital video sample clock and the bit precision of the accumulator. The accumulated phase output from the accumulator is converted into a sine wave signal at the desired audio frequency from which the digital audio sample clock is derived.

Abstract: An apparatus for correcting a time base of a video signal generates a clock which is phase-synchronized with a sync. signal of the video signal and has the same frequency. In a special reproducing mode, the apparatus switches an output level of a phase comparator, which phase-compares the sync. signal and the clock to a predetermined level, which is applied to a controlled oscillator and resets a frequency divider which frequency-divides the output of the controlled oscillator, in accordance with the sync. signal to produce the video signal which can be visually recognized even in the special reproducing mode. The apparatus samples and holds the output level of the phase comparator when the video signal drops out and resets the frequency divider which produces the clock by frequency-dividing the output of the controlled oscillator, when the dropout is recovered so that a video signal of high quality is produced immediately after the recovery of the dropout of the video signal.

Abstract: Circuit arrangement for demodulating a video signal (IF signal) which is frequency-modulated on an intermediate-frequency carrier oscillation, including a first demodulation stage (a frequency or phase demodulator) for multiplicatively combining the IF signal with a carrier oscillation of a controllable oscillator and for supplying a first output signal, a second demodulation stage (a frequency or phase demodulator) for multiplicatively combining the IF signal with the carrier oscillation phase-shifted by a quarter period of the intermediate-frequency carrier oscillation, and for supplying a second output signal, a first filter stage for low-pass filtering the first output signal and for supplying a third output signal, a multiplier stage for multiplicatively combining the second output signal and the third output signal to form a fourth output signal, a superposition stage for forming a seventh output signal by additively combining a fifth output signal and a sixth output signal derived from the second outpu

Abstract: Digital data having a symbol rate that is a multiple of horizontal scan rate are buried in broadcast television signals. In a digital signal receiver the data are separated from composite video signal by quadrature video detection followed by comb filtering. The comb filtering is most economically realized by digital sampling at symbol rates. The regeneration of clocking signals at symbol rate, and at multiples of symbol rate where oversampling analog-to-digital conversion (ADC) techniques are employed, is done using a controlled oscillator with automatic frequency and phase control (AFPC) responding to the horizontal synchronizing pulses transmitted in the broadcast television signals. The horizontal synchronizing pulses are usually much larger than noise, so the controlled oscillator frequency and phase is rapidly adjusted following energization or channel change of the digital signal receiver.

Abstract: A digital time base corrector which can perfectly eliminate residual errors. A sync clock signal whose phase is synchronized with a time base fluctuation included in a reproduction video signal is formed in accordance with at least one of the horizontal sync signal and the color burst signal which are separated from a reproduction video signal. The sync clock signal is phase-modulated in accordance with a burst error signal indicative of the time base fluctuation of the color burst signal in a period of time other than the generating period of time of at least the color burst signal in the reproduction video signal, thereby obtaining a write clock signal of the image memory.

Abstract: In a system which encodes video data in response to an encoding clock, transmits the encoded video data with an encoder clock signal representing the encoding clock frequency, and decodes the video data in response to a decoding clock, system clock accuracy is maintained by adjusting the decoding clock frequency. In order to reduce buffer requirements and to prevent deterioration of video program presentation, the decoding clock frequency is adjusted by slewing only during composite video synchronization periods when composite video decoded from the encoded video stream is not being presented. The preferred video synchronization periods are the vertical blanking interval and the front porch period. Restriction of decoding clock rate adjustment to these periods ensures that decoding clock slew rate limits may be unrestricted, thereby avoiding noticeable effects in the video program presentations.

Abstract: A multi-phase, multi-access pipeline memory system includes a number, n, of processors; a pipeline memory including a latch; and a bus for interconnecting the processors and pipeline memory; a clock circuit responsive to a system clock signal divides the system clock signal into n phases for providing multiple clock signals corresponding to the n phases of the system clock signal for operating each processor to allow data and address to be transferred only during its assigned phase thereby enabling the memory and each processor to operate at the system clock rate while allowing n accesses to the memory during each system clock signal period, one access for each processor.

Abstract: This specification concerns signal processing apparatus for processing line synchronization pulses in a line synchronization signal that define an analog video signal line period. The apparatus comprises a phase locked loop (40) for generating a clock signal of a frequency that is a multiple of the line synchronization signal frequency. The phase locked loop (40) comprises a counter (100) for dividing the clock signal by said multiple. The apparatus further comprises logic (110,50) for resetting the counter (100) upon detection of a spurious pulse introducing a time interval into the line synchronization signal of less than the line period of the video signal. The apparatus is particularly useful in image processing systems for digitizing analog video signals that have been replayed via a conventional, domestic video tape player, and therefore may comprise spurious line sync pulses introduced by playback head skip.

Abstract: A decoder circuit for receiving a video input signal which includes Manchester coded data bits and a range tone component having a frequency of about 102.6 kilohertz. A phase lock loop circuit detects the presence of the 102.6 kilohertz range tone component and then generates a system clock signal which is phase locked to the range tone component of the video input signal. The system clock signal is provided to a clock generating circuit which generates a clock signal having four phases. The phase lock loop circuit also provides a logic signal which is supplied to a data detecting circuit allowing the data detecting circuit to convert the Manchester coded data bits to digital data bits.

Abstract: A circuit for synchronizing an operating clock of a switching power supply (SPS) system is provided. The SPS has an oscillator, a primary control circuit, a secondary voltage generation circuit, a feedback control circuit. The oscillator outputs an oscillation signal to the primary control circuit. The feedback control circuit, in response to a direct current (DC) voltage from the secondary voltage generation circuit, generates a DC feedback voltage signal. The synchronization circuit comprises an isolation device, a signal separation circuit and a triangle-wave generation circuit. The isolation device has an input terminal and an output terminal. The input terminal receives a horizontal synchronization signal and the DC feedback voltage signal. A mixed signal is generated at the output terminal as a result of amplitude-modulating the DC feedback voltage signal by the horizontal synchronization signal. The input terminal is voltage-isolated from the output terminal.

Abstract: A phase compensating circuit in a video signal processing system utilizing a frequency folding technique which requires the recovery of an exact sampling phase is disclosed. A predetermined pattern is inserted during an encoding operation, and the frequency of the inserted pattern is discriminated during a decoding. During this process, when a comparison is made as to whether the original phase lies at the front or at the rear of the received phase, the comparison is not made with an exact value, but with a predetermined range of values by taking into account the inherent variability in delay values, for example, due to temperature variations, of delaying devices of a clock adjusting part. In this regard, the sum total of the delays of the delaying devices is made to include one clock period by taking into account the temperature characteristics of the delaying devices, with the result that clocks having a relatively exact phase can be generated based on the pattern inserted during an encoding.

Abstract: An apparatus, such as an adaptive flywheel, and method for producing periodic time references, forming a periodic time reference signal, from uncertain time references. A counter counts from a first count value to a second count value and provides a periodic time reference each time its count reaches the second count value. An error processing device, coupled to the counter, determines (a) whether an uncertain time reference is received within a predetermined range of count values (corresponding to a window of expectation), or (b) whether the absolute value of the average of an error, corresponding to the number of increment values before or after the second count value, whichever is lower, the count is at when an uncertain synchronization reference is received, and at least one previously determined error for at least one previously received uncertain synchronization reference is greater than WC/2 increment values.

Abstract: A frequency controlled clock circuit for use in a television receiver utilizes a detected sound intermediate frequency (IF) signal for use in controlling a voltage controlled oscillator and thereby provide immunity from ghost signals in the transmitted video signal. A phase locked loop responds to phase errors detected from the voltage controlled oscillator and a reference signal from the sound IF signal to control the frequency of the voltage controlled oscillator.

Abstract: A digital television signal includes data sent as multilevel symbols in successive data segments each including a synchronizing sync character. The detected synchronizing sync character produces a characteristic having two opposite polarity levels separated by a zero reference level, with the levels occurring at successive sampling points of the television signal, and a detection signal that has a peak occurring in time coincidence with the zero reference level. The detection signal controls sampling of the received television signal. The gain of the received signal is controlled by an AGC circuit that also responds to the detection signal.

Abstract: A solid state image pickup apparatus includes a solid state image pickup device for receiving an optical image of an object and generating an electrical image signal representing the optical image of the object in synchronism with a driving pulse from a driving circuit. A sampling circuit generates a sampled image signal by sampling the electrical image signal read out of the solid state image pickup device with a first sampling pulse from a first pulse circuit synchronized with the driving pulse. An analog-to-digital convertor converts the sampled image signal to a digital image signal with a second sampling pulse from a second pulse circuit. A test signal generator generates a test signal which is synchronized with the driving pulse and alternately changes in level between consecutive pixels. A controller controls the phase of the first sampling pulse and the phase of the second sampling pulse relative to each other by processing the test signal.

Abstract: Successive pixels representing video data in successive lines in a raster scan are buffered. Each of the lines has a sync pulse defining the line beginning. A phase adjustment is determined between the sync pulse, preferably at a particular level in the sync pulse, and an adjacent one of system adjacent clock signals at a particular frequency. The actual or expected phase adjustment between the pixels at the end of each line is also determined. The difference between the phase adjustments at the beginning and end of each line is then determined. Progressive adjustments are made in the phase of each successive pixel in the line relative to the system clock signals in accordance with the number of system clock signals in the line and the determined difference in the phase adjustment between the line beginning and end. In this way, the pixels of video data are synchronized with the system clock signals.

Abstract: A color signal reproducing circuit comprising a phase correction device receiving a gain-controlled composite color signal, detecting color burst signal in a composite color signal and correcting phase of the color burst signal by using a 3.58 MHz signal, first gate for receiving the gain-controlled composite color signal and passing only a color signal when a color burst pulse in the delayed horizontal synchronizing signal applied from the delay device is at a low level, and mixer for mixing the phase-corrected color burst signal and the color signal from the first gate to produce a phase-corrected composite color signal.

Abstract: The synchronization method realizes synchronization of a digital input data signal with a digital clock signal with which the data signal is rate synchronous. The method consists in sampling the input signal, grouping these samples in successive sets of a plurality of successive ones of the samples, detecting in each of the sets possible value transitions of the samples, determining for each current transition in a set the theoretical position thereof in a corresponding set assumed to be obtained by sampling a nominal data signal which is the input data signal but with pulses having a width equal to the width of the clock signal period, and using the latter theoretical position and the end value of the transition to generate the synchronized input data signal.

Abstract: A phase control circuit, which can be operated easily, automatically controls the phase of a video signal and a sampling clock signal. A delay circuit (24) outputs delayed clock pulses (DP) that are out of phase with each other, and switching circuits (25a.about.25c) select one, at a time, of the delayed clock pulses (DP) that are out of phase with each other in response to respective switching signals (SS1.about.SS3) from a control circuit (23), Counters (28a.about.28c) count pixel data (ED) latched by data latch circuits (26a.about.26c) each time the delayed clock pulses (DP) are outputted by the corresponding switching circuits (25a.about.

Abstract: Apparatus and method are provided which receive and sample an incoming video image signal asynchronously, and then processes the signal to recover the video image, including video format, for conversion into a preselected video format. The apparatus and methods first sample the video signal using a stable (crystal oscillator) time base clock to reconstruct the frequency of the video signal, i.e., to recover the video format and then using a contrast optimization process to determine the video signal pixel clock rate.

Abstract: An apparatus for compensating a time base error of a video signal. A reference signal of no time base error is generated. A difference between a frequency of the reference signal and a frequency of a horizontal synchronizing signal included in an input analog video signal is detected and then a difference signal is outputted. In response to the difference signal, a phase of the reference signal is controlled. The video signal is sampled, based on the reference signal the phase of which is controlled, thus the video signal is converted into a digital signal in which the difference is cancelled. The digital signal is stored in a memory. And the stored digital signal is read out, based on the reference signal.

Abstract: A video signal conversion system converts input video signals in a studio format, such as CCIR 601 (625/25), into output video signals in another format, such as the Phase Alternate Line (PAL) format. The horizontal line scanning frequency of the input and output signals is the same. The signal conversion system uses an output clock signal to determine the relative timing of the input and output video signals. This signal is generated by a phase-locked loop which employs a crystal-controlled VCO. The phase of the signal produced by the VCO is adjusted to maintain the sampling clock signals of the input and output video signals in a predetermined phase relationship. The phase error signal which is used to control the VCO is generated by comparing a first phase reference signal, generated from the output signal, to a second phase reference signal generated from the input signal.

Abstract: Disclosed is a video camera apparatus including a video camera for generating a video signal and a camera control unit for generating a control signal for controlling the video camera. The camera control unit includes a video signal receiver, a video/reference signal phase comparator, a phase difference signal transmitter, a video signal memory, and write and read clock signal generators. The video camera comprises a phase difference signal receiver, a synchronizing signal generator, a synchronizing signal phase controller, an image pickup device and a video signal transmitter. In this setup, the output video signal is generated under stable genlock control for radio communication between video camera and camera control unit.

Abstract: In a clock generator circuit, a zero hold circuit produces from a fixed clock signal a zero hold clock signal which is in phase with an external sync signal. A phase comparator circuit produces phase difference data indicating the phase difference between the external sync signal and an internal sync signal. A counter cleared by the external sync signal counts pulses of the zero hold clock signal to obtain count data. A memory receiving the phase difference data and the count data as its address input produces the internal sync signal when the count data is smaller than the number of pulses in one cycle of the external sync signal having no time-base variations, and a phase control signal determined by the phase difference data and the count data. A phase shifter shifts the phase of the zero hold clock according to the phase control signal to obtain a modified clock signal synchronized with the external sync signal.