Abstract: A circuitized substrate for mounting at least one electronic component having a plurality of terminals. The circuitized substrate includes a first portion of electrical insulating material embedding a first electric circuit for coupling a first subset of the terminals. The first electric circuit including one or more patterned conductive layers of electrically conductive material extending parallel to a plane of the circuitized substrate. The circuitized substrate further includes a second portion of electrically conductive material. One or more insulating elements of electrical insulating material cross the second portion transversally to the plane to insulate a plurality of conductive elements thereof for coupling a second subset of the terminals. One or more auxiliary components of the electronic component are mounted on the second portion. Each auxiliary component having a first terminal and a second terminal coupled with a first one and a second one, respectively, of a pair of the conductive elements.

Abstract: A power inverter circuit includes a capacitor and a power module. The capacitor includes a positive plate and a negative plate that are spaced apart along opposing sides of the capacitor and extend toward each other along a common side of the capacitor. The power module includes a positive connector and a negative connector that are connected to the positive plate and the negative plate, respectively, and are spaced apart and extend parallel across from each other.

Abstract: A multilayer electronic component includes a multilayer capacitor including a pair of external electrodes respectively formed on both ends opposing each other, and a pair of frame terminals having coupling holes allowing the external electrodes of the multilayer capacitor to be inserted, and separating the multilayer capacitor from a mounting surface, wherein band portions of the external electrodes are bonded to inner surfaces of the coupling holes.

Abstract: An electronic component includes a multilayer capacitor, including a capacitor body, and a pair of external electrodes disposed on both ends of the capacitor body, respectively, and an interposer, including an interposer body, and a pair of external terminals disposed on both ends of the interposer body, respectively. The pair of external terminals include bonding portions disposed on a top surface of the interposer body, mounting portions disposed on a bottom surface of the interposer body, and connection portions disposed on end surfaces of the interposer to connect the bonding portions and the mounting portions to each other. The mounting portions have lengths greater than lengths of the bonding portions in a direction of connection of the pair of external terminals.

Abstract: There is disclosed a multi-band reconfigurable antenna device having at least one radiating element. The radiating element is connected to a single port by way of at least first and second matching circuits arranged in parallel. A high pass filter is provided between the first matching circuit and the radiating element so as to allow passage of a first, higher frequency RF signal through the first matching circuit. A low pass filter is provided between the second matching circuit and the at least one radiating element so as to allow passage of a second, lower frequency RF signal through the second matching circuit. The high pass filter blocks passage of the second, lower frequency RF signal through the first matching circuit, and the low pass filter blocks passage of the first, higher frequency RF signal through the second matching circuit. The first and second matching circuits are adjustable independently of each other so as to allow the first and second RF signals to be tuned independently of each other.

Abstract: A galvanic isolator includes a multi-layer printed circuit board (PCB) including a dielectric material having a top side and a bottom side. An RF transmission line is embedded within the PCB including a plurality of conductor traces spaced apart from one another to include a plurality of gaps (G1 and G2) in a path of the RF transmission line to provide an inline distributed capacitor that together with an impedance of the RF transmission line forms a bandpass (BP) filter. A top metal layer is on the top side and a bottom metal layer on the bottom side connected to one another by a plurality of metal filled vias on respective sides of the RF transmission line. The top metal layer and bottom metal layer each also include at least one gap.

Abstract: A multilayer electronic component includes: a capacitor body including an active region including first and second internal electrodes and upper and lower cover regions; first and second external electrodes including first and second connected portions connected to the first and second internal electrodes and first and second band portions, respectively; and first and second bump terminals having conductive layers and disposed on the first and second band portions, respectively, wherein BW/3?G?BW and T/5<ET<T/2, where BW is a width of each of the first and second band portions, T is a thickness of each of the first and second connected portions, G is a width of each of the first and second bump terminals, and ET is a thickness of each of the first and second bump terminals.

Abstract: A ceramic electronic device includes a chip component, a metal terminal, and a conductive connection member. The component includes a terminal electrode surface on which a terminal electrode is formed. The metal terminal includes an opposing surface to the electrode surface. The connection member contains at least Sn and Sb and connects the terminal electrode surface and the opposing surface. The connection member includes a first part and a second part. In the first part, a distance between the terminal electrode surface and the opposing surface is a first distance, and Sb/Sn is a first value. In the second part, a distance between the terminal electrode surface and the opposing surface is a second distance being smaller than the first distance, and Sb/Sn is a second value being larger than the first value.

Abstract: In an embodiment, a multilayer ceramic capacitor 10 is constituted in such a way that its capacitor body 11 houses a capacitance part which is halved in the third direction d3, along a shared internal electrode layer 11a3 serving as a boundary, into a high-capacitance part HC and a low-capacitance part LC. When the capacitor body 11 is cut along a surface crossing at right angles with the first direction d1, the revealed cross-sectional shape of the shared internal electrode layer 11a3 has a cross-sectional shape where a curved part CP that projects toward the dielectric layer 11b2 on low-capacitance part LC side adjoining the shared internal electrode layer 11a3, is present on both sides in the second direction d2, and also in between.

Abstract: A fan-out semiconductor package includes a core member having a through-hole in which a semiconductor chip is disposed. The semiconductor chip has an active surface having connection pads disposed thereon and an inactive surface opposing the active surface. An encapsulant encapsulates at least a portion of the semiconductor chip. A connection member is disposed on the active surface of the semiconductor chip and includes a redistribution layer electrically connected to the connection pads of the semiconductor chip. A passivation layer is disposed on the connection member. The fan-out semiconductor package further has a slot spaced part from the through-hole and penetrating through at least a portion of the core member or the passivation layer.

Abstract: A ceramic electronic component includes a body including a dielectric layer and first and second internal electrodes disposed to oppose each other with the dielectric layer interposed therebetween, first and second external electrodes each including a connection portion disposed on a side surface of the body and a band portion extending from the connection portion to portions of upper/lower and front/rear surfaces of the body, first and second resin layers each disposed between the band portion and the body and extending from an end of the band portion towards each side surface by a predetermined length, in which the predetermined length is within a range of 3 ?m to 200 ?m.

Abstract: A dielectric film for a film capacitor includes a center portion made of a polymer and composite oxide particles and end portions made of only a polymer. The end portions are provided on both sides of the center portion.

Abstract: A multilayer ceramic capacitor includes a laminate in which dielectric layers and internal electrodes are alternately stacked, and a pair of external electrodes provided on the corresponding surfaces of the laminate. The laminate includes first and second principal surfaces facing each other in its thickness direction, first and second end surfaces facing each other in its lengthwise direction, and first and second side surfaces facing each other in its width direction. The external electrodes each include a metal layer covering the internal electrodes extended to the corresponding one of the end surfaces, a baked layer including glass and metal covering the metal layer, and a plated film covering the baked layer.

Abstract: A multi-layer component having a main body including a stack of alternately arranged dielectric layers and internal electrode layers. In an insulation region on the outer sides of the main body a length of a connecting line between adjacent internal electrode layers of unlike polarity is greater than a direct distance between the adjacent electrode layers. A method for producing a multi-layer component is also provided. The method includes providing a main body including a stack of alternately arranged dielectric layers and internal electrode layers. The method also includes extending the connecting line between adjacent internal electrode layers of unlike polarity on the outer sides of the main body.

Abstract: An electronic component includes a laminated body including first and second end surfaces, first and second side surfaces, and first and second principal surfaces, a first fired electrode layer on the first end surface, and a second fired electrode layer on the second end surface; a first external electrode on the first end surface; and a second external electrode on the second end surface. The first external electrode includes a first fired electrode layer, the second external electrode includes a second fired electrode layer, each of the first and second fired electrode layers includes a first region on the laminated body and a second region covering the first region, the first region includes voids and glass, and the second region includes less voids and glass than in the first region.

Abstract: A decoupling capacitor includes: two capacitor cells sharing the same well; a first trench isolation passing through the well between the two cells without reaching the bottom of the well; and a contact with the well formed in each cell.

Abstract: A multilayer ceramic capacitor that includes a multilayer body with dielectric layers and inner electrode layers and having a first main surface, a second main surface, a first side surface, a second side surface, a first end surface, and a second end surface; and an outer electrode on at least one of the end surfaces. The outer electrode includes a resistor layer on the at least one end surface of the multilayer body, a conductive layer on the resistor layer, and a plating layer on the conductive layer. The resistor layer contains a metallic phase, glass, and an oxide, and the resistor layer has a metallic phase content of 7.5 vol % to 15.6 vol % relative to an area of a section of the resistor layer, and the metallic phase has an average particle size of 1.6 ?m or less.

Abstract: A capacitor-type power supply unit including: a positive bus to which a plurality of capacitor is connected in parallel at each positive-electrode terminal thereof with maintaining equal intervals therebetween, and extends in a parallel direction; and an negative bus to which the plurality of capacitor is connected in parallel, at each negative-electrode terminal thereof with maintaining equal intervals therebetween, and extends in the parallel direction, in which the positive bus has a positive-electrode-side external connection part that is set at a position (SD) separated from the positive-electrode first end by a range of 20% to 30% of the total length in the longitudinal direction thereof, and the negative bus has an negative-electrode-side external connection part that is set at a position (SD) separated from the negative-electrode second end by a range of 20% to 30% of the total length in the longitudinal direction thereof.

Abstract: An item may include fabric having insulating and conductive yarns or other strands of material. The conductive strands may form signal paths. Electrical components can be mounted to the fabric. Each electrical component may have an electrical device such as a semiconductor die that is mounted on an interposer substrate. The interposer may have contacts that are soldered to the conductive strands. A protective cover may encapsulate portions of the electrical component. To create a robust connection between the electrical component and the fabric, the conductive strands may be threaded through recesses in the electrical component. The recesses may be formed in the interposer or may be formed in a protective cover on the interposer. Conductive material in the recess may be used to electrically and/or mechanically connect the conductive strand to a bond pad in the recess. Thermoplastic material may be used to seal the solder joint.

Abstract: A first outer electrode and first inner electrodes are supplied with an anode potential and a second outer electrode and second inner electrodes are supplied with a cathode potential when a monolithic ceramic capacitor is mounted and in use. The first outer electrode supplied with the anode potential has a thickness that is greater than a thickness of the second outer electrode supplied with the cathode potential.

Abstract: A multilayer ceramic capacitor (MLCC) includes a body including first dielectric layers and second dielectric layers, the body including first to sixth surfaces, a second surface, a third surface, a fourth surface, a fifth surface and a sixth surface; first internal electrodes disposed on the first dielectric layers, exposed to the third surface, the fifth surface, and the sixth surface, and spaced apart from the fourth surface by first spaces; second internal electrodes disposed on the second dielectric layers to oppose the first internal electrodes with the first dielectric layers or the second dielectric layers interposed therebetween, exposed to the fourth surface, the fifth surface, and the sixth surface, and spaced apart from the third surface by second spaces; first dielectric patterns disposed in at least a portion of the first spaces, and second dielectric patterns disposed in at least a portion of the second spaces; and lateral insulating layers.

Abstract: A multilayer electronic component includes a capacitor body including a plurality of dielectric layers and a plurality of first and second internal electrodes alternately disposed with respective dielectric layers interposed therebetween. One end of each of the first and second internal electrodes extends, respectively, to a third or fourth surface of the capacitor body. First and second external electrodes respectively include first and second connected portions disposed on the third and fourth surfaces, and first and second band portions respectively extended from the first and second connected portions to portions of a first surface of the capacitor body. A first connection terminal is disposed on the first band portion to provide a first solder accommodating portion, and a second connection terminal is disposed on the second band portion to provide a second solder accommodating portion.

Abstract: A ceramic capacitor which is low in ESL and suitable for being built into a substrate has a dimension in a length direction of a lowermost surface of a third external electrode which is in contact with a capacitor main body denoted by e1 and a dimension in the length direction of the uppermost surface of the third external electrode denoted by e2, and a relationship of e1<e2 is satisfied.

Abstract: An electronic component is able to be mounted on a mounting substrate on which a first electronic component and a second electronic component are able to be mounted. When dimensions of the first electronic component and the second electronic component in a width direction is designated as W1 and W2, respectively, and dimensions of the first electronic component and the second electronic component in a length direction are designated as L1 and L2, respectively, dimensions of the electronic component in the width direction and the length direction are any one of combinations of W1 and L2, and of W2 and L1. The electronic component includes a third laminate and a pair of third external electrodes. Each of the pair of third external electrodes includes a fired layer, and a resin layer provided on an external surface of the fired layer.

Abstract: A multilayer electronic component includes a multilayer capacitor including a capacitor body in which internal electrodes are stacked to be parallel with respect to a mounting surface and external electrodes disposed on opposing end surfaces of the capacitor body, respectively, and a metal frame having a solder pocket and including a vertical portion, an upper horizontal portion extending from an upper end of the vertical portion, and a lower horizontal portion extending from a lower end of the vertical portion, the upper horizontal portion connected to an upper band portion of each of the external electrodes. 0.1?G/CT?0.7 is satisfied, in which CT is a height of the vertical portion and G is a distance between the lower band portion of each of the external electrodes and a lower end of the metal frame.

Abstract: An electronic device includes a chip component and a metal terminal. The chip component has an element body where internal electrodes are laminated inside and a terminal electrode formed outside the element body and connected with end parts of the internal electrodes. The metal terminal is connected with the terminal electrode of the chip component. The metal terminal includes an electrode face portion and a mount portion. The electrode face portion is arranged correspondingly with an end surface of the terminal electrode. The mount portion is mounted on a mount surface. The electrode face portion is provided with an opening portion so that a part of the terminal electrode corresponding with at least a part of the internal electrodes is exposed to the outside.

Abstract: A plurality of dielectric layers containing one of CaZrO3 and SrZrO3 and a plurality of internal electrodes containing Ni are alternately disposed in a second direction. The plurality of internal electrodes includes a plurality of first internal electrodes and a plurality of second internal electrodes. Each of first connecting portions of the first internal electrodes includes a first end portion connected to a first terminal electrode. Each of second connecting portions of the second internal electrodes includes a second end portion connected to a second terminal electrode. The first end portions of the first connecting portions adjacent to each other in the second direction are located not to overlap with each other when viewed from the second direction. The second end portions of the second connecting portions adjacent to each other in the second direction are located not to overlap with each other when viewed from the second direction.

Abstract: A multi-layer ceramic electronic component includes a multi-layer unit and an external electrode. The multi-layer unit includes an end surface oriented in a first direction, a side surface oriented in a second direction orthogonal to the first direction, a ridge connecting the end surface and the side surface, ceramic layers, and internal electrodes. The multi-layer ceramic electronic component satisfies the following relationships: A/L?0.0142*ln(L)+0.0256, A/T?0.0274*ln(T)+0.0719, B/L?0.0103*ln(L)+0.0281, and B/T?0.0189*ln(T)+0.0707, where A represents a thickness of the external electrode in the second direction at a position adjacent to the ridge on the side surface, B represents a thickness of the external electrode in the first direction at a position adjacent to the ridge on the end surface, L represents a dimension of the multi-layer ceramic electronic component in the first direction, and T represents a dimension of the multi-layer ceramic electronic component in the second direction.

Abstract: A semiconductor device includes a capacitor structure. The capacitor structure comprises conductive vias extending through openings in a stack of alternating dielectric materials and first conductive materials, each conductive via comprising a second conductive material extending through the openings and another dielectric material on sidewalls of the openings, first conductive lines in electrical communication with a first group of the conductive vias, and second conductive lines in electrical communication with a second group of the conductive vias. Related semiconductor device, electronic systems, and methods are disclosed.

Abstract: In a ceramic capacitor which is low in ESL and suitable to be built into a substrate, widths of portions of a third external electrode on first and second principal surfaces in a length direction are A, widths of portions of the third external electrode on first and second side surfaces in the length direction are B, A>B is satisfied, and widths of portions of first and second external electrodes on the first and second principal surfaces in the length direction are C, widths of portions of the first and second external electrodes on the first and second side surfaces in the length direction are denoted by D, C>D is satisfied.

Abstract: A solid electrolytic capacitor that includes a capacitor element including an anode portion having a metal layer, a dielectric layer, and a cathode portion having a solid electrolyte layer and a current collector layer; a leading conductor layer; an insulating resin body covering the capacitor element and the leading conductor layer, the insulating resin body having a first end surface and a second end surface opposite to each other; a first external electrode; and a second external electrode. The first external electrode has at least one plating layer on the first end surface, and is connected to the leading conductor layer at the first end surface. The second external electrode has at least one plating layer on the second end surface, and is connected to the metal layer at the second end surface.

Abstract: A semiconductor device composed of a capacitive humidity sensor comprised of a moisture-sensitive polymer layer electrografted to an electrically conductive metal layer situated on an CMOS substrate or a combined MEMS and CMOS substrate, and exposed within an opening through a passivation layer, packages composed of the encapsulated device, and methods of forming the capacitive humidity sensor within the semiconductor device, are provided.

Abstract: An electronic component is able to be mounted on a mounting substrate including a pair of first edge portions that faces each other, and a pair of second edge portions that is perpendicular or substantially perpendicular to the pair of first edge portions and faces each other. The mounting substrate has a structure that allows at least any one of the electronic component, a first electronic component, and a second electronic component, to be mounted thereon. When a dimension of the first electronic component in a length direction is designated as L1, a dimension of the first electronic component in a width direction is designated as W1, a dimension of the second electronic component in the length direction is designated as L2, and a dimension of the second electronic component in the width direction is designated as W2, a dimension of the electronic component in the width direction is any one of W1 and W2.

Abstract: In a circuit module, even if a transmission signal output from a transmission electrode of a mounting substrate to a transmission terminal of a splitter leaks into a ground electrode, the transmission signal that has leaked into the ground electrode is mainly transmitted along an edge of the ground electrode and the transmission signal that has leaked into the ground electrode flows into a plurality of via conductors arranged with end surfaces superposed with the edge of the ground electrode when viewed in plan. Therefore, a transmission signal that has been output from the transmission electrode and leaked into the ground electrode is prevented from traveling along the edge of the ground electrode toward the reception electrode side. As a result, isolation characteristics of the transmission electrode and the reception electrode from each other are improved.

Abstract: An electronic component is provided to include: a capacitor array having a structure in which a plurality of capacitors are arranged; a pair of metal frames disposed on side surfaces of the capacitor array, connected to external electrodes of the plurality of capacitors, and including penetration portions formed in positions in which the pair of metal frames are connected to the external electrodes; and a plating member filling the penetration portions. A manufacturing method thereof is further provided.

Abstract: A multilayer ceramic capacitor with decreased high voltage stress defects and a board having the same may include a body formed by stacking a plurality of dielectric layers and a plurality of first and second internal electrodes in a width direction, the first and second internal electrodes including body portions overlapping each other and lead portions exposed to a mounting surface of the body and disposed to be spaced apart from each other, respectively; and first to third external electrodes disposed on the mounting surface of the capacitor body to be connected to the lead portions, respectively, wherein the body portions of the first and second internal electrodes have different areas from each other.

Abstract: A multilayer ceramic capacitor having inner electrodes with a Ni-Metal A alloy, the Metal A being selected from Fe, V, Y, and Cu and dissolved in the Ni to form a solid solution. The percentage of the Metal A with respect to the total amount of Metal A and Ni in near-surface regions located at a depth of 2 nm from a surface of the inner electrode in contact with an adjacent ceramic dielectric layer is 1.4 or more atom %, and XA?YA?1.0, where XA represents the atomic percentage of Metal A in the near-surface regions and YA represents the atomic percentage of Metal A in mid-thickness regions of the inner electrodes. A method for producing a multilayer ceramic capacitor includes annealing the ceramic multilayer body under specific conditions to thereby increase, in the inner electrodes, the percentage of Metal A in the near-surface regions.

Abstract: A coil device and a wireless power transmission device which can detect the happened open fault or short fault reliably in any one of the plurality of capacitor elements constituting the capacitor circuit. Coil device includes coil for power transmission, capacitor circuit connected to coil for power transmission and having a plurality of capacitor elements, conductive metal portion which is disposed close to coil for power transmission, and measuring portion for measuring a voltage or a current generated in metal portion.

Abstract: A multilayer ceramic capacitor may include: three external electrodes disposed on a mounting surface of a ceramic body to be spaced apart from one another. When a thickness of an active layer including a plurality of first and second internal electrodes disposed therein is defined as AT, and a gap between a first or second lead part of the first internal electrode and a third lead part of the second internal electrode is defined as LG, the following Equation may be satisfied: 0.00044?LG*log [1/AT]?0.00150.

Abstract: Methods and systems to improve a multilayer ceramic capacitor using additive manufacturing are disclosed. Conductive layer ends and dielectric layer edges of a multilayer ceramic capacitor may be modified to comprise a round shape, which may increase voltage limits by reducing electric field intensity that results from sharp corners. Further, the capacitor may comprise wave-like structures to increase surface area of a conductive layer and/or dielectric layer. The round shape of the conductive layer end may in-part reduce the need for a wide protective gap due to its dome-shape permitting the dielectric layer to be wider on top and bottom, and thinner at the center, e.g. concave, which provides strength support to the layers. The 3D Printing process permits the distance between the conductive layer end of the conductive layer to be much closer to the dielectric layer edge of the dielectric layer, such as below the standard 500 microns.

Abstract: Provided is a module comprising a carrier material, comprising a first conductive portion and a second conductive portion, and a multiplicity of electronic components wherein each electronic component comprises a first external termination with at least one first longitudinal edge and a second external termination with at least one second longitudinal edge. A first longitudinal edge of a first electronic component is connected to the first conductive portion by a first interconnect; and a second longitudinal edge of the first electronic component is connected to the second conductive portion by a second interconnect.

Abstract: A multilayer electronic component includes a capacitor body, first and second external electrodes, first and second land portions, and first and second insulating portions. The first and second external electrodes are disposed and spaced apart from each other on a mounting surface of the capacitor body. The first and second land portions include a conductive material and are disposed on the first and second external electrodes, respectively. The first and second insulating portions are disposed between the first and second land portions on the mounting surface of the capacitor body to be spaced apart from each other and each have one end connected to a respective one of the first and second land portions. A board having a multilayer electronic component includes a circuit board having first and second electrode pads disposed on one surface thereof, and the multilayer electronic component mounted thereon.

Abstract: Relatively low noise capacitors are provided for surface mounted applications. Electro-mechanical vibrations generate audible noise, which are otherwise relatively reduced through modifications to MLCC device structures, and/or their mounting interfaces on substrates such as printed circuit boards (PCBs). Different embodiments variously make use of flexible termination compliance so that surface mounting has reduced amplitude vibrations transmitted to the PCB. In other instances, side terminal and transposer embodiments effectively reduce the size of the mounting pads relative to the case of the capacitor, or a molded enclosure provides standoff, termination compliance and clamping of vibrations.

Abstract: A multilayer capacitor includes a capacitor body, dielectric layers and a plurality of first internal electrodes and second internal electrodes forming a portion of the capacitor body, the plurality of first internal electrodes and second internal electrodes alternately disposed with respective dielectric layers interposed therebetween, the capacitor body further having a first surface and a second surface opposing each other, a third surface and a fourth surface opposing each other, and a fifth surface and a sixth surface opposing each other, the first internal electrodes and the second internal electrodes being exposed through at least the third surface and the fourth surface, respectively, an insulating layer disposed in the first surface of the capacitor body, a buffer layer at least partially covering the insulating layer, and a first terminal electrode and a second terminal electrode spaced apart from each other.

Abstract: A multilayer ceramic capacitor includes a capacitor body and first to fourth outer connectors. The capacitor body includes dielectric layers and conductor layers, first and second principal surfaces facing each other in a height direction, first and second side surfaces facing each other in a length direction, and third and fourth side surfaces facing each other in a width direction. The first to fourth outer connectors cover portions of the first to fourth side surfaces, respectively. In a case where L0, W0, and H0 are maximum external dimensions of the multilayer ceramic capacitor in the length direction, the width direction, and the height direction, respectively, L0, W0, and H0 satisfy a condition of about 2.67?L0/H0 and a condition of about 1/1.72?L0/W0?about 1.72.

Abstract: The present disclosure discloses a thin-film capacitor for an electric vehicle, including: a casing, a plurality of capacitor cores, an anode busbar, a cathode busbar, a first electrode terminal, a second electrode terminal, a first connection sheet, a second connection sheet, a first battery connection sheet, a second battery connection sheet, a first battery connection terminal and a second battery connection terminal, in which the first battery connection sheet is connected to the anode busbar and adjacent to an end of the anode busbar, the second battery connection sheet is connected to the cathode busbar and adjacent to the first battery connection sheet, an axis of one of the plurality of the capacitor cores is arranged to be perpendicular to the anode busbar and the cathode busbar and two ends of the one capacitor core are connected to the first battery connection sheet and the second battery connection sheet respectively.

Abstract: An interposer substrate includes a first circuit pattern embedded at a first surface of a dielectric layer and a second circuit pattern embedded at a second surface of the dielectric layer; a middle patterned conductive layer in the dielectric layer between the first circuit pattern and the second circuit pattern; first conductive vias, where each first conductive via includes a first end adjacent to the first circuit pattern and a second end adjacent to the middle patterned conductive layer, wherein a width of the first end is greater than a width of the second end; second conductive vias, where each second conductive via including a third end adjacent to the second circuit pattern and a fourth end adjacent to the middle patterned conductive layer, wherein a width of the third end is greater than a width of the fourth end.

Abstract: A multilayer capacitor includes a body including a capacitor body formed by layering a plurality of dielectric layers and a plurality of first and second internal electrodes in a width direction, the first and second internal electrodes including body portions overlapping each other and lead portions exposed to a mounting surface of the capacitor body and disposed to be spaced apart from each other, respectively; and first, second and third external electrodes disposed on the mounting surface of the capacitor body to be connected to the lead portions, respectively, wherein the first, second and third external electrodes each include first, second and third electrode layers which are sequentially stacked, the first and second electrode layers containing metal and glass particles, and the third electrode layer containing a conductive resin.

Abstract: Methods and systems to improve a multilayer ceramic capacitor using additive manufacturing are disclosed. Layers of a capacitor may be modified from its traditional planar shape to a wavy structure. The wavy shape increases surface area within a fixed volume of the capacitor, thus increasing capacitance, and may comprise smooth and repetitive oscillations without the presence of voltage-degrading sharp corners. In addition, the ends of each conductive layer do not have sharp edges, such as comprising of a round corner. The one-dimensional wave pattern may run parallel to the width of the capacitor, or it may align in parallel to the length of the capacitor. In some embodiments, the wave pattern may be parallel to both the width and the length—in two dimensions—such that it forms an egg-crate shape. Further, the wavy structures may comprise of secondary or tertiary wavy structures to further increase surface area.

Abstract: A method of forming a capacitor structure includes forming a first set of electrodes having a first electrode and a second electrode, wherein each electrode of the first set of electrodes has an L-shaped portion. The method further includes forming a second set of electrodes having a third electrode and a fourth electrode, wherein each electrode of the second set of electrodes has an L-shaped portion. The method further includes forming insulation layers between the first set of electrodes and the second set of electrodes. The method further includes forming a first L-shaped line plug connecting the first electrode to the third electrode, wherein an entirety of an outer surface of the first L-shaped line plug is recessed with respect to an outer surface of the L-shaped portion of the first electrode. The method further includes forming a second line plug connecting the second electrode to the fourth electrode.