Component Within Printed Circuit Board Patents (Class 361/761)
  • Patent number: 10958005
    Abstract: Apparatuses for direct cabled connections of fabric signals—i.e., high-speed data signals exchanged between computer processors and peripheral devices. Specifically, varying apparatus configurations are outlined herein for minimizing, if not eliminating, the routing of these fabric signals through printed circuit boards, which tend to cause signal quality degradation due to phenomena such as the skin effect and dielectric loss.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: March 23, 2021
    Assignee: Dell Products L.P.
    Inventor: Shawn Joel Dube
  • Patent number: 10952319
    Abstract: An electronic component embedded substrate includes a core layer having a first cavity and a second cavity on a first surface and a second surface of the core layer, respectively, the second surface opposite to the first surface in a thickness direction of the core layer; an electronic component disposed in the first cavity; a first insulating material covering at least a portion of the electronic component; a first wiring layer disposed on the first insulating material and connected to the electronic component; a built-in block disposed in the second cavity; and a second insulating material covering at least a portion of the built-in block.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: March 16, 2021
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Young Kwan Lee, Kyoung Jun Kim, Yong Hoon Kim, Seung Eun Lee, Hak Chun Kim
  • Patent number: 10952310
    Abstract: A high-frequency module (1) includes a substrate (10), a first electronic component (13) and a second electronic component (14) that are provided on the substrate (10), an insulating layer (15) that covers a part of a side surface of the first electronic component (13) and a side surface and a top surface of the second electronic component (14), and a heat-dissipating layer (16) that covers at least a top surface of the first electronic component (13) and a portion of the side surface of the first electronic component (13) excluding the portion of the side surface of the first electronic component (13) in contact with the insulating layer (15).
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: March 16, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Syuichi Onodera
  • Patent number: 10905016
    Abstract: A method of manufacturing a component carrier is disclosed. The method includes providing a first component carrier body having at least one first electrically insulating layer structure and at least one first electrically conductive layer structure, providing a second component carrier body having at least one second electrically insulating layer structure and at least one second electrically conductive layer structure, providing at least a part of at least one of the first component carrier body and the second component carrier body of an at least partially uncured material, and interconnecting the first component carrier body with the second component carrier body by curing the at least partially uncured material.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: January 26, 2021
    Assignee: AT & Austria Technologie & Systemtechnik Aktiengesellschaft
    Inventors: Gernot Grober, Sabine Liebfahrt, Marco Gavagnin
  • Patent number: 10882248
    Abstract: A three dimensional printing system for producing a three dimensional article of manufacture includes a build platform, a powder dispensing apparatus, a light emitting device head, a drop ejecting head, a movement mechanism, and a controller. The light emitting device head may be a vertical cavity surface-emitting laser (VCSEL) head that has a columnar arrangement of VCSELs that emit light having a defined spectral distribution. The drop ejecting head is configured to separately eject a plurality of different inks having correspondingly different absorption coefficients for the defined spectral distribution. The controller operates the powder dispensing apparatus to dispense powder, move and operate the drop ejecting head to define an array of inked pixels, and move and operate the VCSEL head to fuse the inked pixels. The controller varies an energy output of the VCSELs in correspondence with a variation of an absorption coefficient of the inked pixels.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: January 5, 2021
    Assignee: 3D Systems, Inc.
    Inventor: James Francis Smith, III
  • Patent number: 10868209
    Abstract: A sensor element is disclosed.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: December 15, 2020
    Assignee: OSRAM OLED GMBH
    Inventors: Choon Kim Lim, Choo Kean Lim, Jeok Pheng Go
  • Patent number: 10858244
    Abstract: Production of a device for connecting a nano-object to an external electrical system (SEE) including: a first chip provided with conducting areas (8a, 8b) and a first nano-object (50) connected to the conducting areas, the first chip being assembled on a support (70) such that the first nano-object is arranged facing an upper face of the support, the device being further provided with first connection elements (80a, 80b) capable of being connected to the external electrical system and arranged on and in contact with the first conducting areas (8a, 8b), the first connection elements being formed on the side of the upper face of the support (70) and being accessible from the side of the upper face of the support.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: December 8, 2020
    Assignee: Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Aurelie Thuaire, Patrick Reynaud, Patrick Leduc, Emmanuel Rolland
  • Patent number: 10856723
    Abstract: A medical circuit board includes a substrate on which a wiring pattern is formed, a plurality of electronic components mounted in a mounting area on the substrate, a resinous sealing member covering the plurality of electronic components, with which the plurality of electronic components are sealed to the substrate, and a detection unit provided in an area other than the mounting area on the substrate and detecting an infiltration of a liquid from an interface between the substrate and the sealing member into the mounting area. At least a part of the detection unit is covered with the sealing member and sealed with the sealing member to the substrate.
    Type: Grant
    Filed: October 9, 2018
    Date of Patent: December 8, 2020
    Assignee: SONY OLYMPUS MEDICAL SOLUTIONS INC.
    Inventor: Masahiro Hagihara
  • Patent number: 10863631
    Abstract: A manufacturing method, wherein the method includes providing a layer stack having at least partially uncured component carrier material, arranging a plurality of components in recesses of the layer stack, integrally connecting the components with the layer stack by curing the component carrier material, and applying a high temperature robust dielectric structure on a main surface of the cured layer stack with the components therein.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: December 8, 2020
    Assignee: AT&S Austria Technologie & Systemtechnik Aktiengesellschaft
    Inventors: Johannes Stahr, Timo Schwarz, Mario Schober
  • Patent number: 10813227
    Abstract: In a component press-bonding device that performs work related to component mounting on a board after a mark provided on a transparent end region of the board is recognized, an imaging camera provided with an imaging optical axis extending downwards, a light emitter that irradiates the end region with illumination light from above the board in a state where the mark is positioned within an imaging visual field of the imaging camera, and a light reflecting member that is provided below the imaging camera and reflects the illumination light, which is emitted by the light emitter and is transmitted downwards through the end region, back to the end region are included. The imaging camera images the mark under the illumination light, which is reflected by the light reflecting member and is transmitted upwards through the end region.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: October 20, 2020
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Toshihiko Tsujikawa, Akira Kameda
  • Patent number: 10756023
    Abstract: A semiconductor package includes a connection member and a supporting member. The connection member has first and second surfaces opposing each other and a redistribution layer. The supporting member is disposed on the first surface of the connection member, has a first through-hole and a second through-hole spaced apart from each other, and has a blocking layer disposed on at least an inner surface of the second through-hole. A semiconductor chip is disposed in the first through-hole and has connection pads connected to the redistribution layer. At least one passive component is disposed in the second through-hole and has connection terminals connected to the redistribution layer. An encapsulant encapsulates the semiconductor chip and the at least one passive component in the first and second through-holes, respectively. An electromagnetic band-gap (EBG) structure is embedded in the supporting member.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: August 25, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Han Kim, Hyung Joon Kim
  • Patent number: 10734170
    Abstract: A resin structure includes a molded resin element and a push-type switch. The push-type switch includes a receptacle whereon a first terminal and a second terminal are secured, the first terminal and the second terminal configured to connect to an electrical circuit; a button unit protruding from the receptacle; and a contact spring unit configured to move with the button unit, to electrically connect between the first terminal and the second terminal, and to generate an opposing force relative to a pressure applied between the receptacle and the button unit. The receptacle stores the button unit and the contact spring unit. The receptacle of the push-type switch is embedded in the molded resin element with the button unit exposed from the molded resin element.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: August 4, 2020
    Assignee: OMRON Corporation
    Inventor: Wakahiro Kawai
  • Patent number: 10641820
    Abstract: Apparatus and methods for detecting and identifying a cause of a hot-switching event in an automated test system. One or more antennae positioned near mechanical relays in the system may be used to sense electromagnetic radiation. The antennae may be configured to respond to electromagnetic radiation of the type generated during a hot-switching event. Signals measured by the antennae may be processed to determine whether the signals have characteristics of hot-switching events. Processing may entail generating a signal envelope and determining whether the envelope has characteristics indicative of a hot-switching event. When a hot-switching event is detected, information to correlate the event to other events in the test system may also be captured. That information may be time information, enabling program test-system program instructions executing at the time of the event to be identified, such that the test system may be reprogrammed to avoid hot-switching events.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: May 5, 2020
    Assignee: Teradyne, Inc.
    Inventors: Alan B. Hussey, Richard John Burns, Gregory Smith, Mark Alan Levin
  • Patent number: 10629476
    Abstract: A package includes a device die, a molding material molding the device die therein, a through-via substantially penetrating through the molding material, wherein the through-via has an end. The end of the through-via is tapered and has rounded sidewall surfaces. The package further includes a redistribution line electrically coupled to the through-via.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: April 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Hsien-Wei Chen
  • Patent number: 10593568
    Abstract: Semiconductor devices having a semiconductor die electrically coupled to a redistribution structure and a molded material over the redistribution structure are disclosed herein, along with associated systems and methods. In one embodiment, a semiconductor device includes a semiconductor die attached to a first side of a substrate-free redistribution structure, and a plurality of conductive columns extending through a molded material disposed on the first side of the redistribution structure. The semiconductor device can also include a second redistribution structure on the molded material and electrically coupled to the conductive columns. A semiconductor device can be manufactured using a single carrier and requiring processing on only a single side of the semiconductor device.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: March 17, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Chan H. Yoo, John F. Kaeding, Ashok Pachamuthu, Mark E. Tuttle
  • Patent number: 10580738
    Abstract: Direct bonding heterogeneous integration packaging structures and processes include a packaging substrate with first and second opposing surfaces. A trench or a pedestal is provided in the first surface. A bridge is disposed in the trench or is adjacent the pedestal sidewall, wherein the bridge includes an upper surface coplanar with the first surface of the package substrate. At least two chips in a side by side proximal arrangement overly the bridge and the packaging substrate, wherein the bridge underlies peripheral edges of the at least two chips in the side by side proximal arrangement. The at least two chips include a plurality of electric connections that are directly coupled to corresponding electrical connections on the bridge and on the packaging substrate.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: March 3, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kamal K. Sikka, Jon A. Casey, Joshua Rubin, Arvind Kumar, Dinesh Gupta, Charles L. Arvin, Mark W. Kapfhammer, Steve Ostrander, Maryse Cournoyer, Valérie A. Oberson, Lawrence A. Clevenger
  • Patent number: 10559905
    Abstract: Implementations of pins for semiconductor packages may include: an upper contact portion having a contact surface configured to mechanically and electrically couple with a pin receiver; a lower portion having a vertical stop and at least two curved legs; a horizontal base coupled directly to the at least two curved legs and configured to be soldered to a substrate to mechanically and electrically couple the pin to the substrate, the horizontal base having an upper contact surface, and; a gap between a bottom contact surface of the vertical stop and the upper contact surface of the horizontal base; wherein the at least two curved legs are configured to flex to allow the bottom contact surface of the vertical stop to move toward the upper contact surface of the horizontal base in response to a pressure applied to the pin along a direction collinear with a longest length of the pin toward the upper contact surface, and; wherein the vertical stop is configured to stop movement of the pin when the bottom contact s
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: February 11, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Yushuang Yao, Chee Hiong Chew, Atapol Prajuckamol
  • Patent number: 10551697
    Abstract: An electrooptic display device includes a TFT substrate, a touch panel superimposed and placed on the TFT substrate, a circuit board spaced apart from the TFT substrate and the touch panel, one side of the circuit board facing the TFT substrate and the touch panel, a plurality of first FPCs each including one end electrically connected to one side of the TFT substrate, and the other end electrically connected to one side of the circuit board, and a second FPC that is electrically connected to the touch panel and extends in parallel to the first FPCs. The circuit board includes a cutout in a portion overlapping the second FPC on one side of the circuit board.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: February 4, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventor: Takahiro Ueno
  • Patent number: 10483345
    Abstract: An electronic component embedded substrate includes: a substrate that includes an insulating layer and has a first principal surface and a second principal surface on the opposite side of the first principal surface; and an electronic component that is embedded in the substrate and has a plurality of first terminals provided close to the first principal surface, a plurality of second terminals provided close to the second principal surface, and a capacity part provided between the plurality of first terminals and the plurality of second terminals. The electronic component is configured such that at least a part of the second terminals is embedded in the insulating layer. An insulating member is provided between the neighboring second terminals to be in contact with both of the neighboring second terminals. The insulating member and the insulating layer are formed of materials whose thermal expansion coefficients are different from each other.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: November 19, 2019
    Assignee: TDK CORPORATION
    Inventors: Mitsuhiro Tomikawa, Koichi Tsunoda, Kazuhiro Yoshikawa, Kenichi Yoshida
  • Patent number: 10474868
    Abstract: A fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole of the first connection member and having an active surface with connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first connection member and the semiconductor chip; and a second connection member disposed on the first connection member and the semiconductor chip. The first connection member and the second connection member respectively include first redistribution layers and second redistribution layers electrically connected to the connection pads and formed of one or more layers, at least one of the first redistribution layers is disposed between a plurality of insulating layers of the first connection member, and at least one of the second redistribution layers includes sensor patterns recognizing a fingerprint.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: November 12, 2019
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Yong Ho Baek, Jung Hyun Cho, Byoung Chan Kim
  • Patent number: 10475734
    Abstract: A semiconductor device package includes: (1) a substrate having a first surface and a second surface opposite to the first surface; (2) a first patterned conductive layer on the first surface of the substrate and having a first surface and a second surface, wherein the second surface of the first patterned conductive layer is adjacent to the substrate and opposite to the first surface of the first patterned conductive layer; (3) a first insulation layer on the first surface of the substrate and having a first surface and a second surface, wherein the second surface of the first insulation layer is adjacent to the substrate and opposite to the first surface of the first insulation layer; and (4) a second patterned conductive layer extending from the first surface of the first insulation layer to the second surface of the substrate, the second patterned conductive layer electrically connected to the first patterned conductive layer.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: November 12, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chien-Hua Chen, Sheng-Chi Hsieh, Cheng-Yuan Kung
  • Patent number: 10475776
    Abstract: A fan-out semiconductor package module includes a core member having first and second through-holes. A semiconductor chip is in the first through-hole and has an active surface with a connection pad and an inactive surface opposing the active surface. Another passive component is in the second through-hole. An first encapsulant covers at least portions of the core member and the passive component, and fills at least a portion of the second through-hole. A reinforcing member is on the first encapsulant. A second encapsulant covers at least a portion of the semiconductor chip, and fills at least a portion of the first through-hole. A connection member is on the core member, the active surface of the semiconductor chip, and the passive component, and includes a redistribution layer electrically connected to the connection pad and the passive component.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: November 12, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yeong A Kim, Eun Sil Kim, Young Gwan Ko, Akihisa Kuroyanagi, Jin Su Kim, Jun Woo Myung
  • Patent number: 10446455
    Abstract: A fingerprint sensor device and a method of making a fingerprint sensor device. As non-limiting examples, various aspects of this disclosure provide various fingerprint sensor devices, and methods of manufacturing thereof, that comprise a sensing area on a bottom side of a die without top side electrodes that senses fingerprints from the top side, and/or that comprise a sensor die directly electrically connected to conductive elements of a plate through which fingerprints are sensed.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: October 15, 2019
    Assignee: Amkor Technology, Inc.
    Inventors: Sung Sun Park, Ji Young Chung, Christopher Berry
  • Patent number: 10404226
    Abstract: A power amplifier module includes a substrate, a power amplifier having a first surface on which an electrode is defined and a second surface opposite the first surface, the first surface faces a principal surface of the substrate, a surface acoustic wave duplexer having a first surface on which an electrode is defined and a second surface opposite the first surface, the first surface faces the principal surface of the substrate, a heat dissipation unit defined on another principal surface of the substrate, a heat dissipation path that connects a connecting portion between the power amplifier and the principal surface to the heat dissipation unit, an insulating resin that covers the power amplifier and the surface acoustic wave duplexer, a conductive shield that covers the insulating resin, and a first conductive unit defined on the second surface of the surface acoustic wave duplexer and electrically connected to the conductive shield.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: September 3, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Takashi Kitahara, Hiroaki Nakayama, Tsunekazu Saimei, Hiroki Noto, Koichiro Kawasaki
  • Patent number: 10402620
    Abstract: A fan-out semiconductor package includes: a core member including a support layer, a first wiring layer, a second wiring layer, and through-vias and having a through-hole; a semiconductor chip disposed in the through-hole; an encapsulant covering the core member and the semiconductor chip and filling at least portions of the through-hole; a connection member including an insulating layer disposed on the first wiring layer and the semiconductor chip, a redistribution layer disposed on the insulating layer, first vias electrically connecting the redistribution layer and the connection pads to each other, and second vias electrically connecting the redistribution layer and the first wiring layer to each other; and a passivation layer disposed on the insulating layer and covering the redistribution layer, wherein a thickness of the passivation layer is within half a distance from an inactive surface of the semiconductor chip to a lower surface of the encapsulant.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: September 3, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byung Ho Kim, Da Hee Kim, Joon Sung Kim, Joo Young Choi, Hee Sook Park, Tae Wook Kim
  • Patent number: 10396046
    Abstract: Apparatuses, systems and methods associated with substrate design with a magnetic feature for fully integrated voltage regulator are disclosed herein. In embodiments, a substrate assembly may include a base substrate and one or more interconnect elements located at a first side of the base substrate, the one or more interconnect elements to be coupled to a semiconductor chip having an integrated voltage regulator (IVR). The substrate assembly may further include a magnetic feature located at a second side of the base substrate, the second side being opposite to the first side, wherein the magnetic feature extends along a portion of the second side of the base substrate that is opposite to where the IVR is to be located when the semiconductor chip is coupled to the one or more interconnect elements. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: August 27, 2019
    Assignee: Intel Corporation
    Inventors: Yikang Deng, Robert Sankman
  • Patent number: 10345874
    Abstract: The disclosed apparatus may include (1) a ganged heatsink base that (A) absorbs heat dissipated by a plurality of electronic components that consume differing amounts of power and (B) includes a plurality of thermal regions dedicated to absorbing the heat dissipated by the plurality of electronic components and (2) at least one thermal isolation engine that (A) is incorporated into the ganged heatsink base, (B) separates the plurality of thermal regions from one another, and (C) localizes the heat dissipated by the plurality of electronic components by maintaining at least some of the heat dissipated by one of the electronic components within the thermal region that absorbed the at least some of the heat such that the at least some of the heat does not migrate to another thermal region included in the ganged heatsink base. Various other apparatuses, systems, and methods are also disclosed.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: July 9, 2019
    Assignee: Juniper Networks, Inc
    Inventors: Susheela Nanjunda Rao Narasimhan, Basavaraja Munishamappa, Troy M. Sheets, Luis Zamora, Seongchul C. Kim
  • Patent number: 10333407
    Abstract: A multi-phase DC-DC converter includes a substrate having opposing first and second sides, a plurality of power stage packages attached to the first side of the substrate, each power stage package including active semiconductor components operable to provide an output phase of the multi-phase DC-DC converter, and a coupled inductor attached to the first side of the substrate and at least partly covering two or more of the power stage packages. The coupled inductor includes separate windings wound on the same core. Each winding of the coupled inductor electrically connects an output of one of the power stage packages at least partly covered by the coupled inductor to a metal trace on the substrate such that the outputs of the power stage packages at least partly covered by the coupled inductor are electrically connected to the same metal trace on the substrate.
    Type: Grant
    Filed: May 6, 2015
    Date of Patent: June 25, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Emil Todorov, Benjamim Tang, Darryl Tschirhart
  • Patent number: 10321088
    Abstract: Provided is a television apparatus including: a display panel which displays an image; a front cover which covers a front side of the television apparatus such that the display panel is exposed; a rear cover which is opposed to the front cover; a power supply which is supported between the front cover and the rear cover and includes an input connector mounted thereon to receive an input AC power for the display panel; an output connector configured to detachably coupled with the input connector to supply the input AC power, wherein the rear cover includes an inwardly-depressed portion at which a cover insertion hole is formed such that the output connector is coupled to the input connector through the cover insertion hole.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: June 11, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Young-deok Choi
  • Patent number: 10289892
    Abstract: The present disclosure provides a fingerprint chip package structure and a terminal. The fingerprint chip package structure includes a package body and a fingerprint identification chip. The package body includes a bottom surface and a lateral surface connected to the bottom surface, and defines a recessed portion at a junction of the bottom surface and the lateral surface. The fingerprint identification chip is received in the package body. The package body packages the fingerprint identification chip therein. The package body includes a first package portion and a second package portion coupled to the first package portion. The first package portion includes the bottom surface, and the second package portion includes the lateral surface. The fingerprint chip package structure is configured to be received in a decoration enclosure.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: May 14, 2019
    Assignee: GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP., LTD.
    Inventors: Shoukuan Wu, Zanjian Zeng
  • Patent number: 10268872
    Abstract: A fingerprint sensor package and method are provided. Embodiments include a sensor and a sensor surface material encapsulated within the fingerprint sensor package. An array of electrodes of the sensor are electrically connected using through vias that are located either in the sensor, in connection blocks separated from the sensor, or through connection blocks, or else connected through other connections such as wire bonds. A high voltage die is attached in order to increase the sensitivity of the fingerprint sensor.
    Type: Grant
    Filed: February 19, 2018
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chih Huang, Chih-Hua Chen, Yu-Jen Cheng, Chih-Wei Lin, Yu-Feng Chen, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
  • Patent number: 10256581
    Abstract: A connector housing mounting structure includes a connector housing; and a mounting member having a mounting surface. The connector housing includes a housing body, and a pair of flange portions extending from the housing body and having first mounting holes respectively. The mounting member includes a pair of first columnar portions protruding in parallel with each other from the mounting surface. Each of the first columnar portions is inserted into each of the first mounting holes, and the pair of flange portions is fixed to the mounting surface, thus the connector housing is regularly mounted on the mounting surface. A size of one of the flange portions in a width direction perpendicular to an extending direction of the flange portion is larger than the other flange portion in order that in case of incorrect mounting, the larger flange becomes obstructed and forms a visible indicator of misinstallation.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: April 9, 2019
    Assignee: YAZAKI CORPORATION
    Inventor: Yoshifumi Shinmi
  • Patent number: 10224217
    Abstract: A wafer level fan out package includes a semiconductor die having a first surface, a second surface, and a third surface. A stiffener is disposed on the third surface of the semiconductor die. A conductive via passes through the stiffener. First and second electrically conductive patterns electrically connected to the conductive via are disposed on the first and second surfaces of the semiconductor die and stiffener. Solder balls are electrically connected to the first or second electrically conductive patterns.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: March 5, 2019
    Assignee: Amkor Technology, Inc.
    Inventors: Jin Young Kim, Doo Hyun Park, Seung Jae Lee
  • Patent number: 10217684
    Abstract: A resin molding includes a semiconductor element, a circuit board, and a resin. A conductor connected to the semiconductor element is formed on the circuit board. The resin is adhered and integrated with the circuit board. A resin leakage suppression layer including a material having a higher thermal conductivity than that of a material forming a surface layer of the circuit board is provided in an edge region extending along a portion adhered to the resin in the circuit board and extending along at least one-side side surface of the resin.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: February 26, 2019
    Assignee: Hitachi Automotive Systems, Ltd.
    Inventors: Tsubasa Watanabe, Tsutomu Kono, Takayuki Yogo, Hiroaki Hoshika
  • Patent number: 10189703
    Abstract: A transducer module, comprising: a supporting substrate, having a first side and a second side; a cap, which extends over the first side of the supporting substrate and defines therewith a first chamber and a second chamber internally isolated from one another; a first transducer in the first chamber; a second transducer in the second chamber; and a control chip, which extends at least partially in the first chamber and/or in the second chamber and is functionally coupled to the first and second transducers for receiving, in use, the signals transduced by the first and second transducers.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: January 29, 2019
    Assignee: STMicroelectronics S.r.l.
    Inventors: Marco Omar Ghidoni, Roberto Brioschi
  • Patent number: 10186502
    Abstract: A component to be transferred to a receiving substrate is to be coupled both electrically and thermally. This is achieved by an integrated circuit comprising a substrate and a plurality of first components formed in or on the substrate. A plurality of metallization layers are provided. A second component applied by transfer printing is provided which is positioned, at least in part, on a level with and laterally adjacent to at least one of the plurality of metallization layers.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: January 22, 2019
    Assignee: X-FAB SEMICONDUCTOR FOUNDRIES GMBH
    Inventor: Ralf Lerner
  • Patent number: 10135224
    Abstract: An apparatus and method of forming a chip package with a waveguide for light coupling is disclosed. The method includes depositing an adhesive layer over a carrier. The method further includes depositing a laser diode (LD) die having a laser emitting area onto the adhesive layer and depositing a molding compound layer over the LD die and the adhesive layer. The method still further includes curing the molding compound layer and partially removing the molding compound layer to expose the laser emitting area. The method also includes depositing a ridge waveguide structure adjacent to the laser emitting area and depositing an upper cladding layer over the ridge waveguide structure.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: November 20, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Hao Tseng, Ying-Hao Kuo, Kuo-Chung Yee
  • Patent number: 10103087
    Abstract: The present invention provides a heat dissipation assembly and an electronic device, where the heat dissipation assembly includes: a shielding element, where a via hole is disposed on the shielding element, the shielding element is electrically connected to ground copper of a PCB board, and a heat-generating electronic element is disposed on the PCB board; a heat pipe, located on the via hole, where the heat pipe is electrically connected to the shielding element, and the heat pipe, the PCB board, and the shielding element form an electromagnetic shielding can that is used to accommodate the heat-generating electronic element; and an elastic thermal interface material, disposed between the heat pipe and the heat-generating electronic element and mutually fitted to the heat pipe and the heat-generating electronic element.
    Type: Grant
    Filed: March 18, 2014
    Date of Patent: October 16, 2018
    Assignee: HUAWEI DEVICE (DONGGUAN) CO., LTD.
    Inventors: Linfang Jin, Yongwang Xiao, Guoping Wang, Jie Zou, Hualin Li
  • Patent number: 10079254
    Abstract: Implementations of semiconductor packages may include: a die coupled to a glass lid; one or more inner walls having a first material coupled to the die; an outer wall having a second material coupled to the die; and a glass lid coupled to the die at the one or more inner walls and at the outer wall; wherein the outer wall may be located at the edge of the die and the glass lid and the one or more inner walls may be located within the perimeter of the outer wall at a predetermined distance from the perimeter of the outer wall; and wherein a modulus of the first material may be lower than a modulus of the second material.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: September 18, 2018
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Bingzhi Su, Derek Gochnour, Larry Kinsman
  • Patent number: 10080284
    Abstract: A circuit board structure includes an inner circuit structure and a first build-up circuit structure. The inner circuit structure includes a core layer having an upper surface and a lower surface, a first patterned circuit layer disposed on the upper surface, a second patterned circuit layer disposed on the lower surface and a conductive through hole connecting the first and the second patterned circuit layers. The first build-up circuit structure at least has a cavity and an inner dielectric layer. The inner dielectric layer has an opening communicating the cavity and a pad of the first patterned circuit layer is located in the opening. A hole diameter of the opening is smaller than a hole diameter of cavity. An inner surface of the inner dielectric layer exposed by the cavity and a top surface of the pad are coplanar or have a height difference.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: September 18, 2018
    Assignee: Unimicron Technology Corp.
    Inventors: Ming-Hao Wu, Shu-Sheng Chiang, Wei-Ming Cheng
  • Patent number: 10062635
    Abstract: A double-facing cooling-type power module has coolers on both sides. The power module includes: a first switch having the coolers on both sides; a second switch disposed independently from the first switch and having the coolers on both sides; and a common electrode coupled to both the first switch and the second switch.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: August 28, 2018
    Assignee: Hyundai Motor Company
    Inventor: Woo Yong Jeon
  • Patent number: 10055631
    Abstract: A sensor package and a method of forming a sensor package are disclosed. The sensor package comprises: a multilayer substrate comprising a mold compound layer and a plurality of patterned metal layers; an embedded die embedded in the multilayer substrate, wherein the mold compound layer of the multilayer substrate surrounds the embedded die; and, a sensing element disposed over the multilayer substrate, the sensing element comprising a first patterned metal layer electrically connected to the embedded die through the multilayer substrate.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: August 21, 2018
    Assignee: Synaptics Incorporated
    Inventors: Shengmin Wen, Brett Dunlap, Jay Kim
  • Patent number: 10015885
    Abstract: Provided are a printed circuit board and a method of manufacturing the printed circuit board, the printed circuit board including: a first element and a second element; a first base substrate including an embedding part in which the first element is embedded and a cavity into which the second element is mounted; and a second base substrate bonded to one surface of the first base substrate and including a first via for the second element.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: July 3, 2018
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Won Suk Jung, Yun Ho An, Sang Myung Lee, Joon Wook Han
  • Patent number: 9998812
    Abstract: A surface mountable microphone package comprises a first microphone and a second microphone. Furthermore, the surface mountable microphone package comprises a first opening for the first microphone and a second opening for the second microphone. The first opening and the second opening are arranged on opposite sides of the surface mountable microphone package.
    Type: Grant
    Filed: February 15, 2016
    Date of Patent: June 12, 2018
    Assignee: Infineon Technologies AG
    Inventors: Klaus Elian, Horst Theuss, Thomas Mueller
  • Patent number: 9984988
    Abstract: A flip chip assembly is disclosed that includes a die with die circuitry and a plurality of electrical contacts electrically connected to the die circuitry. A substrate includes electrical contacts that are juxtaposed with and electrically connected to corresponding die electrical contacts. A passive component is disposed between the die and the substrate, and includes a dielectric disposed between a first electrode and a second electrode. The first electrode is electrically connected to a first of the die electrical contacts and a corresponding substrate electrical contact, and the second electrode is electrically connected to a second of the die electrical contacts and a corresponding substrate electrical contact.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: May 29, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jean Audet, Luc G. Guerin, Richard Langlois, Stephan L. Martel, Sylvain E. Ouimet
  • Patent number: 9974182
    Abstract: Provided is a circuit assembly that does not require e.g. bending of a terminal of an electronic component. A circuit assembly includes an electronic component that is to be mounted is connected to a conductive member through a first opening in a state in which its main body is disposed on one side of a substrate covering at least a part of the first opening formed in the substrate, and a first terminal is connected to a conductive pattern (a land) of the substrate, and a second terminal is connected to the conductive member through a second opening formed in the substrate.
    Type: Grant
    Filed: July 1, 2015
    Date of Patent: May 15, 2018
    Assignees: AutoNetworks Technologies, Ltd., Sumitomo Wiring Systems, Ltd., Sumitomo Electric Industries, Ltd.
    Inventor: Arinobu Nakamura
  • Patent number: 9935026
    Abstract: The present disclosure relates to an air-cavity package, which includes a bottom substrate, a top substrate, a perimeter wall, a bottom electronic component, and a top electronic component. The bottom substrate includes a bottom signal via extending through the bottom substrate and the top substrate includes a top signal via extending through the top substrate. The perimeter wall extends between a periphery of the top substrate and a periphery of the bottom substrate to form a cavity. The bottom electronic component is mounted on the bottom substrate, exposed to the cavity, and electrically coupled to the bottom signal via. The top electronic component is mounted on the top substrate, exposed to the cavity, and electrically coupled to the top signal via.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: April 3, 2018
    Assignee: Qorvo US, Inc.
    Inventors: Kevin J. Anderson, Ning Chen
  • Patent number: 9922957
    Abstract: A semiconductor device includes a substrate, a first electrode located on an upper surface of the substrate, and a second electrode located on a lower surface of the substrate and electrically connected to the first electrode. The semiconductor device further includes a first resist layer located on the upper surface of the substrate so as to surround the first electrode and spaced from the first electrode, and a second resist layer located on the lower surface of the substrate.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: March 20, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Shinya Watanabe
  • Patent number: 9900677
    Abstract: A wearable monitoring system includes a microelectromechanical (MEMS) microphone to receive acoustic signal data through skin of a user. An integrated circuit chip is bonded to and electrically connected to the MEMS microphone. A portable power source is connected to at least the integrated circuit chip. A flexible substrate is configured to encapsulate and affix the MEMS microphone and the integrated circuit chip to the skin of the user.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: February 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: Li-Wen Hung, John U. Knickerbocker
  • Patent number: 9875387
    Abstract: A fingerprint sensor is provided. The fingerprint sensor includes a multi-layer printed circuit board (PCB), a fingerprint sensing die and a molding compound. The multi-layer PCB includes a bottom dielectric layer, at least one intermediate dielectric layer disposed on the bottom dielectric layer, a top dielectric layer disposed on the intermediate dielectric layer and a trench. The trench is formed by digging out a portion of the intermediate dielectric layer and a portion of the top dielectric layer. The fingerprint sensing die is disposed in the trench of the multi-layer PCB and mounted on an upper surface of the bottom dielectric layer of the multi-layer PCB. The fingerprint sensing die includes a sensing array capable of sensing fingerprint information of a user. The fingerprint sensing die is covered by the molding compound, and the trench of the multi-layer PCB is filled with the molding compound.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: January 23, 2018
    Assignee: Egis Technology Inc.
    Inventor: Pin-Yu Chen