Component Within Printed Circuit Board Patents (Class 361/761)
  • Patent number: 11328968
    Abstract: An apparatus is provided which comprises: a plurality of dielectric layers forming a substrate, a plurality of first conductive contacts on a first surface of the substrate, a cavity in the first surface of the substrate defining a second surface parallel to the first surface, a plurality of second conductive contacts on the second surface of the substrate, one or more integrated circuit die(s) coupled with the second conductive contacts, and mold material at least partially covering the one or more integrated circuit die(s) and the first conductive contacts. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: May 10, 2022
    Assignee: Intel Corporation
    Inventors: Mitul Modi, Robert L. Sankman, Debendra Mallik, Ravindranath V. Mahajan, Amruthavalli P. Alur, Yikang Deng, Eric J. Li
  • Patent number: 11257775
    Abstract: Mechanisms for forming a semiconductor device are provided. The semiconductor device includes a contact pad over a substrate. The semiconductor device also includes a passivation layer over the substrate and a first portion of the contact pad, and a second portion of the contact pad is exposed through an opening. The semiconductor device further includes a post-passivation interconnect layer over the passivation layer and coupled to the second portion of the contact pad. In addition, the semiconductor device includes a bump over the post-passivation interconnect layer and outside of the opening. The semiconductor device also includes a diffusion barrier layer physically insulating the bump from the post-passivation interconnect layer while electrically connecting the bump to the post-passivation interconnect layer.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: February 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ying-Ju Chen, Hsien-Wei Chen
  • Patent number: 11244919
    Abstract: A package structure is provided comprising a die, a redistribution layer, at least one integrated passive device (IPD), a plurality of solder balls and a molding compound. The die comprises a substrate and a plurality of conductive pads. The redistribution layer is disposed on the die, wherein the redistribution layer comprises first connection structures and second connection structures. The IPD is disposed on the redistribution layer, wherein the IPD is connected to the first connection structures of the redistribution layer. The plurality of solder balls is disposed on the redistribution layer, wherein the solder balls are disposed and connected to the second connection structures of the redistribution layer. The molding compound is disposed on the redistribution layer, and partially encapsulating the IPD and the plurality of solder balls, wherein top portions of the solder balls and a top surface of the IPD are exposed from the molding compound.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: February 8, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Wen Hsiao, Chen-Shien Chen, Kuo-Ching Hsu, Mirng-Ji Lii
  • Patent number: 11236868
    Abstract: Various embodiments provide a light emitting diode (LED) module, an LED lighting device comprising an LED module, and methods for manufacturing an LED module and/or an LED lighting device. In one embodiment, the LED lighting device comprises a housing comprising a metal shell and defining a central opening; and an LED module having one or more LEDs mounted about a periphery of a first surface of the LED module. The LED module is oriented and retained within the central opening of the housing such that the first surface faces out of the central opening. Furthermore, the LED module is secured to the housing via the metal shell.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: February 1, 2022
    Assignee: Feit Electric Company, Inc.
    Inventor: Shen Yanwei
  • Patent number: 11232895
    Abstract: A coil component includes a magnetic section containing a resin material and a filler component containing a magnetic metal, a coil conductor embedded in the magnetic section, and outer plating electrodes electrically connected to the coil conductor. At least one end portion of the magnetic section has a concave indentation. The surface of the indentation is overlaid with a hydrophobic insulating film. The surface of the magnetic section except for the indentation and extended end surfaces of the coil conductor are overlaid with an insulating protective film. The magnetic section, the coil conductor, and the protective film form a component body. The outer electrodes are placed on both end portions of the component body that exclude the indentation.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: January 25, 2022
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Kousei Sato
  • Patent number: 11212919
    Abstract: A voltage regulator module includes a circuit board assembly, a magnetic core assembly and a molding compound layer. The circuit board assembly includes a printed circuit board and at least one switch element. The switch element is disposed on a first surface of the printed circuit board. Moreover, at least one first copper post, at least one second copper post, at least one third copper post and the magnetic core assembly are disposed on a second surface of the printed circuit board. The magnetic core assembly includes at least one opening. The at least one first copper post is penetrated through the corresponding opening, so that at least one inductor is defined by the at least one first copper post and the magnetic core assembly collaboratively. The molding compound layer encapsulates the printed circuit board and the magnetic core assembly in a double-sided molding manner.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: December 28, 2021
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Yahong Xiong, Shaojun Chen, Da Jin, Qinghua Su
  • Patent number: 11205759
    Abstract: A display apparatus includes a substrate including a display area, a peripheral area outside the display area, and a bending area bendable along a bending axis, and an anti-crack projection disposed in the peripheral area and extending along at least a part of an edge of the substrate. A portion of the anti-crack projection in the bending area is a bending portion. A preset area including the bending portion on the substrate is a first area. A preset area of the substrate disposed outside the first area, having substantially the same area as that of the first area, and including a part of the anti-crack projection is a second area. A portion of the anti-crack projection belonging to the second area is a flat portion. The area occupied by the bending portion in the first area is greater than the area occupied by the flat portion in the second area.
    Type: Grant
    Filed: July 5, 2019
    Date of Patent: December 21, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Yonghan Park, Sangmin Kim, Dongho Lee, Hyunjung Kim
  • Patent number: 11202373
    Abstract: A connector device that includes a circuit board; a connector attached to the circuit board; and a molded resin that covers the entire circuit board and part of the connector, wherein: a housing of the connector contains a resin material and fibrous inorganic fillers, a groove is formed in a region of a surface of the housing that is covered with the molded resin, the groove being formed by removing the resin material with the inorganic fillers remaining, and extending in a direction that intersects a mounting direction in which a counterpart connector is to be mounted to the connector, the groove has a depth and a width in a range from 50 ?m to 150 ?m inclusive, and the groove is filled with the molded resin.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: December 14, 2021
    Assignees: AUTONETWORKS TECHNOLOGIES, LTD., SUMITOMO WIRING SYSTEMS, LTD., SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Yu Muronoi, Naomichi Kawashima, Tatsuo Hirabayashi, Seiji Hashimoto, Iori Kobayashi, Yoshiaki Kado
  • Patent number: 11177199
    Abstract: A semiconductor package includes a semiconductor chip including a chip pad and an external bump pad electrically connected to the chip pad of the semiconductor chip. The external bump pad may include a trench portion extending from a perimeter surface of the external bump pad toward a center of the external bump pad. The semiconductor package includes an external connector on the external bump pad, with the external connector including a portion that is in the trench portion of the external bump pad.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: November 16, 2021
    Inventor: Gayoung Kim
  • Patent number: 11146224
    Abstract: A generator including a power combiner is provided. The power combiner includes a plurality of inputs, each input connectable to a respective power amplifier for receiving a respective power signal. A plurality of impedance matching circuit branches is connected to a respective one of the plurality of inputs. Each impedance matching circuit branch includes at least one high pass filter section and at least one low pass filter section through which the respective power signal passes. The impedance matching circuit branches are connected so as to combine the power signals from each power amplifier. An output is provided for outputting the combined power signal.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: October 12, 2021
    Assignee: Comet AG
    Inventors: Daniel Gruner, Anton Labanc, Cyril Guinnard
  • Patent number: 11147165
    Abstract: An interposer for a processor includes: an electrically insulating material having a first main side and a second main side opposite the first main side; a plurality of electrically conductive structures embedded in the electrically insulating material and configured to provide an electrical interface for a processor substrate at the first main side of the electrically insulating material and to provide electrical connections from the electrical interface to the second main side of the electrically insulating material; and a power device module embedded in the electrically insulating material and configured to convert a voltage provided at the second main side of the electrically insulating material to a lower voltage at the first main side of the electrically insulating material.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: October 12, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Danny Clavette, Darryl Galipeau
  • Patent number: 11101255
    Abstract: A 3D printable feedstock ink is disclosed for use in a 3D printing process where the ink is flowed through a printing nozzle. The ink may be made up of a non-conductive flowable material and a plurality of chiplets contained in the non-conductive flowable material in random orientations. The chiplets may form a plurality of percolating chiplet networks within the non-conductive flowable material as ones of the chiplets contact one another. Each one of the chiplets has a predetermined circuit characteristic which is responsive to a predetermined electrical signal, and which becomes electrically conductive when the predetermined electrical signal is applied to the ink, to thus form at least one conductive signal path through the ink.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: August 24, 2021
    Assignee: Lawrence Livermore National Security, LLC
    Inventors: Maxwell Murialdo, Yuliya Kanarska, Andrew Pascall
  • Patent number: 11088060
    Abstract: A package module includes a core structure including a dummy member, one or more electronic components disposed around the dummy member, and an insulating material covering at least a portion of each of the dummy member and the electronic components, the core structure including a first penetration hole passing through the dummy member and the insulating material, a semiconductor chip disposed in the first penetration hole and having an active surface on which a connection pad is disposed and an inactive surface, an encapsulant covering at least a portion of each of the core structure and the semiconductor chip and filling at least a portion of the first penetration hole, and a connection structure disposed on the core structure and the active surface and including a redistribution layer electrically connected to the electronic components and the connection pad.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: August 10, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jaekul Lee, Jinseon Park, Junwoo Myung
  • Patent number: 11076496
    Abstract: In accordance with the embodiments described herein, there is provided an enclosure system including an enclosure formed of an insulating material, and at least one heatsink arrangement formed of a thermally-conductive material. The heatsink arrangement includes a heat conductive surface configured as one of a pyramid, an inverted pyramid, a plateau, a spherical segment, and an inverted spherical segment. The heatsink arrangement in the enclosure system can be integrally formed from the enclosure such that a demarcation between the heatsink arrangement and the enclosure is water-tight. The enclosure and the heatsink arrangement can also be simultaneously integrally formed and enmeshed using additive manufacturing processes.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: July 27, 2021
    Inventors: Steven F Hurt, Cynthia Hurt
  • Patent number: 11056444
    Abstract: A surface-mountable component is disclosed. The surface-mountable component may include a substrate having a side surface and a top surface that is perpendicular to the side surface. The component may include an element layer formed on the top surface of the substrate. The element layer may include a thin-film element and a contact pad electrically connected with the thin-film element. The contact pad may extend to the side surface of the substrate. The component may include a terminal that is electrically connected with the contact pad at a connection area. The connection area may be parallel with the top surface of the substrate. The terminal may have a visible edge surface that is approximately aligned with the side surface of the substrate. The visible edge surface may be visible for inspection when the surface-mountable component is mounted to a mounting surface.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: July 6, 2021
    Assignee: AVX Corporation
    Inventors: Yehuda Seidman, Elinor O'Neill, Dan Rozbroj
  • Patent number: 11049825
    Abstract: A method for producing a semiconductor device of the present invention includes: step (I) of disposing one or more semiconductor elements each having an active surface, on a thermosetting resin film containing a thermosetting resin composition, such that the thermosetting resin film and the active surfaces of the semiconductor elements come into contact; step (II) of encapsulating the semiconductor elements disposed on the thermosetting resin film with a member for semiconductor encapsulation; step (III) of providing openings in the thermosetting resin film or a cured product thereof after step (II), the openings extending to the active surfaces of the semiconductor elements; and step (IV) of filling the openings with a conductor or forming a conductor layer inside the openings.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: June 29, 2021
    Assignee: Showa Denko Materials Co., Ltd.
    Inventors: Aya Kasahara, Toshihisa Nonaka, Daisuke Fujimoto, Naoya Suzuki
  • Patent number: 11018111
    Abstract: A leadless integrated circuit (IC) package includes a spaced apart plurality of lead terminals on at least two sides of the leadless IC package, and an IC die including a substrate having at least a semiconductor surface including circuitry coupled to bond pads with the bond pads having bonding features thereon. The bonding features are flip chip bonded to the plurality of lead terminals. Mold compound is above the IC die and between adjacent lead terminals. The lead terminals and the substrate both extend out to have exposed surfaces at edges of the leadless IC package, and the lead terminals also provide a back side bondable contact.
    Type: Grant
    Filed: May 27, 2019
    Date of Patent: May 25, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Rongwei Zhang, James Huckabee, Vikas Gupta
  • Patent number: 10998247
    Abstract: A board includes: a core structure; one or more first passive components embedded in the core structure; a first build-up structure disposed on one side of the core structure and including first build-up layers and first wiring layers; and a second build-up structure disposed on the other side of the core structure and including second build-up layers and second wiring layers. One surface of a first core layer contacting a first insulating layer is coplanar with one surface of each of the one or more first passive components contacting a first insulating layer, the other surface of each of the one or more first passive components covered with a second insulating layer is spaced apart from a second core layer, and the one or more first passive components are electrically connected to at least one of the plurality of first wiring layers and the plurality of second wiring layers.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: May 4, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung Hyun Cho, Young Sik Hur, Won Wook So, Kyung Hwan Ko, Yong Ho Baek, Yong Duk Lee
  • Patent number: 10974443
    Abstract: A method, system, and apparatus for fabricating a three-dimensional circuit is provided. In an embodiment, a method for fabricating a three-dimensional circuit by an additive manufacturing process includes determining a shape, location, and spatial orientation of a number of components, a number of dielectrics, and a number of metal interconnects for the three dimensional circuit. The method also includes obtaining fused filament fabrication (FFF) specific actions for a number of dielectric materials and the metal interconnects. The method also includes separating tool paths of the dielectric material and the metal interconnects into individual tool paths for each of the dielectric materials and the metal interconnects. The method also includes removing specific actions for one of the individual toolpaths from an FFF specific action. The method also includes rewriting the one of the individual toolpaths into micro-dispensing actions to control a tool for micro-dispensing ink.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: April 13, 2021
    Assignee: Board of Regents, The University of Texas System
    Inventors: Raymond C. Rumpf, Cesar Luis Valle, Gilbert Carranza, Ubaldo Robles
  • Patent number: 10980131
    Abstract: The disclosure relates to systems, methods and compositions for direct printing of printed circuit boards with embedded integrated chips. Specifically, the disclosure relates to systems methods and compositions for the direct, top-down inkjet printing of printed circuit board with embedded chip and/or chip packages using a combination of print heads with conductive and dielectric ink compositions, creating predetermined dedicated compartments for locating the chips and/or chip packages and covering these with an encapsulating layer while maintaining interconnectedness among the embedded chips. Placing of the chips can be done automatically using robotic arms.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: April 13, 2021
    Assignee: Nano Dimension Technologies, Ltd.
    Inventor: Dan Kozlovski
  • Patent number: 10958005
    Abstract: Apparatuses for direct cabled connections of fabric signals—i.e., high-speed data signals exchanged between computer processors and peripheral devices. Specifically, varying apparatus configurations are outlined herein for minimizing, if not eliminating, the routing of these fabric signals through printed circuit boards, which tend to cause signal quality degradation due to phenomena such as the skin effect and dielectric loss.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: March 23, 2021
    Assignee: Dell Products L.P.
    Inventor: Shawn Joel Dube
  • Patent number: 10952310
    Abstract: A high-frequency module (1) includes a substrate (10), a first electronic component (13) and a second electronic component (14) that are provided on the substrate (10), an insulating layer (15) that covers a part of a side surface of the first electronic component (13) and a side surface and a top surface of the second electronic component (14), and a heat-dissipating layer (16) that covers at least a top surface of the first electronic component (13) and a portion of the side surface of the first electronic component (13) excluding the portion of the side surface of the first electronic component (13) in contact with the insulating layer (15).
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: March 16, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Syuichi Onodera
  • Patent number: 10952319
    Abstract: An electronic component embedded substrate includes a core layer having a first cavity and a second cavity on a first surface and a second surface of the core layer, respectively, the second surface opposite to the first surface in a thickness direction of the core layer; an electronic component disposed in the first cavity; a first insulating material covering at least a portion of the electronic component; a first wiring layer disposed on the first insulating material and connected to the electronic component; a built-in block disposed in the second cavity; and a second insulating material covering at least a portion of the built-in block.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: March 16, 2021
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Young Kwan Lee, Kyoung Jun Kim, Yong Hoon Kim, Seung Eun Lee, Hak Chun Kim
  • Patent number: 10905016
    Abstract: A method of manufacturing a component carrier is disclosed. The method includes providing a first component carrier body having at least one first electrically insulating layer structure and at least one first electrically conductive layer structure, providing a second component carrier body having at least one second electrically insulating layer structure and at least one second electrically conductive layer structure, providing at least a part of at least one of the first component carrier body and the second component carrier body of an at least partially uncured material, and interconnecting the first component carrier body with the second component carrier body by curing the at least partially uncured material.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: January 26, 2021
    Assignee: AT & Austria Technologie & Systemtechnik Aktiengesellschaft
    Inventors: Gernot Grober, Sabine Liebfahrt, Marco Gavagnin
  • Patent number: 10882248
    Abstract: A three dimensional printing system for producing a three dimensional article of manufacture includes a build platform, a powder dispensing apparatus, a light emitting device head, a drop ejecting head, a movement mechanism, and a controller. The light emitting device head may be a vertical cavity surface-emitting laser (VCSEL) head that has a columnar arrangement of VCSELs that emit light having a defined spectral distribution. The drop ejecting head is configured to separately eject a plurality of different inks having correspondingly different absorption coefficients for the defined spectral distribution. The controller operates the powder dispensing apparatus to dispense powder, move and operate the drop ejecting head to define an array of inked pixels, and move and operate the VCSEL head to fuse the inked pixels. The controller varies an energy output of the VCSELs in correspondence with a variation of an absorption coefficient of the inked pixels.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: January 5, 2021
    Assignee: 3D Systems, Inc.
    Inventor: James Francis Smith, III
  • Patent number: 10868209
    Abstract: A sensor element is disclosed.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: December 15, 2020
    Assignee: OSRAM OLED GMBH
    Inventors: Choon Kim Lim, Choo Kean Lim, Jeok Pheng Go
  • Patent number: 10856723
    Abstract: A medical circuit board includes a substrate on which a wiring pattern is formed, a plurality of electronic components mounted in a mounting area on the substrate, a resinous sealing member covering the plurality of electronic components, with which the plurality of electronic components are sealed to the substrate, and a detection unit provided in an area other than the mounting area on the substrate and detecting an infiltration of a liquid from an interface between the substrate and the sealing member into the mounting area. At least a part of the detection unit is covered with the sealing member and sealed with the sealing member to the substrate.
    Type: Grant
    Filed: October 9, 2018
    Date of Patent: December 8, 2020
    Assignee: SONY OLYMPUS MEDICAL SOLUTIONS INC.
    Inventor: Masahiro Hagihara
  • Patent number: 10858244
    Abstract: Production of a device for connecting a nano-object to an external electrical system (SEE) including: a first chip provided with conducting areas (8a, 8b) and a first nano-object (50) connected to the conducting areas, the first chip being assembled on a support (70) such that the first nano-object is arranged facing an upper face of the support, the device being further provided with first connection elements (80a, 80b) capable of being connected to the external electrical system and arranged on and in contact with the first conducting areas (8a, 8b), the first connection elements being formed on the side of the upper face of the support (70) and being accessible from the side of the upper face of the support.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: December 8, 2020
    Assignee: Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Aurelie Thuaire, Patrick Reynaud, Patrick Leduc, Emmanuel Rolland
  • Patent number: 10863631
    Abstract: A manufacturing method, wherein the method includes providing a layer stack having at least partially uncured component carrier material, arranging a plurality of components in recesses of the layer stack, integrally connecting the components with the layer stack by curing the component carrier material, and applying a high temperature robust dielectric structure on a main surface of the cured layer stack with the components therein.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: December 8, 2020
    Assignee: AT&S Austria Technologie & Systemtechnik Aktiengesellschaft
    Inventors: Johannes Stahr, Timo Schwarz, Mario Schober
  • Patent number: 10813227
    Abstract: In a component press-bonding device that performs work related to component mounting on a board after a mark provided on a transparent end region of the board is recognized, an imaging camera provided with an imaging optical axis extending downwards, a light emitter that irradiates the end region with illumination light from above the board in a state where the mark is positioned within an imaging visual field of the imaging camera, and a light reflecting member that is provided below the imaging camera and reflects the illumination light, which is emitted by the light emitter and is transmitted downwards through the end region, back to the end region are included. The imaging camera images the mark under the illumination light, which is reflected by the light reflecting member and is transmitted upwards through the end region.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: October 20, 2020
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Toshihiko Tsujikawa, Akira Kameda
  • Patent number: 10756023
    Abstract: A semiconductor package includes a connection member and a supporting member. The connection member has first and second surfaces opposing each other and a redistribution layer. The supporting member is disposed on the first surface of the connection member, has a first through-hole and a second through-hole spaced apart from each other, and has a blocking layer disposed on at least an inner surface of the second through-hole. A semiconductor chip is disposed in the first through-hole and has connection pads connected to the redistribution layer. At least one passive component is disposed in the second through-hole and has connection terminals connected to the redistribution layer. An encapsulant encapsulates the semiconductor chip and the at least one passive component in the first and second through-holes, respectively. An electromagnetic band-gap (EBG) structure is embedded in the supporting member.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: August 25, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Han Kim, Hyung Joon Kim
  • Patent number: 10734170
    Abstract: A resin structure includes a molded resin element and a push-type switch. The push-type switch includes a receptacle whereon a first terminal and a second terminal are secured, the first terminal and the second terminal configured to connect to an electrical circuit; a button unit protruding from the receptacle; and a contact spring unit configured to move with the button unit, to electrically connect between the first terminal and the second terminal, and to generate an opposing force relative to a pressure applied between the receptacle and the button unit. The receptacle stores the button unit and the contact spring unit. The receptacle of the push-type switch is embedded in the molded resin element with the button unit exposed from the molded resin element.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: August 4, 2020
    Assignee: OMRON Corporation
    Inventor: Wakahiro Kawai
  • Patent number: 10641820
    Abstract: Apparatus and methods for detecting and identifying a cause of a hot-switching event in an automated test system. One or more antennae positioned near mechanical relays in the system may be used to sense electromagnetic radiation. The antennae may be configured to respond to electromagnetic radiation of the type generated during a hot-switching event. Signals measured by the antennae may be processed to determine whether the signals have characteristics of hot-switching events. Processing may entail generating a signal envelope and determining whether the envelope has characteristics indicative of a hot-switching event. When a hot-switching event is detected, information to correlate the event to other events in the test system may also be captured. That information may be time information, enabling program test-system program instructions executing at the time of the event to be identified, such that the test system may be reprogrammed to avoid hot-switching events.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: May 5, 2020
    Assignee: Teradyne, Inc.
    Inventors: Alan B. Hussey, Richard John Burns, Gregory Smith, Mark Alan Levin
  • Patent number: 10629476
    Abstract: A package includes a device die, a molding material molding the device die therein, a through-via substantially penetrating through the molding material, wherein the through-via has an end. The end of the through-via is tapered and has rounded sidewall surfaces. The package further includes a redistribution line electrically coupled to the through-via.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: April 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Hsien-Wei Chen
  • Patent number: 10593568
    Abstract: Semiconductor devices having a semiconductor die electrically coupled to a redistribution structure and a molded material over the redistribution structure are disclosed herein, along with associated systems and methods. In one embodiment, a semiconductor device includes a semiconductor die attached to a first side of a substrate-free redistribution structure, and a plurality of conductive columns extending through a molded material disposed on the first side of the redistribution structure. The semiconductor device can also include a second redistribution structure on the molded material and electrically coupled to the conductive columns. A semiconductor device can be manufactured using a single carrier and requiring processing on only a single side of the semiconductor device.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: March 17, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Chan H. Yoo, John F. Kaeding, Ashok Pachamuthu, Mark E. Tuttle
  • Patent number: 10580738
    Abstract: Direct bonding heterogeneous integration packaging structures and processes include a packaging substrate with first and second opposing surfaces. A trench or a pedestal is provided in the first surface. A bridge is disposed in the trench or is adjacent the pedestal sidewall, wherein the bridge includes an upper surface coplanar with the first surface of the package substrate. At least two chips in a side by side proximal arrangement overly the bridge and the packaging substrate, wherein the bridge underlies peripheral edges of the at least two chips in the side by side proximal arrangement. The at least two chips include a plurality of electric connections that are directly coupled to corresponding electrical connections on the bridge and on the packaging substrate.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: March 3, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kamal K. Sikka, Jon A. Casey, Joshua Rubin, Arvind Kumar, Dinesh Gupta, Charles L. Arvin, Mark W. Kapfhammer, Steve Ostrander, Maryse Cournoyer, Valérie A. Oberson, Lawrence A. Clevenger
  • Patent number: 10559905
    Abstract: Implementations of pins for semiconductor packages may include: an upper contact portion having a contact surface configured to mechanically and electrically couple with a pin receiver; a lower portion having a vertical stop and at least two curved legs; a horizontal base coupled directly to the at least two curved legs and configured to be soldered to a substrate to mechanically and electrically couple the pin to the substrate, the horizontal base having an upper contact surface, and; a gap between a bottom contact surface of the vertical stop and the upper contact surface of the horizontal base; wherein the at least two curved legs are configured to flex to allow the bottom contact surface of the vertical stop to move toward the upper contact surface of the horizontal base in response to a pressure applied to the pin along a direction collinear with a longest length of the pin toward the upper contact surface, and; wherein the vertical stop is configured to stop movement of the pin when the bottom contact s
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: February 11, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Yushuang Yao, Chee Hiong Chew, Atapol Prajuckamol
  • Patent number: 10551697
    Abstract: An electrooptic display device includes a TFT substrate, a touch panel superimposed and placed on the TFT substrate, a circuit board spaced apart from the TFT substrate and the touch panel, one side of the circuit board facing the TFT substrate and the touch panel, a plurality of first FPCs each including one end electrically connected to one side of the TFT substrate, and the other end electrically connected to one side of the circuit board, and a second FPC that is electrically connected to the touch panel and extends in parallel to the first FPCs. The circuit board includes a cutout in a portion overlapping the second FPC on one side of the circuit board.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: February 4, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventor: Takahiro Ueno
  • Patent number: 10483345
    Abstract: An electronic component embedded substrate includes: a substrate that includes an insulating layer and has a first principal surface and a second principal surface on the opposite side of the first principal surface; and an electronic component that is embedded in the substrate and has a plurality of first terminals provided close to the first principal surface, a plurality of second terminals provided close to the second principal surface, and a capacity part provided between the plurality of first terminals and the plurality of second terminals. The electronic component is configured such that at least a part of the second terminals is embedded in the insulating layer. An insulating member is provided between the neighboring second terminals to be in contact with both of the neighboring second terminals. The insulating member and the insulating layer are formed of materials whose thermal expansion coefficients are different from each other.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: November 19, 2019
    Assignee: TDK CORPORATION
    Inventors: Mitsuhiro Tomikawa, Koichi Tsunoda, Kazuhiro Yoshikawa, Kenichi Yoshida
  • Patent number: 10475776
    Abstract: A fan-out semiconductor package module includes a core member having first and second through-holes. A semiconductor chip is in the first through-hole and has an active surface with a connection pad and an inactive surface opposing the active surface. Another passive component is in the second through-hole. An first encapsulant covers at least portions of the core member and the passive component, and fills at least a portion of the second through-hole. A reinforcing member is on the first encapsulant. A second encapsulant covers at least a portion of the semiconductor chip, and fills at least a portion of the first through-hole. A connection member is on the core member, the active surface of the semiconductor chip, and the passive component, and includes a redistribution layer electrically connected to the connection pad and the passive component.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: November 12, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yeong A Kim, Eun Sil Kim, Young Gwan Ko, Akihisa Kuroyanagi, Jin Su Kim, Jun Woo Myung
  • Patent number: 10475734
    Abstract: A semiconductor device package includes: (1) a substrate having a first surface and a second surface opposite to the first surface; (2) a first patterned conductive layer on the first surface of the substrate and having a first surface and a second surface, wherein the second surface of the first patterned conductive layer is adjacent to the substrate and opposite to the first surface of the first patterned conductive layer; (3) a first insulation layer on the first surface of the substrate and having a first surface and a second surface, wherein the second surface of the first insulation layer is adjacent to the substrate and opposite to the first surface of the first insulation layer; and (4) a second patterned conductive layer extending from the first surface of the first insulation layer to the second surface of the substrate, the second patterned conductive layer electrically connected to the first patterned conductive layer.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: November 12, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chien-Hua Chen, Sheng-Chi Hsieh, Cheng-Yuan Kung
  • Patent number: 10474868
    Abstract: A fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole of the first connection member and having an active surface with connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first connection member and the semiconductor chip; and a second connection member disposed on the first connection member and the semiconductor chip. The first connection member and the second connection member respectively include first redistribution layers and second redistribution layers electrically connected to the connection pads and formed of one or more layers, at least one of the first redistribution layers is disposed between a plurality of insulating layers of the first connection member, and at least one of the second redistribution layers includes sensor patterns recognizing a fingerprint.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: November 12, 2019
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Yong Ho Baek, Jung Hyun Cho, Byoung Chan Kim
  • Patent number: 10446455
    Abstract: A fingerprint sensor device and a method of making a fingerprint sensor device. As non-limiting examples, various aspects of this disclosure provide various fingerprint sensor devices, and methods of manufacturing thereof, that comprise a sensing area on a bottom side of a die without top side electrodes that senses fingerprints from the top side, and/or that comprise a sensor die directly electrically connected to conductive elements of a plate through which fingerprints are sensed.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: October 15, 2019
    Assignee: Amkor Technology, Inc.
    Inventors: Sung Sun Park, Ji Young Chung, Christopher Berry
  • Patent number: 10402620
    Abstract: A fan-out semiconductor package includes: a core member including a support layer, a first wiring layer, a second wiring layer, and through-vias and having a through-hole; a semiconductor chip disposed in the through-hole; an encapsulant covering the core member and the semiconductor chip and filling at least portions of the through-hole; a connection member including an insulating layer disposed on the first wiring layer and the semiconductor chip, a redistribution layer disposed on the insulating layer, first vias electrically connecting the redistribution layer and the connection pads to each other, and second vias electrically connecting the redistribution layer and the first wiring layer to each other; and a passivation layer disposed on the insulating layer and covering the redistribution layer, wherein a thickness of the passivation layer is within half a distance from an inactive surface of the semiconductor chip to a lower surface of the encapsulant.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: September 3, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byung Ho Kim, Da Hee Kim, Joon Sung Kim, Joo Young Choi, Hee Sook Park, Tae Wook Kim
  • Patent number: 10404226
    Abstract: A power amplifier module includes a substrate, a power amplifier having a first surface on which an electrode is defined and a second surface opposite the first surface, the first surface faces a principal surface of the substrate, a surface acoustic wave duplexer having a first surface on which an electrode is defined and a second surface opposite the first surface, the first surface faces the principal surface of the substrate, a heat dissipation unit defined on another principal surface of the substrate, a heat dissipation path that connects a connecting portion between the power amplifier and the principal surface to the heat dissipation unit, an insulating resin that covers the power amplifier and the surface acoustic wave duplexer, a conductive shield that covers the insulating resin, and a first conductive unit defined on the second surface of the surface acoustic wave duplexer and electrically connected to the conductive shield.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: September 3, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Takashi Kitahara, Hiroaki Nakayama, Tsunekazu Saimei, Hiroki Noto, Koichiro Kawasaki
  • Patent number: 10396046
    Abstract: Apparatuses, systems and methods associated with substrate design with a magnetic feature for fully integrated voltage regulator are disclosed herein. In embodiments, a substrate assembly may include a base substrate and one or more interconnect elements located at a first side of the base substrate, the one or more interconnect elements to be coupled to a semiconductor chip having an integrated voltage regulator (IVR). The substrate assembly may further include a magnetic feature located at a second side of the base substrate, the second side being opposite to the first side, wherein the magnetic feature extends along a portion of the second side of the base substrate that is opposite to where the IVR is to be located when the semiconductor chip is coupled to the one or more interconnect elements. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: August 27, 2019
    Assignee: Intel Corporation
    Inventors: Yikang Deng, Robert Sankman
  • Patent number: 10345874
    Abstract: The disclosed apparatus may include (1) a ganged heatsink base that (A) absorbs heat dissipated by a plurality of electronic components that consume differing amounts of power and (B) includes a plurality of thermal regions dedicated to absorbing the heat dissipated by the plurality of electronic components and (2) at least one thermal isolation engine that (A) is incorporated into the ganged heatsink base, (B) separates the plurality of thermal regions from one another, and (C) localizes the heat dissipated by the plurality of electronic components by maintaining at least some of the heat dissipated by one of the electronic components within the thermal region that absorbed the at least some of the heat such that the at least some of the heat does not migrate to another thermal region included in the ganged heatsink base. Various other apparatuses, systems, and methods are also disclosed.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: July 9, 2019
    Assignee: Juniper Networks, Inc
    Inventors: Susheela Nanjunda Rao Narasimhan, Basavaraja Munishamappa, Troy M. Sheets, Luis Zamora, Seongchul C. Kim
  • Patent number: 10333407
    Abstract: A multi-phase DC-DC converter includes a substrate having opposing first and second sides, a plurality of power stage packages attached to the first side of the substrate, each power stage package including active semiconductor components operable to provide an output phase of the multi-phase DC-DC converter, and a coupled inductor attached to the first side of the substrate and at least partly covering two or more of the power stage packages. The coupled inductor includes separate windings wound on the same core. Each winding of the coupled inductor electrically connects an output of one of the power stage packages at least partly covered by the coupled inductor to a metal trace on the substrate such that the outputs of the power stage packages at least partly covered by the coupled inductor are electrically connected to the same metal trace on the substrate.
    Type: Grant
    Filed: May 6, 2015
    Date of Patent: June 25, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Emil Todorov, Benjamim Tang, Darryl Tschirhart
  • Patent number: 10321088
    Abstract: Provided is a television apparatus including: a display panel which displays an image; a front cover which covers a front side of the television apparatus such that the display panel is exposed; a rear cover which is opposed to the front cover; a power supply which is supported between the front cover and the rear cover and includes an input connector mounted thereon to receive an input AC power for the display panel; an output connector configured to detachably coupled with the input connector to supply the input AC power, wherein the rear cover includes an inwardly-depressed portion at which a cover insertion hole is formed such that the output connector is coupled to the input connector through the cover insertion hole.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: June 11, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Young-deok Choi
  • Patent number: 10289892
    Abstract: The present disclosure provides a fingerprint chip package structure and a terminal. The fingerprint chip package structure includes a package body and a fingerprint identification chip. The package body includes a bottom surface and a lateral surface connected to the bottom surface, and defines a recessed portion at a junction of the bottom surface and the lateral surface. The fingerprint identification chip is received in the package body. The package body packages the fingerprint identification chip therein. The package body includes a first package portion and a second package portion coupled to the first package portion. The first package portion includes the bottom surface, and the second package portion includes the lateral surface. The fingerprint chip package structure is configured to be received in a decoration enclosure.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: May 14, 2019
    Assignee: GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP., LTD.
    Inventors: Shoukuan Wu, Zanjian Zeng