Component Within Printed Circuit Board Patents (Class 361/761)
  • Patent number: 10446455
    Abstract: A fingerprint sensor device and a method of making a fingerprint sensor device. As non-limiting examples, various aspects of this disclosure provide various fingerprint sensor devices, and methods of manufacturing thereof, that comprise a sensing area on a bottom side of a die without top side electrodes that senses fingerprints from the top side, and/or that comprise a sensor die directly electrically connected to conductive elements of a plate through which fingerprints are sensed.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: October 15, 2019
    Assignee: Amkor Technology, Inc.
    Inventors: Sung Sun Park, Ji Young Chung, Christopher Berry
  • Patent number: 10404226
    Abstract: A power amplifier module includes a substrate, a power amplifier having a first surface on which an electrode is defined and a second surface opposite the first surface, the first surface faces a principal surface of the substrate, a surface acoustic wave duplexer having a first surface on which an electrode is defined and a second surface opposite the first surface, the first surface faces the principal surface of the substrate, a heat dissipation unit defined on another principal surface of the substrate, a heat dissipation path that connects a connecting portion between the power amplifier and the principal surface to the heat dissipation unit, an insulating resin that covers the power amplifier and the surface acoustic wave duplexer, a conductive shield that covers the insulating resin, and a first conductive unit defined on the second surface of the surface acoustic wave duplexer and electrically connected to the conductive shield.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: September 3, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Takashi Kitahara, Hiroaki Nakayama, Tsunekazu Saimei, Hiroki Noto, Koichiro Kawasaki
  • Patent number: 10402620
    Abstract: A fan-out semiconductor package includes: a core member including a support layer, a first wiring layer, a second wiring layer, and through-vias and having a through-hole; a semiconductor chip disposed in the through-hole; an encapsulant covering the core member and the semiconductor chip and filling at least portions of the through-hole; a connection member including an insulating layer disposed on the first wiring layer and the semiconductor chip, a redistribution layer disposed on the insulating layer, first vias electrically connecting the redistribution layer and the connection pads to each other, and second vias electrically connecting the redistribution layer and the first wiring layer to each other; and a passivation layer disposed on the insulating layer and covering the redistribution layer, wherein a thickness of the passivation layer is within half a distance from an inactive surface of the semiconductor chip to a lower surface of the encapsulant.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: September 3, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byung Ho Kim, Da Hee Kim, Joon Sung Kim, Joo Young Choi, Hee Sook Park, Tae Wook Kim
  • Patent number: 10396046
    Abstract: Apparatuses, systems and methods associated with substrate design with a magnetic feature for fully integrated voltage regulator are disclosed herein. In embodiments, a substrate assembly may include a base substrate and one or more interconnect elements located at a first side of the base substrate, the one or more interconnect elements to be coupled to a semiconductor chip having an integrated voltage regulator (IVR). The substrate assembly may further include a magnetic feature located at a second side of the base substrate, the second side being opposite to the first side, wherein the magnetic feature extends along a portion of the second side of the base substrate that is opposite to where the IVR is to be located when the semiconductor chip is coupled to the one or more interconnect elements. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: August 27, 2019
    Assignee: Intel Corporation
    Inventors: Yikang Deng, Robert Sankman
  • Patent number: 10345874
    Abstract: The disclosed apparatus may include (1) a ganged heatsink base that (A) absorbs heat dissipated by a plurality of electronic components that consume differing amounts of power and (B) includes a plurality of thermal regions dedicated to absorbing the heat dissipated by the plurality of electronic components and (2) at least one thermal isolation engine that (A) is incorporated into the ganged heatsink base, (B) separates the plurality of thermal regions from one another, and (C) localizes the heat dissipated by the plurality of electronic components by maintaining at least some of the heat dissipated by one of the electronic components within the thermal region that absorbed the at least some of the heat such that the at least some of the heat does not migrate to another thermal region included in the ganged heatsink base. Various other apparatuses, systems, and methods are also disclosed.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: July 9, 2019
    Assignee: Juniper Networks, Inc
    Inventors: Susheela Nanjunda Rao Narasimhan, Basavaraja Munishamappa, Troy M. Sheets, Luis Zamora, Seongchul C. Kim
  • Patent number: 10333407
    Abstract: A multi-phase DC-DC converter includes a substrate having opposing first and second sides, a plurality of power stage packages attached to the first side of the substrate, each power stage package including active semiconductor components operable to provide an output phase of the multi-phase DC-DC converter, and a coupled inductor attached to the first side of the substrate and at least partly covering two or more of the power stage packages. The coupled inductor includes separate windings wound on the same core. Each winding of the coupled inductor electrically connects an output of one of the power stage packages at least partly covered by the coupled inductor to a metal trace on the substrate such that the outputs of the power stage packages at least partly covered by the coupled inductor are electrically connected to the same metal trace on the substrate.
    Type: Grant
    Filed: May 6, 2015
    Date of Patent: June 25, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Emil Todorov, Benjamim Tang, Darryl Tschirhart
  • Patent number: 10321088
    Abstract: Provided is a television apparatus including: a display panel which displays an image; a front cover which covers a front side of the television apparatus such that the display panel is exposed; a rear cover which is opposed to the front cover; a power supply which is supported between the front cover and the rear cover and includes an input connector mounted thereon to receive an input AC power for the display panel; an output connector configured to detachably coupled with the input connector to supply the input AC power, wherein the rear cover includes an inwardly-depressed portion at which a cover insertion hole is formed such that the output connector is coupled to the input connector through the cover insertion hole.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: June 11, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Young-deok Choi
  • Patent number: 10289892
    Abstract: The present disclosure provides a fingerprint chip package structure and a terminal. The fingerprint chip package structure includes a package body and a fingerprint identification chip. The package body includes a bottom surface and a lateral surface connected to the bottom surface, and defines a recessed portion at a junction of the bottom surface and the lateral surface. The fingerprint identification chip is received in the package body. The package body packages the fingerprint identification chip therein. The package body includes a first package portion and a second package portion coupled to the first package portion. The first package portion includes the bottom surface, and the second package portion includes the lateral surface. The fingerprint chip package structure is configured to be received in a decoration enclosure.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: May 14, 2019
    Assignee: GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP., LTD.
    Inventors: Shoukuan Wu, Zanjian Zeng
  • Patent number: 10268872
    Abstract: A fingerprint sensor package and method are provided. Embodiments include a sensor and a sensor surface material encapsulated within the fingerprint sensor package. An array of electrodes of the sensor are electrically connected using through vias that are located either in the sensor, in connection blocks separated from the sensor, or through connection blocks, or else connected through other connections such as wire bonds. A high voltage die is attached in order to increase the sensitivity of the fingerprint sensor.
    Type: Grant
    Filed: February 19, 2018
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chih Huang, Chih-Hua Chen, Yu-Jen Cheng, Chih-Wei Lin, Yu-Feng Chen, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
  • Patent number: 10256581
    Abstract: A connector housing mounting structure includes a connector housing; and a mounting member having a mounting surface. The connector housing includes a housing body, and a pair of flange portions extending from the housing body and having first mounting holes respectively. The mounting member includes a pair of first columnar portions protruding in parallel with each other from the mounting surface. Each of the first columnar portions is inserted into each of the first mounting holes, and the pair of flange portions is fixed to the mounting surface, thus the connector housing is regularly mounted on the mounting surface. A size of one of the flange portions in a width direction perpendicular to an extending direction of the flange portion is larger than the other flange portion in order that in case of incorrect mounting, the larger flange becomes obstructed and forms a visible indicator of misinstallation.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: April 9, 2019
    Assignee: YAZAKI CORPORATION
    Inventor: Yoshifumi Shinmi
  • Patent number: 10224217
    Abstract: A wafer level fan out package includes a semiconductor die having a first surface, a second surface, and a third surface. A stiffener is disposed on the third surface of the semiconductor die. A conductive via passes through the stiffener. First and second electrically conductive patterns electrically connected to the conductive via are disposed on the first and second surfaces of the semiconductor die and stiffener. Solder balls are electrically connected to the first or second electrically conductive patterns.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: March 5, 2019
    Assignee: Amkor Technology, Inc.
    Inventors: Jin Young Kim, Doo Hyun Park, Seung Jae Lee
  • Patent number: 10217684
    Abstract: A resin molding includes a semiconductor element, a circuit board, and a resin. A conductor connected to the semiconductor element is formed on the circuit board. The resin is adhered and integrated with the circuit board. A resin leakage suppression layer including a material having a higher thermal conductivity than that of a material forming a surface layer of the circuit board is provided in an edge region extending along a portion adhered to the resin in the circuit board and extending along at least one-side side surface of the resin.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: February 26, 2019
    Assignee: Hitachi Automotive Systems, Ltd.
    Inventors: Tsubasa Watanabe, Tsutomu Kono, Takayuki Yogo, Hiroaki Hoshika
  • Patent number: 10189703
    Abstract: A transducer module, comprising: a supporting substrate, having a first side and a second side; a cap, which extends over the first side of the supporting substrate and defines therewith a first chamber and a second chamber internally isolated from one another; a first transducer in the first chamber; a second transducer in the second chamber; and a control chip, which extends at least partially in the first chamber and/or in the second chamber and is functionally coupled to the first and second transducers for receiving, in use, the signals transduced by the first and second transducers.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: January 29, 2019
    Assignee: STMicroelectronics S.r.l.
    Inventors: Marco Omar Ghidoni, Roberto Brioschi
  • Patent number: 10186502
    Abstract: A component to be transferred to a receiving substrate is to be coupled both electrically and thermally. This is achieved by an integrated circuit comprising a substrate and a plurality of first components formed in or on the substrate. A plurality of metallization layers are provided. A second component applied by transfer printing is provided which is positioned, at least in part, on a level with and laterally adjacent to at least one of the plurality of metallization layers.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: January 22, 2019
    Assignee: X-FAB SEMICONDUCTOR FOUNDRIES GMBH
    Inventor: Ralf Lerner
  • Patent number: 10135224
    Abstract: An apparatus and method of forming a chip package with a waveguide for light coupling is disclosed. The method includes depositing an adhesive layer over a carrier. The method further includes depositing a laser diode (LD) die having a laser emitting area onto the adhesive layer and depositing a molding compound layer over the LD die and the adhesive layer. The method still further includes curing the molding compound layer and partially removing the molding compound layer to expose the laser emitting area. The method also includes depositing a ridge waveguide structure adjacent to the laser emitting area and depositing an upper cladding layer over the ridge waveguide structure.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: November 20, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Hao Tseng, Ying-Hao Kuo, Kuo-Chung Yee
  • Patent number: 10103087
    Abstract: The present invention provides a heat dissipation assembly and an electronic device, where the heat dissipation assembly includes: a shielding element, where a via hole is disposed on the shielding element, the shielding element is electrically connected to ground copper of a PCB board, and a heat-generating electronic element is disposed on the PCB board; a heat pipe, located on the via hole, where the heat pipe is electrically connected to the shielding element, and the heat pipe, the PCB board, and the shielding element form an electromagnetic shielding can that is used to accommodate the heat-generating electronic element; and an elastic thermal interface material, disposed between the heat pipe and the heat-generating electronic element and mutually fitted to the heat pipe and the heat-generating electronic element.
    Type: Grant
    Filed: March 18, 2014
    Date of Patent: October 16, 2018
    Assignee: HUAWEI DEVICE (DONGGUAN) CO., LTD.
    Inventors: Linfang Jin, Yongwang Xiao, Guoping Wang, Jie Zou, Hualin Li
  • Patent number: 10079254
    Abstract: Implementations of semiconductor packages may include: a die coupled to a glass lid; one or more inner walls having a first material coupled to the die; an outer wall having a second material coupled to the die; and a glass lid coupled to the die at the one or more inner walls and at the outer wall; wherein the outer wall may be located at the edge of the die and the glass lid and the one or more inner walls may be located within the perimeter of the outer wall at a predetermined distance from the perimeter of the outer wall; and wherein a modulus of the first material may be lower than a modulus of the second material.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: September 18, 2018
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Bingzhi Su, Derek Gochnour, Larry Kinsman
  • Patent number: 10080284
    Abstract: A circuit board structure includes an inner circuit structure and a first build-up circuit structure. The inner circuit structure includes a core layer having an upper surface and a lower surface, a first patterned circuit layer disposed on the upper surface, a second patterned circuit layer disposed on the lower surface and a conductive through hole connecting the first and the second patterned circuit layers. The first build-up circuit structure at least has a cavity and an inner dielectric layer. The inner dielectric layer has an opening communicating the cavity and a pad of the first patterned circuit layer is located in the opening. A hole diameter of the opening is smaller than a hole diameter of cavity. An inner surface of the inner dielectric layer exposed by the cavity and a top surface of the pad are coplanar or have a height difference.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: September 18, 2018
    Assignee: Unimicron Technology Corp.
    Inventors: Ming-Hao Wu, Shu-Sheng Chiang, Wei-Ming Cheng
  • Patent number: 10062635
    Abstract: A double-facing cooling-type power module has coolers on both sides. The power module includes: a first switch having the coolers on both sides; a second switch disposed independently from the first switch and having the coolers on both sides; and a common electrode coupled to both the first switch and the second switch.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: August 28, 2018
    Assignee: Hyundai Motor Company
    Inventor: Woo Yong Jeon
  • Patent number: 10055631
    Abstract: A sensor package and a method of forming a sensor package are disclosed. The sensor package comprises: a multilayer substrate comprising a mold compound layer and a plurality of patterned metal layers; an embedded die embedded in the multilayer substrate, wherein the mold compound layer of the multilayer substrate surrounds the embedded die; and, a sensing element disposed over the multilayer substrate, the sensing element comprising a first patterned metal layer electrically connected to the embedded die through the multilayer substrate.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: August 21, 2018
    Assignee: Synaptics Incorporated
    Inventors: Shengmin Wen, Brett Dunlap, Jay Kim
  • Patent number: 10015885
    Abstract: Provided are a printed circuit board and a method of manufacturing the printed circuit board, the printed circuit board including: a first element and a second element; a first base substrate including an embedding part in which the first element is embedded and a cavity into which the second element is mounted; and a second base substrate bonded to one surface of the first base substrate and including a first via for the second element.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: July 3, 2018
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Won Suk Jung, Yun Ho An, Sang Myung Lee, Joon Wook Han
  • Patent number: 9998812
    Abstract: A surface mountable microphone package comprises a first microphone and a second microphone. Furthermore, the surface mountable microphone package comprises a first opening for the first microphone and a second opening for the second microphone. The first opening and the second opening are arranged on opposite sides of the surface mountable microphone package.
    Type: Grant
    Filed: February 15, 2016
    Date of Patent: June 12, 2018
    Assignee: Infineon Technologies AG
    Inventors: Klaus Elian, Horst Theuss, Thomas Mueller
  • Patent number: 9984988
    Abstract: A flip chip assembly is disclosed that includes a die with die circuitry and a plurality of electrical contacts electrically connected to the die circuitry. A substrate includes electrical contacts that are juxtaposed with and electrically connected to corresponding die electrical contacts. A passive component is disposed between the die and the substrate, and includes a dielectric disposed between a first electrode and a second electrode. The first electrode is electrically connected to a first of the die electrical contacts and a corresponding substrate electrical contact, and the second electrode is electrically connected to a second of the die electrical contacts and a corresponding substrate electrical contact.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: May 29, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jean Audet, Luc G. Guerin, Richard Langlois, Stephan L. Martel, Sylvain E. Ouimet
  • Patent number: 9974182
    Abstract: Provided is a circuit assembly that does not require e.g. bending of a terminal of an electronic component. A circuit assembly includes an electronic component that is to be mounted is connected to a conductive member through a first opening in a state in which its main body is disposed on one side of a substrate covering at least a part of the first opening formed in the substrate, and a first terminal is connected to a conductive pattern (a land) of the substrate, and a second terminal is connected to the conductive member through a second opening formed in the substrate.
    Type: Grant
    Filed: July 1, 2015
    Date of Patent: May 15, 2018
    Assignees: AutoNetworks Technologies, Ltd., Sumitomo Wiring Systems, Ltd., Sumitomo Electric Industries, Ltd.
    Inventor: Arinobu Nakamura
  • Patent number: 9935026
    Abstract: The present disclosure relates to an air-cavity package, which includes a bottom substrate, a top substrate, a perimeter wall, a bottom electronic component, and a top electronic component. The bottom substrate includes a bottom signal via extending through the bottom substrate and the top substrate includes a top signal via extending through the top substrate. The perimeter wall extends between a periphery of the top substrate and a periphery of the bottom substrate to form a cavity. The bottom electronic component is mounted on the bottom substrate, exposed to the cavity, and electrically coupled to the bottom signal via. The top electronic component is mounted on the top substrate, exposed to the cavity, and electrically coupled to the top signal via.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: April 3, 2018
    Assignee: Qorvo US, Inc.
    Inventors: Kevin J. Anderson, Ning Chen
  • Patent number: 9922957
    Abstract: A semiconductor device includes a substrate, a first electrode located on an upper surface of the substrate, and a second electrode located on a lower surface of the substrate and electrically connected to the first electrode. The semiconductor device further includes a first resist layer located on the upper surface of the substrate so as to surround the first electrode and spaced from the first electrode, and a second resist layer located on the lower surface of the substrate.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: March 20, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Shinya Watanabe
  • Patent number: 9900677
    Abstract: A wearable monitoring system includes a microelectromechanical (MEMS) microphone to receive acoustic signal data through skin of a user. An integrated circuit chip is bonded to and electrically connected to the MEMS microphone. A portable power source is connected to at least the integrated circuit chip. A flexible substrate is configured to encapsulate and affix the MEMS microphone and the integrated circuit chip to the skin of the user.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: February 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: Li-Wen Hung, John U. Knickerbocker
  • Patent number: 9875387
    Abstract: A fingerprint sensor is provided. The fingerprint sensor includes a multi-layer printed circuit board (PCB), a fingerprint sensing die and a molding compound. The multi-layer PCB includes a bottom dielectric layer, at least one intermediate dielectric layer disposed on the bottom dielectric layer, a top dielectric layer disposed on the intermediate dielectric layer and a trench. The trench is formed by digging out a portion of the intermediate dielectric layer and a portion of the top dielectric layer. The fingerprint sensing die is disposed in the trench of the multi-layer PCB and mounted on an upper surface of the bottom dielectric layer of the multi-layer PCB. The fingerprint sensing die includes a sensing array capable of sensing fingerprint information of a user. The fingerprint sensing die is covered by the molding compound, and the trench of the multi-layer PCB is filled with the molding compound.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: January 23, 2018
    Assignee: Egis Technology Inc.
    Inventor: Pin-Yu Chen
  • Patent number: 9860990
    Abstract: A circuit board structure with chips embedded therein includes a multi-layer board and a power module embedded in the multi-layer board. The power module includes an insulating material, a power unit covered by the insulating material, and a circuit layer disposed on the insulating material. The power unit includes an electrically and thermally conductive carrier and a plurality of power chips. The electrically and thermally conductive carrier includes a transmitting portion and a carrying portion perpendicularly connected to the transmitting portion. Each power chip has a first electrode layer and an opposite second electrode layer. The first electrode layers are fixed on and electrically connected to the carrying portion in parallel, and the power chips are disposed at one side of the transmitting portion. The circuit layer is electrically connected to the electrically and thermally conductive carrier and the second electrode layers.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: January 2, 2018
    Assignee: BOARDTEK ELECTRONICS CORPORATION
    Inventors: Chien-Cheng Lee, Wen-Feng Cheng, Chung-Hsing Liao
  • Patent number: 9852973
    Abstract: A manufacturing method of a package substrate is provided. The method includes forming a first circuit layer on a carrier. A passive component is disposed on the first circuit layer and the carrier. A dielectric layer is formed on the carrier to embed the passive component and the first circuit layer in the dielectric layer. A second circuit layer is formed on the dielectric layer. The carrier is removed from the dielectric layer. A manufacturing method of a chip package is also provided.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: December 26, 2017
    Assignee: MEDIATEK INC.
    Inventors: Wen-Sung Hsu, Ta-Jen Yu
  • Patent number: 9832873
    Abstract: A circuit board structure includes an inner circuit structure and a first build-up circuit structure. The inner circuit structure includes a core layer having an upper surface and a lower surface, a first patterned circuit layer disposed on the upper surface, a second patterned circuit layer disposed on the lower surface and a conductive through hole connecting the first and the second patterned circuit layers. The first build-up circuit structure at least has a cavity and an inner dielectric layer. The inner dielectric layer has an opening connecting the cavity and exposing a portion of the first patterned circuit layer. A hole diameter of the opening is smaller than a hole diameter of cavity. A height difference is between an inner surface of the inner dielectric layer exposed by the cavity and a top surface of the first patterned circuit layer exposed by the opening.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: November 28, 2017
    Assignee: Unimicron Technology Corp.
    Inventors: Shu-Sheng Chiang, Ming-Hao Wu, Wei-Ming Cheng
  • Patent number: 9795025
    Abstract: A method of manufacturing a printed circuit board or a sub-assembly thereof by coupling at least two elements of insulating materials with different properties on adjacent side surfaces and covering the elements with a layer of conductive material and building up at least one further layer at least partly overlapping the at least two elements.
    Type: Grant
    Filed: July 12, 2012
    Date of Patent: October 17, 2017
    Assignee: AT&S AUSTRIA TECHNOLOGIE & SYSTEMTECHNIK AKTIENGESELLSCHAFT
    Inventors: Simon Sebanz, Hannes Voraberger
  • Patent number: 9781845
    Abstract: In a semi-finished product for the production of a printed circuit board, the semi-finished product comprising a plurality of having multiple insulating layers of a prepreg material and conductive layers (2, 2?) of a conductive material and further comprising having at least one electronic component embedded in at least one insulating layer the at least one electronic component is attached to a corresponding conductive layer by the aid of an Anisotropic Conductive Film and the Anisotropic Conductive Film as well as the prepreg material are in an unprocessed state.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: October 3, 2017
    Assignee: AT&S Austria Technologie & Systemtechnik Aktiengesellschaft
    Inventors: Johannes Stahr, Mikael Tuominen
  • Patent number: 9754852
    Abstract: A fingerprint sensor package, including a sensing side for sensing fingerprint information and a separate connection side for electrically connecting the fingerprint sensor package to a host device, is disclosed. The fingerprint sensor package can also include a sensor integrated circuit facing the sensing side and substantially surrounded by a fill material. The fill material includes vias at peripheral locations around the sensor integrated circuit. The fingerprint sensor package can further include a redistribution layer on the sensing side which redistributes connections of the sensor integrated circuit to the vias. The connections can further be directed through the vias to a ball grid array on the connection side. Some aspects also include electrostatic discharge traces positioned at least partially around a perimeter of the connection side. Methods of manufacturing are also disclosed.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: September 5, 2017
    Assignee: Amkor Technology, Inc.
    Inventors: Ronald Patrick Huemoeller, David Bolognia, Robert Francis Darveaux, Brett Arnold Dunlap
  • Patent number: 9741686
    Abstract: Some embodiments relate to an electronic package. The electronic package includes a substrate that includes a plurality of buildup layers. A first die is embedded in one of the buildup layers on one side of the substrate. A second die is bonded to the substrate within a cavity on an opposing side of the substrate. The first die and the second die may be electrically connected to conductors within the plurality of buildup layers. Other embodiments relate to method of connecting a first die to a second die to form an electronic package. The method includes attaching a first die to a core and fabricating a substrate onto the core. The method further includes creating a cavity in another of the buildup layers on an opposing side of the substrate and attaching a second die to the substrate within the cavity.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: August 22, 2017
    Assignee: Intel Corporation
    Inventors: Harold Ryan Chase, Mathew J Manusharow, Mihir K Roy
  • Patent number: 9743525
    Abstract: An electronic device embedded substrate and a method of manufacturing the same includes a substrate comprising a cavity formed therein, and an electronic device embedded in the cavity. The substrate and method thereof also include a first support pattern part formed on one surface of the substrate and pressing the electronic device to restrict a movement of the electronic device within the cavity, and a second support pattern part formed on another surface of the core substrate facing opposite to the one surface and extended toward an inside of the cavity to support the electronic device.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: August 22, 2017
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Bong-Soo Kim
  • Patent number: 9736575
    Abstract: A method of manufacturing a microphone includes steps of forming a sound element; forming a semiconductor chip; coupling the sound element and the semiconductor chip to each other; inserting the sound element and the semiconductor chip into a case; and forming a sound hole in a lower portion of the case and in a lower portion of the sound element.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: August 15, 2017
    Assignee: Hyundai Motor Company
    Inventors: Hyunsoo Kim, Sang Hyeok Yang, Sang Gyu Park, Ilseon Yoo
  • Patent number: 9711273
    Abstract: In an inductor component, fallen-off-filler marks that are formed as a result of a filler falling off from an outer surface of a component body are present in a dotted manner in portions of the outer surface that are in contact with outer electrodes. As a result of the filler falling off, a joining area at interfaces between the component body and the outer electrodes increases, and stress generated at the interfaces between the component body and the outer electrodes is reduced.
    Type: Grant
    Filed: June 10, 2015
    Date of Patent: July 18, 2017
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Hironori Suzuki, Masaki Kitajima
  • Patent number: 9693007
    Abstract: Provided is a television apparatus including: a display panel which displays an image; a front cover which covers a front side of the television apparatus such that the display panel is exposed; a rear cover which is opposed to the front cover; a power supply which is supported between the front cover and the rear cover and includes an input connector mounted thereon to receive an input AC power for the display panel; an output connector configured to detachably coupled with the input connector to supply the input AC power, wherein the rear cover includes an inwardly-depressed portion at which a cover insertion hole is formed such that the output connector is coupled to the input connector through the cover insertion hole.
    Type: Grant
    Filed: January 5, 2015
    Date of Patent: June 27, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Young-deok Choi
  • Patent number: 9691537
    Abstract: A power supply module is disclosed. the power supply module includes a coil including a coil body and connecting terminals; an electronic component including at least an integrated circuit chip; a magnetic core configured to enclose in and around the coil body, wherein a recess is provided on at least one side surface of the magnetic core, the electronic components are located in the recess, and an opening is provided on at least one side wall of the recess; a connector configured to be tightly attached to and cover the side surface where the recess is provided, and be electrically connected with the coil and the electronic component; and a heat conducting material provided in the recess and configured to cover the electronic component.
    Type: Grant
    Filed: March 19, 2014
    Date of Patent: June 27, 2017
    Assignee: Sumida Electric (H.K.) Company Limited
    Inventors: Douglas James Malcolm, Yanfei Liu, Guoping Zhang
  • Patent number: 9685880
    Abstract: A power conversion device includes a winding portion and a core portion. The winding portion can be embedded within a plurality of layers of a system printed circuit board. The core portion can be located within one or more elements of the power conversion device that are separate from the system printed circuit board.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: June 20, 2017
    Assignee: Apple Inc.
    Inventor: Sunil M. Akre
  • Patent number: 9674948
    Abstract: Rigid-flex-type circuit-board structure and manufacturing method, in which a flexible membrane and a sacrificial-material piece are attached to an insulator membrane in the location of the flexible zone. An insulator layer, which encloses within itself a sacrificial-material piece is manufactured on the surface of the conductor membrane. The flexible zone is formed in such a way that an opening is made in the insulator layer, through which the sacrificial-material piece is removed. The flexible zone comprises at least part of the flexible membrane as well as conductors, which are manufactured by patterning the insulator membrane at a suitable stage in the method.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: June 6, 2017
    Assignee: GE Embedded Electronics Oy
    Inventors: Antti Iihola, Tuomas Waris
  • Patent number: 9653805
    Abstract: An apparatus includes a die with through-silicon vias and radio frequency integrated circuit capabilities and it is vertically integrated with a phased-array antenna substrate. The through-silicon via and a radio frequency integrated circuit is coupled to a plurality of antenna elements disposed on the phased-array antenna substrate where each of the plurality of antenna elements is coupled to the through-silicon vias and radio frequency integrated circuit through a plurality of through-silicon vias. A process of assembling the through-silicon vias and radio frequency integrated circuit to the phased-array antenna substrate includes testing the apparatus.
    Type: Grant
    Filed: July 29, 2014
    Date of Patent: May 16, 2017
    Assignee: Intel Corporation
    Inventors: Telesphor Kamgaing, Valluri R. Rao, Georgios Yorgos Palaskas
  • Patent number: 9640521
    Abstract: A package structure includes a substrate having a first bond pad layer. A silicon bridge layer having one or more redistribution layers therein. The silicon bridge layer has a second bond pad, and the silicon bridge layer is attached to the substrate by an adhesive layer. A first die is coupled to the substrate and the silicon bridge layer. A second die is coupled to the silicon bridge layer, wherein the first die and the second die communicate with one another by way of the one or more redistribution layers. Power and/or ground connectors are coupled to the first bond pad and the second bond pad for enabling grounding and/or transferring power from the semiconductor substrate to the second die.
    Type: Grant
    Filed: January 2, 2015
    Date of Patent: May 2, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei Sen Chang, Yu-Feng Chen, Chen-Shien Chen, Mirng-Ji Lii
  • Patent number: 9627309
    Abstract: A wiring substrate includes a first wiring substrate, a first insulation layer stacked on the first wiring layer, and second and third insulation layers sequentially stacked on the first insulation layer. An electronic component is mounted on the first insulation layer in a cavity extending through the second and third insulation layers. The cavity is filled with a fourth insulation layer that entirely covers an upper surface of the third insulation layer and covers the electronic component. A second wiring layer is incorporated in the second and third insulation layers and electrically connected to the first wiring layer. The second wiring layer is electrically connected to a third wiring layer, which is stacked on the fourth insulation layer, by a first via wiring extending through the second and third insulation layers.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: April 18, 2017
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Kazuhiro Kobayashi, Junji Sato, Yasuhiko Kusama
  • Patent number: 9607762
    Abstract: There is provided a multilayer ceramic electronic part to be embedded in a board including: a ceramic body including dielectric layers; an active layer including a plurality of first and second internal electrodes; upper and lower cover layers disposed on and below the active layer, respectively; and first and second external electrodes formed on both end portions of the ceramic body, wherein a first internal electrode positioned at an outermost position among the first electrodes is connected to the first external electrode by at least one first via extended to at least one of first and second main surfaces of the ceramic body, and a second internal electrode positioned at an outermost position among the second internal electrodes is connected to the second external electrode by at least one second via extended to at least one of first and second main surfaces of the ceramic body.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: March 28, 2017
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Byoung Hwa Lee, Doo Young Kim, Hai Joon Lee, Jin Man Jung
  • Patent number: 9589939
    Abstract: An optoelectronic semiconductor chip includes an interconnection layer with a first electrically conductive contact layer, a second electrically conductive contact layer and an insulation layer, which is formed of an electrically insulating material. Further, the optoelectronic semiconductor chip includes two optoelectronic semiconductor bodies, each of which include an active region that is intended to generate radiation. The insulation layer is arranged on a top of the second electrically conductive contact layer facing the optoelectronic semiconductor bodies. The first electrically conductive contact layer is arranged on a top of the insulation layer remote from the second electrically conductive contact layer. The optoelectronic semiconductor bodies are interconnected electrically in parallel by the interconnection layer.
    Type: Grant
    Filed: May 27, 2013
    Date of Patent: March 7, 2017
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventor: Norwin von Malm
  • Patent number: 9583842
    Abstract: Aspects of the present disclosure provide an apparatus for wireless communications. The apparatus generally includes a printed circuit board (PCB) and a plurality of antenna elements. Each of the plurality of antenna elements is mechanically attached to a perimeter of the PCB via one or more solder elements. Each of the solder elements are spaced apart from each other and electrically isolated from each other in a vicinity of the antenna elements.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: February 28, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Elimelech Ganchrow, Alon Yehezkely
  • Patent number: 9585259
    Abstract: A printed circuit board (PCB) defines a first outer surface and a second outer surface that is opposite the first outer surface. The first outer surface of the PCB defines a recess. The PCB includes a signal layer between the first outer surface and the second surface with a first portion exposed within the recess and a second portion exposed within the recess. A component is disposed within the recess and connected to the first portion and the second portion of the signal layer such that an entirety of the component is within the recess and below the first surface.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: February 28, 2017
    Assignee: Juniper Networks, Inc.
    Inventors: Boris Reynov, Oscar Diaz-Landa, Shreeram Siddhaye, Chebrolu S. Srinivas, Lee M. Forbes, Mark Simpson, Mark Devenport
  • Patent number: 9536660
    Abstract: A chip electronic component may include: a magnetic body; and internal coil parts buried in the magnetic body. The magnetic body includes: a core layer including the internal coil parts; and upper and lower cover layers disposed on upper and lower portions of the core layer, respectively, the core layer having a level of magnetic permeability different from that of at least one of the upper and lower cover layers.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: January 3, 2017
    Assignees: HYUNDAI MOTOR COMPANY, KIA MOTOR CORPORATION
    Inventors: Moon Soo Park, Tae Young Kim, Dong Hwan Lee