Component Within Printed Circuit Board Patents (Class 361/761)
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Patent number: 11637057Abstract: Examples herein provide more integrated circuit packages that allow direct bonding of semiconductor chips to the package, smaller line/spacing of traces, and uniform vias with no capture or cover pads. For example, an integrated circuit (IC) package may include a plurality of pads and a plurality of traces on a substrate with at least two of the plurality of traces located between two of the plurality of pads, and a dielectric layer that completely covers the plurality of traces and partially covers the plurality of pads.Type: GrantFiled: December 21, 2019Date of Patent: April 25, 2023Assignee: QUALCOMM INCORPORATEDInventors: Kuiwon Kang, Chin-Kwan Kim, Aniket Patil, Jaehyun Yeon
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Patent number: 11576262Abstract: Fabric may include one or more conductive strands. An insertion tool may insert an electrical component into the fabric during formation of the fabric. The electrical component may include an electrical device mounted to a substrate and encapsulated by a protective structure. An interconnect structure such as a metal via or printed circuit layers may pass through an opening in the protective structure and may be used to couple a conductive strand to a contact pad on the substrate. The protective structure may be transparent or may include an opening so that light can be detected by or emitted from an optical device on the substrate. The protective structure may be formed using a molding tool that provides the protective structure with grooves or may be molded around a hollow conductive structure to create grooves. An electrical component mounted to the fabric may be embedded within printed circuit layers.Type: GrantFiled: March 25, 2021Date of Patent: February 7, 2023Assignee: Apple Inc.Inventors: Bilal Mohamed Ibrahim Kani, Benjamin J. Grena, Kyusang Kim, David M. Kindlon, Pierpaolo Lupo, Kishore N. Renjan, Manoj Vadeentavida
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Patent number: 11574858Abstract: A foil-based package and a method for manufacturing a foil-based package includes, among other things, a first and a second foil substrate. An electronic component is arranged between the two foil substrates in a sandwich-like manner. Due to the component thickness, there is a distance difference between the two foil substrates between the mounting area of the component and ears outside of the mounting area. The foil-based package and the method provides means for reducing and/or compensating a distance difference between the first foil substrate and the second foil substrate caused by the component thickness.Type: GrantFiled: February 25, 2020Date of Patent: February 7, 2023Assignee: Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V.Inventors: Erwin Yacoub-George, Waltraud Hell
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Patent number: 11563451Abstract: A radio frequency module including a module substrate including a first principal surface and a second principal surface; a power amplifier; an inductor disposed on the second principal surface and connected to the power amplifier; and an external connection terminal configured to receive a power supply voltage. The first external connection terminal is disposed on the second principal surface and connected to the power amplifier via the inductor.Type: GrantFiled: April 5, 2021Date of Patent: January 24, 2023Assignee: MURATA MANUFACTURING CO., LTD.Inventor: Naoya Matsumoto
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Patent number: 11552023Abstract: Certain aspects of the present disclosure generally relate to an embedded trace substrate (ETS) with one or more passive components embedded therein. Such an ETS may provide shorter routing, smaller loop area, and lower parasitics between a semiconductor die and a land-side passive component embedded in the ETS. One example embedded trace substrate generally includes a core, a first insulating material disposed above the core and having a first metal pattern embedded therein, a second insulating material disposed below the core and having a second metal pattern embedded therein, and one or more passive components embedded in the core.Type: GrantFiled: June 26, 2020Date of Patent: January 10, 2023Assignee: QUALCOMM IncorporatedInventors: Kuiwon Kang, Brigham Navaja, Marcus Hsu, Terence Cheung
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Patent number: 11545439Abstract: A package that includes a substrate and an integrated device. The substrate includes a core portion, a first substrate portion and a second substrate portion. The core portion includes a core layer and core interconnects. The first substrate portion is coupled to the core portion. The first substrate portion includes at least one first dielectric layer coupled to the core layer, and a first plurality of interconnects located in the at least one first dielectric layer. The second substrate portion is coupled to the core portion. The second substrate includes at least one second dielectric layer coupled to the core layer, and a second plurality of interconnects located in the at least one second dielectric layer. The core portion and the second substrate portion include a cavity. The integrated device is coupled to the first substrate portion through the cavity of the second substrate portion and the core portion.Type: GrantFiled: September 10, 2020Date of Patent: January 3, 2023Assignee: QUALCOMM INCORPORATEDInventors: Aniket Patil, Hong Bok We, Kuiwon Kang
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Patent number: 11539511Abstract: In one aspect, a system component includes a printed circuit (PC) board on which plural conductive ink segments are disposed. The system component also includes a sealed housing that houses the PC board. The plural conductive ink segments define a bit pattern to establish a key.Type: GrantFiled: August 8, 2019Date of Patent: December 27, 2022Assignee: Lenovo (Singapore) Pte. Ltd.Inventors: Robert J. Kapinos, Robert Norton, Russell Speight VanBlon, Scott Wentao Li
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Patent number: 11495379Abstract: A manufacturing method of an integrated driving module with energy conversion function includes providing a carrier board and forming an integrated electromagnetic induction component layer having a first dielectric layer, a plurality of conductive coil layers and a plurality of conductive connecting components on a surface of the carrier board. A patterned conductive circuit layer is formed on the integrated electromagnetic induction component layer, and electrically connecting to each other through the conductive connecting components. An embedded electrical component is patterned on the patterned conductive circuit layer. A conductive component is disposed on the patterned conductive circuit layer. Thereafter, the method forms a second dielectric layer to cover the embedded electrical component and the conductive component and removes the carrier board to form a plurality of integrated driving modules.Type: GrantFiled: May 20, 2020Date of Patent: November 8, 2022Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.Inventors: Wen-Hung Hu, Tsung-Yueh Chen
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Patent number: 11477892Abstract: A PCB, printed circuit board, structure for forming at least one embedded electronic component. The structure comprises a multi-layer PCB board comprising at least one through-hole via, the via comprising a plurality of electrodes vertically aligned within the via, each electrode comprising a plated ring; and an isolation section separating each of the electrodes.Type: GrantFiled: May 2, 2019Date of Patent: October 18, 2022Assignee: UNIVERSITY OF LIMERICKInventors: John Harris, Jennifer Hennessy, Seamus Clifford, Mark Southern
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Patent number: 11437247Abstract: A semiconductor package structure and a method of manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a conductive base, a first semiconductor die, a first conductive pillar, and a first encapsulant. The conductive base has a first surface. The first semiconductor die is disposed on the first surface of the conductive base. The first conductive pillar is disposed on the first semiconductor die. The first encapsulant is disposed on the first surface of the conductive base. The first encapsulant encapsulates the first semiconductor die. The first encapsulant includes an opening defined by the first conductive pillar.Type: GrantFiled: July 20, 2020Date of Patent: September 6, 2022Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Kay Stefan Essig, Jean Marc Yannou, Bradford Factor
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Patent number: 11375055Abstract: The disclosure relates to a universal holder assembly for mobile terminal equipment, for both physically holding and supporting same and for electrically recharging said mobile terminal equipment. This is achieved by a holder assembly comprising either a housing designed with a base surface, said housing having an interior designed to hold mobile terminal equipment, or an adapter element designed with a base surface that can be mechanically and physically connected to a mobile device, the inner and outer faces of the base surface being provided with electrical contact means which are designed and arranged such that an electrical connection can be established between mobile terminal equipment that can be positioned against or on the base surface and the contact means designed on the outer face. The outer face of the base surface is also provided with at least two recesses or depressions, each designed to physically receive an engagement means.Type: GrantFiled: July 3, 2018Date of Patent: June 28, 2022Assignee: Collatz+Trojan GmbHInventor: Michael Trojan
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Patent number: 11342298Abstract: A device includes a base substrate with a sensor component arranged thereon; a spacer layer on the base substrate, wherein the spacer layer is structured in order to predefine a cavity region, in which the sensor component is arranged in an exposed fashion on the base substrate, and a DAF tape element (DAF=Die-Attach-Film) on a stack element, wherein the DAF tape element mechanically fixedly connects the stack element to the spacer layer arranged on the base substrate and to obtain the cavity region.Type: GrantFiled: September 17, 2020Date of Patent: May 24, 2022Assignee: INFINEON TECHNOLOGIES AGInventors: Matthias Steiert, Karolina Gierl
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Patent number: 11328968Abstract: An apparatus is provided which comprises: a plurality of dielectric layers forming a substrate, a plurality of first conductive contacts on a first surface of the substrate, a cavity in the first surface of the substrate defining a second surface parallel to the first surface, a plurality of second conductive contacts on the second surface of the substrate, one or more integrated circuit die(s) coupled with the second conductive contacts, and mold material at least partially covering the one or more integrated circuit die(s) and the first conductive contacts. Other embodiments are also disclosed and claimed.Type: GrantFiled: December 27, 2016Date of Patent: May 10, 2022Assignee: Intel CorporationInventors: Mitul Modi, Robert L. Sankman, Debendra Mallik, Ravindranath V. Mahajan, Amruthavalli P. Alur, Yikang Deng, Eric J. Li
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Patent number: 11257775Abstract: Mechanisms for forming a semiconductor device are provided. The semiconductor device includes a contact pad over a substrate. The semiconductor device also includes a passivation layer over the substrate and a first portion of the contact pad, and a second portion of the contact pad is exposed through an opening. The semiconductor device further includes a post-passivation interconnect layer over the passivation layer and coupled to the second portion of the contact pad. In addition, the semiconductor device includes a bump over the post-passivation interconnect layer and outside of the opening. The semiconductor device also includes a diffusion barrier layer physically insulating the bump from the post-passivation interconnect layer while electrically connecting the bump to the post-passivation interconnect layer.Type: GrantFiled: July 1, 2019Date of Patent: February 22, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ying-Ju Chen, Hsien-Wei Chen
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Patent number: 11244919Abstract: A package structure is provided comprising a die, a redistribution layer, at least one integrated passive device (IPD), a plurality of solder balls and a molding compound. The die comprises a substrate and a plurality of conductive pads. The redistribution layer is disposed on the die, wherein the redistribution layer comprises first connection structures and second connection structures. The IPD is disposed on the redistribution layer, wherein the IPD is connected to the first connection structures of the redistribution layer. The plurality of solder balls is disposed on the redistribution layer, wherein the solder balls are disposed and connected to the second connection structures of the redistribution layer. The molding compound is disposed on the redistribution layer, and partially encapsulating the IPD and the plurality of solder balls, wherein top portions of the solder balls and a top surface of the IPD are exposed from the molding compound.Type: GrantFiled: March 28, 2019Date of Patent: February 8, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ching-Wen Hsiao, Chen-Shien Chen, Kuo-Ching Hsu, Mirng-Ji Lii
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Patent number: 11236868Abstract: Various embodiments provide a light emitting diode (LED) module, an LED lighting device comprising an LED module, and methods for manufacturing an LED module and/or an LED lighting device. In one embodiment, the LED lighting device comprises a housing comprising a metal shell and defining a central opening; and an LED module having one or more LEDs mounted about a periphery of a first surface of the LED module. The LED module is oriented and retained within the central opening of the housing such that the first surface faces out of the central opening. Furthermore, the LED module is secured to the housing via the metal shell.Type: GrantFiled: September 28, 2020Date of Patent: February 1, 2022Assignee: Feit Electric Company, Inc.Inventor: Shen Yanwei
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Patent number: 11232895Abstract: A coil component includes a magnetic section containing a resin material and a filler component containing a magnetic metal, a coil conductor embedded in the magnetic section, and outer plating electrodes electrically connected to the coil conductor. At least one end portion of the magnetic section has a concave indentation. The surface of the indentation is overlaid with a hydrophobic insulating film. The surface of the magnetic section except for the indentation and extended end surfaces of the coil conductor are overlaid with an insulating protective film. The magnetic section, the coil conductor, and the protective film form a component body. The outer electrodes are placed on both end portions of the component body that exclude the indentation.Type: GrantFiled: January 23, 2018Date of Patent: January 25, 2022Assignee: Murata Manufacturing Co., Ltd.Inventor: Kousei Sato
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Patent number: 11212919Abstract: A voltage regulator module includes a circuit board assembly, a magnetic core assembly and a molding compound layer. The circuit board assembly includes a printed circuit board and at least one switch element. The switch element is disposed on a first surface of the printed circuit board. Moreover, at least one first copper post, at least one second copper post, at least one third copper post and the magnetic core assembly are disposed on a second surface of the printed circuit board. The magnetic core assembly includes at least one opening. The at least one first copper post is penetrated through the corresponding opening, so that at least one inductor is defined by the at least one first copper post and the magnetic core assembly collaboratively. The molding compound layer encapsulates the printed circuit board and the magnetic core assembly in a double-sided molding manner.Type: GrantFiled: March 5, 2020Date of Patent: December 28, 2021Assignee: DELTA ELECTRONICS, INC.Inventors: Yahong Xiong, Shaojun Chen, Da Jin, Qinghua Su
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Patent number: 11205759Abstract: A display apparatus includes a substrate including a display area, a peripheral area outside the display area, and a bending area bendable along a bending axis, and an anti-crack projection disposed in the peripheral area and extending along at least a part of an edge of the substrate. A portion of the anti-crack projection in the bending area is a bending portion. A preset area including the bending portion on the substrate is a first area. A preset area of the substrate disposed outside the first area, having substantially the same area as that of the first area, and including a part of the anti-crack projection is a second area. A portion of the anti-crack projection belonging to the second area is a flat portion. The area occupied by the bending portion in the first area is greater than the area occupied by the flat portion in the second area.Type: GrantFiled: July 5, 2019Date of Patent: December 21, 2021Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Yonghan Park, Sangmin Kim, Dongho Lee, Hyunjung Kim
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Patent number: 11202373Abstract: A connector device that includes a circuit board; a connector attached to the circuit board; and a molded resin that covers the entire circuit board and part of the connector, wherein: a housing of the connector contains a resin material and fibrous inorganic fillers, a groove is formed in a region of a surface of the housing that is covered with the molded resin, the groove being formed by removing the resin material with the inorganic fillers remaining, and extending in a direction that intersects a mounting direction in which a counterpart connector is to be mounted to the connector, the groove has a depth and a width in a range from 50 ?m to 150 ?m inclusive, and the groove is filled with the molded resin.Type: GrantFiled: March 12, 2020Date of Patent: December 14, 2021Assignees: AUTONETWORKS TECHNOLOGIES, LTD., SUMITOMO WIRING SYSTEMS, LTD., SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Yu Muronoi, Naomichi Kawashima, Tatsuo Hirabayashi, Seiji Hashimoto, Iori Kobayashi, Yoshiaki Kado
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Patent number: 11177199Abstract: A semiconductor package includes a semiconductor chip including a chip pad and an external bump pad electrically connected to the chip pad of the semiconductor chip. The external bump pad may include a trench portion extending from a perimeter surface of the external bump pad toward a center of the external bump pad. The semiconductor package includes an external connector on the external bump pad, with the external connector including a portion that is in the trench portion of the external bump pad.Type: GrantFiled: March 3, 2020Date of Patent: November 16, 2021Inventor: Gayoung Kim
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Patent number: 11146224Abstract: A generator including a power combiner is provided. The power combiner includes a plurality of inputs, each input connectable to a respective power amplifier for receiving a respective power signal. A plurality of impedance matching circuit branches is connected to a respective one of the plurality of inputs. Each impedance matching circuit branch includes at least one high pass filter section and at least one low pass filter section through which the respective power signal passes. The impedance matching circuit branches are connected so as to combine the power signals from each power amplifier. An output is provided for outputting the combined power signal.Type: GrantFiled: November 18, 2019Date of Patent: October 12, 2021Assignee: Comet AGInventors: Daniel Gruner, Anton Labanc, Cyril Guinnard
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Patent number: 11147165Abstract: An interposer for a processor includes: an electrically insulating material having a first main side and a second main side opposite the first main side; a plurality of electrically conductive structures embedded in the electrically insulating material and configured to provide an electrical interface for a processor substrate at the first main side of the electrically insulating material and to provide electrical connections from the electrical interface to the second main side of the electrically insulating material; and a power device module embedded in the electrically insulating material and configured to convert a voltage provided at the second main side of the electrically insulating material to a lower voltage at the first main side of the electrically insulating material.Type: GrantFiled: October 17, 2019Date of Patent: October 12, 2021Assignee: Infineon Technologies Austria AGInventors: Danny Clavette, Darryl Galipeau
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Patent number: 11101255Abstract: A 3D printable feedstock ink is disclosed for use in a 3D printing process where the ink is flowed through a printing nozzle. The ink may be made up of a non-conductive flowable material and a plurality of chiplets contained in the non-conductive flowable material in random orientations. The chiplets may form a plurality of percolating chiplet networks within the non-conductive flowable material as ones of the chiplets contact one another. Each one of the chiplets has a predetermined circuit characteristic which is responsive to a predetermined electrical signal, and which becomes electrically conductive when the predetermined electrical signal is applied to the ink, to thus form at least one conductive signal path through the ink.Type: GrantFiled: December 13, 2018Date of Patent: August 24, 2021Assignee: Lawrence Livermore National Security, LLCInventors: Maxwell Murialdo, Yuliya Kanarska, Andrew Pascall
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Patent number: 11088060Abstract: A package module includes a core structure including a dummy member, one or more electronic components disposed around the dummy member, and an insulating material covering at least a portion of each of the dummy member and the electronic components, the core structure including a first penetration hole passing through the dummy member and the insulating material, a semiconductor chip disposed in the first penetration hole and having an active surface on which a connection pad is disposed and an inactive surface, an encapsulant covering at least a portion of each of the core structure and the semiconductor chip and filling at least a portion of the first penetration hole, and a connection structure disposed on the core structure and the active surface and including a redistribution layer electrically connected to the electronic components and the connection pad.Type: GrantFiled: November 6, 2019Date of Patent: August 10, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jaekul Lee, Jinseon Park, Junwoo Myung
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Patent number: 11076496Abstract: In accordance with the embodiments described herein, there is provided an enclosure system including an enclosure formed of an insulating material, and at least one heatsink arrangement formed of a thermally-conductive material. The heatsink arrangement includes a heat conductive surface configured as one of a pyramid, an inverted pyramid, a plateau, a spherical segment, and an inverted spherical segment. The heatsink arrangement in the enclosure system can be integrally formed from the enclosure such that a demarcation between the heatsink arrangement and the enclosure is water-tight. The enclosure and the heatsink arrangement can also be simultaneously integrally formed and enmeshed using additive manufacturing processes.Type: GrantFiled: April 27, 2020Date of Patent: July 27, 2021Inventors: Steven F Hurt, Cynthia Hurt
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Patent number: 11056444Abstract: A surface-mountable component is disclosed. The surface-mountable component may include a substrate having a side surface and a top surface that is perpendicular to the side surface. The component may include an element layer formed on the top surface of the substrate. The element layer may include a thin-film element and a contact pad electrically connected with the thin-film element. The contact pad may extend to the side surface of the substrate. The component may include a terminal that is electrically connected with the contact pad at a connection area. The connection area may be parallel with the top surface of the substrate. The terminal may have a visible edge surface that is approximately aligned with the side surface of the substrate. The visible edge surface may be visible for inspection when the surface-mountable component is mounted to a mounting surface.Type: GrantFiled: October 17, 2019Date of Patent: July 6, 2021Assignee: AVX CorporationInventors: Yehuda Seidman, Elinor O'Neill, Dan Rozbroj
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Patent number: 11049825Abstract: A method for producing a semiconductor device of the present invention includes: step (I) of disposing one or more semiconductor elements each having an active surface, on a thermosetting resin film containing a thermosetting resin composition, such that the thermosetting resin film and the active surfaces of the semiconductor elements come into contact; step (II) of encapsulating the semiconductor elements disposed on the thermosetting resin film with a member for semiconductor encapsulation; step (III) of providing openings in the thermosetting resin film or a cured product thereof after step (II), the openings extending to the active surfaces of the semiconductor elements; and step (IV) of filling the openings with a conductor or forming a conductor layer inside the openings.Type: GrantFiled: December 6, 2017Date of Patent: June 29, 2021Assignee: Showa Denko Materials Co., Ltd.Inventors: Aya Kasahara, Toshihisa Nonaka, Daisuke Fujimoto, Naoya Suzuki
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Patent number: 11018111Abstract: A leadless integrated circuit (IC) package includes a spaced apart plurality of lead terminals on at least two sides of the leadless IC package, and an IC die including a substrate having at least a semiconductor surface including circuitry coupled to bond pads with the bond pads having bonding features thereon. The bonding features are flip chip bonded to the plurality of lead terminals. Mold compound is above the IC die and between adjacent lead terminals. The lead terminals and the substrate both extend out to have exposed surfaces at edges of the leadless IC package, and the lead terminals also provide a back side bondable contact.Type: GrantFiled: May 27, 2019Date of Patent: May 25, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Rongwei Zhang, James Huckabee, Vikas Gupta
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Patent number: 10998247Abstract: A board includes: a core structure; one or more first passive components embedded in the core structure; a first build-up structure disposed on one side of the core structure and including first build-up layers and first wiring layers; and a second build-up structure disposed on the other side of the core structure and including second build-up layers and second wiring layers. One surface of a first core layer contacting a first insulating layer is coplanar with one surface of each of the one or more first passive components contacting a first insulating layer, the other surface of each of the one or more first passive components covered with a second insulating layer is spaced apart from a second core layer, and the one or more first passive components are electrically connected to at least one of the plurality of first wiring layers and the plurality of second wiring layers.Type: GrantFiled: July 26, 2019Date of Patent: May 4, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jung Hyun Cho, Young Sik Hur, Won Wook So, Kyung Hwan Ko, Yong Ho Baek, Yong Duk Lee
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Patent number: 10974443Abstract: A method, system, and apparatus for fabricating a three-dimensional circuit is provided. In an embodiment, a method for fabricating a three-dimensional circuit by an additive manufacturing process includes determining a shape, location, and spatial orientation of a number of components, a number of dielectrics, and a number of metal interconnects for the three dimensional circuit. The method also includes obtaining fused filament fabrication (FFF) specific actions for a number of dielectric materials and the metal interconnects. The method also includes separating tool paths of the dielectric material and the metal interconnects into individual tool paths for each of the dielectric materials and the metal interconnects. The method also includes removing specific actions for one of the individual toolpaths from an FFF specific action. The method also includes rewriting the one of the individual toolpaths into micro-dispensing actions to control a tool for micro-dispensing ink.Type: GrantFiled: November 8, 2019Date of Patent: April 13, 2021Assignee: Board of Regents, The University of Texas SystemInventors: Raymond C. Rumpf, Cesar Luis Valle, Gilbert Carranza, Ubaldo Robles
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Patent number: 10980131Abstract: The disclosure relates to systems, methods and compositions for direct printing of printed circuit boards with embedded integrated chips. Specifically, the disclosure relates to systems methods and compositions for the direct, top-down inkjet printing of printed circuit board with embedded chip and/or chip packages using a combination of print heads with conductive and dielectric ink compositions, creating predetermined dedicated compartments for locating the chips and/or chip packages and covering these with an encapsulating layer while maintaining interconnectedness among the embedded chips. Placing of the chips can be done automatically using robotic arms.Type: GrantFiled: January 24, 2018Date of Patent: April 13, 2021Assignee: Nano Dimension Technologies, Ltd.Inventor: Dan Kozlovski
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Patent number: 10958005Abstract: Apparatuses for direct cabled connections of fabric signals—i.e., high-speed data signals exchanged between computer processors and peripheral devices. Specifically, varying apparatus configurations are outlined herein for minimizing, if not eliminating, the routing of these fabric signals through printed circuit boards, which tend to cause signal quality degradation due to phenomena such as the skin effect and dielectric loss.Type: GrantFiled: January 31, 2020Date of Patent: March 23, 2021Assignee: Dell Products L.P.Inventor: Shawn Joel Dube
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Patent number: 10952310Abstract: A high-frequency module (1) includes a substrate (10), a first electronic component (13) and a second electronic component (14) that are provided on the substrate (10), an insulating layer (15) that covers a part of a side surface of the first electronic component (13) and a side surface and a top surface of the second electronic component (14), and a heat-dissipating layer (16) that covers at least a top surface of the first electronic component (13) and a portion of the side surface of the first electronic component (13) excluding the portion of the side surface of the first electronic component (13) in contact with the insulating layer (15).Type: GrantFiled: April 3, 2019Date of Patent: March 16, 2021Assignee: MURATA MANUFACTURING CO., LTD.Inventor: Syuichi Onodera
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Patent number: 10952319Abstract: An electronic component embedded substrate includes a core layer having a first cavity and a second cavity on a first surface and a second surface of the core layer, respectively, the second surface opposite to the first surface in a thickness direction of the core layer; an electronic component disposed in the first cavity; a first insulating material covering at least a portion of the electronic component; a first wiring layer disposed on the first insulating material and connected to the electronic component; a built-in block disposed in the second cavity; and a second insulating material covering at least a portion of the built-in block.Type: GrantFiled: March 11, 2020Date of Patent: March 16, 2021Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Young Kwan Lee, Kyoung Jun Kim, Yong Hoon Kim, Seung Eun Lee, Hak Chun Kim
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Patent number: 10905016Abstract: A method of manufacturing a component carrier is disclosed. The method includes providing a first component carrier body having at least one first electrically insulating layer structure and at least one first electrically conductive layer structure, providing a second component carrier body having at least one second electrically insulating layer structure and at least one second electrically conductive layer structure, providing at least a part of at least one of the first component carrier body and the second component carrier body of an at least partially uncured material, and interconnecting the first component carrier body with the second component carrier body by curing the at least partially uncured material.Type: GrantFiled: October 21, 2016Date of Patent: January 26, 2021Assignee: AT & Austria Technologie & Systemtechnik AktiengesellschaftInventors: Gernot Grober, Sabine Liebfahrt, Marco Gavagnin
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Patent number: 10882248Abstract: A three dimensional printing system for producing a three dimensional article of manufacture includes a build platform, a powder dispensing apparatus, a light emitting device head, a drop ejecting head, a movement mechanism, and a controller. The light emitting device head may be a vertical cavity surface-emitting laser (VCSEL) head that has a columnar arrangement of VCSELs that emit light having a defined spectral distribution. The drop ejecting head is configured to separately eject a plurality of different inks having correspondingly different absorption coefficients for the defined spectral distribution. The controller operates the powder dispensing apparatus to dispense powder, move and operate the drop ejecting head to define an array of inked pixels, and move and operate the VCSEL head to fuse the inked pixels. The controller varies an energy output of the VCSELs in correspondence with a variation of an absorption coefficient of the inked pixels.Type: GrantFiled: June 27, 2018Date of Patent: January 5, 2021Assignee: 3D Systems, Inc.Inventor: James Francis Smith, III
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Patent number: 10868209Abstract: A sensor element is disclosed.Type: GrantFiled: February 23, 2017Date of Patent: December 15, 2020Assignee: OSRAM OLED GMBHInventors: Choon Kim Lim, Choo Kean Lim, Jeok Pheng Go
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Patent number: 10856723Abstract: A medical circuit board includes a substrate on which a wiring pattern is formed, a plurality of electronic components mounted in a mounting area on the substrate, a resinous sealing member covering the plurality of electronic components, with which the plurality of electronic components are sealed to the substrate, and a detection unit provided in an area other than the mounting area on the substrate and detecting an infiltration of a liquid from an interface between the substrate and the sealing member into the mounting area. At least a part of the detection unit is covered with the sealing member and sealed with the sealing member to the substrate.Type: GrantFiled: October 9, 2018Date of Patent: December 8, 2020Assignee: SONY OLYMPUS MEDICAL SOLUTIONS INC.Inventor: Masahiro Hagihara
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Patent number: 10863631Abstract: A manufacturing method, wherein the method includes providing a layer stack having at least partially uncured component carrier material, arranging a plurality of components in recesses of the layer stack, integrally connecting the components with the layer stack by curing the component carrier material, and applying a high temperature robust dielectric structure on a main surface of the cured layer stack with the components therein.Type: GrantFiled: March 6, 2019Date of Patent: December 8, 2020Assignee: AT&S Austria Technologie & Systemtechnik AktiengesellschaftInventors: Johannes Stahr, Timo Schwarz, Mario Schober
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Patent number: 10858244Abstract: Production of a device for connecting a nano-object to an external electrical system (SEE) including: a first chip provided with conducting areas (8a, 8b) and a first nano-object (50) connected to the conducting areas, the first chip being assembled on a support (70) such that the first nano-object is arranged facing an upper face of the support, the device being further provided with first connection elements (80a, 80b) capable of being connected to the external electrical system and arranged on and in contact with the first conducting areas (8a, 8b), the first connection elements being formed on the side of the upper face of the support (70) and being accessible from the side of the upper face of the support.Type: GrantFiled: October 3, 2016Date of Patent: December 8, 2020Assignee: Commissariat A L'Energie Atomique et aux Energies AlternativesInventors: Aurelie Thuaire, Patrick Reynaud, Patrick Leduc, Emmanuel Rolland
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Patent number: 10813227Abstract: In a component press-bonding device that performs work related to component mounting on a board after a mark provided on a transparent end region of the board is recognized, an imaging camera provided with an imaging optical axis extending downwards, a light emitter that irradiates the end region with illumination light from above the board in a state where the mark is positioned within an imaging visual field of the imaging camera, and a light reflecting member that is provided below the imaging camera and reflects the illumination light, which is emitted by the light emitter and is transmitted downwards through the end region, back to the end region are included. The imaging camera images the mark under the illumination light, which is reflected by the light reflecting member and is transmitted upwards through the end region.Type: GrantFiled: October 17, 2017Date of Patent: October 20, 2020Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Toshihiko Tsujikawa, Akira Kameda
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Patent number: 10756023Abstract: A semiconductor package includes a connection member and a supporting member. The connection member has first and second surfaces opposing each other and a redistribution layer. The supporting member is disposed on the first surface of the connection member, has a first through-hole and a second through-hole spaced apart from each other, and has a blocking layer disposed on at least an inner surface of the second through-hole. A semiconductor chip is disposed in the first through-hole and has connection pads connected to the redistribution layer. At least one passive component is disposed in the second through-hole and has connection terminals connected to the redistribution layer. An encapsulant encapsulates the semiconductor chip and the at least one passive component in the first and second through-holes, respectively. An electromagnetic band-gap (EBG) structure is embedded in the supporting member.Type: GrantFiled: February 26, 2018Date of Patent: August 25, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Han Kim, Hyung Joon Kim
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Patent number: 10734170Abstract: A resin structure includes a molded resin element and a push-type switch. The push-type switch includes a receptacle whereon a first terminal and a second terminal are secured, the first terminal and the second terminal configured to connect to an electrical circuit; a button unit protruding from the receptacle; and a contact spring unit configured to move with the button unit, to electrically connect between the first terminal and the second terminal, and to generate an opposing force relative to a pressure applied between the receptacle and the button unit. The receptacle stores the button unit and the contact spring unit. The receptacle of the push-type switch is embedded in the molded resin element with the button unit exposed from the molded resin element.Type: GrantFiled: September 19, 2017Date of Patent: August 4, 2020Assignee: OMRON CorporationInventor: Wakahiro Kawai
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Patent number: 10641820Abstract: Apparatus and methods for detecting and identifying a cause of a hot-switching event in an automated test system. One or more antennae positioned near mechanical relays in the system may be used to sense electromagnetic radiation. The antennae may be configured to respond to electromagnetic radiation of the type generated during a hot-switching event. Signals measured by the antennae may be processed to determine whether the signals have characteristics of hot-switching events. Processing may entail generating a signal envelope and determining whether the envelope has characteristics indicative of a hot-switching event. When a hot-switching event is detected, information to correlate the event to other events in the test system may also be captured. That information may be time information, enabling program test-system program instructions executing at the time of the event to be identified, such that the test system may be reprogrammed to avoid hot-switching events.Type: GrantFiled: October 19, 2018Date of Patent: May 5, 2020Assignee: Teradyne, Inc.Inventors: Alan B. Hussey, Richard John Burns, Gregory Smith, Mark Alan Levin
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Patent number: 10629476Abstract: A package includes a device die, a molding material molding the device die therein, a through-via substantially penetrating through the molding material, wherein the through-via has an end. The end of the through-via is tapered and has rounded sidewall surfaces. The package further includes a redistribution line electrically coupled to the through-via.Type: GrantFiled: July 16, 2018Date of Patent: April 21, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Hsien-Wei Chen
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Patent number: 10593568Abstract: Semiconductor devices having a semiconductor die electrically coupled to a redistribution structure and a molded material over the redistribution structure are disclosed herein, along with associated systems and methods. In one embodiment, a semiconductor device includes a semiconductor die attached to a first side of a substrate-free redistribution structure, and a plurality of conductive columns extending through a molded material disposed on the first side of the redistribution structure. The semiconductor device can also include a second redistribution structure on the molded material and electrically coupled to the conductive columns. A semiconductor device can be manufactured using a single carrier and requiring processing on only a single side of the semiconductor device.Type: GrantFiled: September 6, 2018Date of Patent: March 17, 2020Assignee: Micron Technology, Inc.Inventors: Chan H. Yoo, John F. Kaeding, Ashok Pachamuthu, Mark E. Tuttle
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Patent number: 10580738Abstract: Direct bonding heterogeneous integration packaging structures and processes include a packaging substrate with first and second opposing surfaces. A trench or a pedestal is provided in the first surface. A bridge is disposed in the trench or is adjacent the pedestal sidewall, wherein the bridge includes an upper surface coplanar with the first surface of the package substrate. At least two chips in a side by side proximal arrangement overly the bridge and the packaging substrate, wherein the bridge underlies peripheral edges of the at least two chips in the side by side proximal arrangement. The at least two chips include a plurality of electric connections that are directly coupled to corresponding electrical connections on the bridge and on the packaging substrate.Type: GrantFiled: March 20, 2018Date of Patent: March 3, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kamal K. Sikka, Jon A. Casey, Joshua Rubin, Arvind Kumar, Dinesh Gupta, Charles L. Arvin, Mark W. Kapfhammer, Steve Ostrander, Maryse Cournoyer, Valérie A. Oberson, Lawrence A. Clevenger
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Patent number: 10559905Abstract: Implementations of pins for semiconductor packages may include: an upper contact portion having a contact surface configured to mechanically and electrically couple with a pin receiver; a lower portion having a vertical stop and at least two curved legs; a horizontal base coupled directly to the at least two curved legs and configured to be soldered to a substrate to mechanically and electrically couple the pin to the substrate, the horizontal base having an upper contact surface, and; a gap between a bottom contact surface of the vertical stop and the upper contact surface of the horizontal base; wherein the at least two curved legs are configured to flex to allow the bottom contact surface of the vertical stop to move toward the upper contact surface of the horizontal base in response to a pressure applied to the pin along a direction collinear with a longest length of the pin toward the upper contact surface, and; wherein the vertical stop is configured to stop movement of the pin when the bottom contact sType: GrantFiled: January 16, 2019Date of Patent: February 11, 2020Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Yushuang Yao, Chee Hiong Chew, Atapol Prajuckamol
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Patent number: 10551697Abstract: An electrooptic display device includes a TFT substrate, a touch panel superimposed and placed on the TFT substrate, a circuit board spaced apart from the TFT substrate and the touch panel, one side of the circuit board facing the TFT substrate and the touch panel, a plurality of first FPCs each including one end electrically connected to one side of the TFT substrate, and the other end electrically connected to one side of the circuit board, and a second FPC that is electrically connected to the touch panel and extends in parallel to the first FPCs. The circuit board includes a cutout in a portion overlapping the second FPC on one side of the circuit board.Type: GrantFiled: September 29, 2017Date of Patent: February 4, 2020Assignee: Mitsubishi Electric CorporationInventor: Takahiro Ueno