Capacitor And Electrical Component Patents (Class 361/763)
  • Patent number: 10431537
    Abstract: A package assembly includes a substrate and at least a first die having a first contact array and a second contact array. First and second via assemblies are respectively coupled with the first and second contact arrays. Each of the first and second via assemblies includes a base pad, a cap assembly, and a via therebetween. One or more of the cap assembly or the via includes an electromigration resistant material to isolate each of the base pad and the cap assembly. Each first cap assembly and via of the first via assemblies has a first assembly profile less than a second assembly profile of each second cap assembly and via of the second via assemblies. The first and second cap assemblies have a common applied thickness in an application configuration. The first and second cap assemblies have a thickness variation of ten microns or less in a reflowed configuration.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: October 1, 2019
    Assignee: Intel Corporation
    Inventors: Srinivas Pietambaram, Jung Kyu Han, Ali Lehaf, Steve Cho, Thomas Heaton, Hiroki Tanaka, Kristof Darmawikarta, Robert Alan May, Sri Ranga Sai Boyapati
  • Patent number: 10396044
    Abstract: A semiconductor device includes a wiring substrate including a first surface and a second surface opposite to the first surface, a semiconductor chip including a plurality of chip electrodes and mounted over the wiring substrate, a first capacitor arranged at a position overlapping with the semiconductor chip in plan view and incorporated in the wiring substrate, and a second capacitor arranged between the first capacitor and a peripheral portion of the wiring substrate in plan view. Also, the second capacitor is inserted in series connection into a signal transmission path through which an electric signal is input to or output from the semiconductor chip.
    Type: Grant
    Filed: October 15, 2015
    Date of Patent: August 27, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kazuyuki Nakagawa, Keita Tsuchiya, Yoshiaki Sato, Shinji Baba
  • Patent number: 10306764
    Abstract: The invention relates to a variable sensor interface for a control unit, this variable sensor interface including a circuit board which is provided with components. In a sensor interface which can easily be used for the use of different sensor types, the circuit board has a predefined conductive track layout having a plurality of predefined mounting locations, the mounting locations being provided with components in a sensor-specific manner.
    Type: Grant
    Filed: March 20, 2015
    Date of Patent: May 28, 2019
    Assignee: SCHAEFFLER TECHNOLOGIES AG & CO. KG
    Inventors: Daniel Ritter, Steffen Linz, Thomas Wacker
  • Patent number: 10264680
    Abstract: There is provided a multilayer ceramic electronic component embedded in a board including: a ceramic body including dielectric layers; first and second internal electrodes; and first and second external electrodes formed on first and second side surfaces of the ceramic body, respectively, wherein the first external electrode includes a first electrode layer and a first metal layer formed on the first electrode layer, the second external electrode includes a second electrode layer and a second metal layer formed on the second electrode layer, the first and second external electrodes are formed to be extended to first main surface of the ceramic body, and when a maximum width and a minimum width of at least one of the first and second external electrodes formed on the first main surface are defined as BWmax and BWmin, respectively, 0?BWmax?BWmin?100 ?m is satisfied.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: April 16, 2019
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jin Woo Lee, Jin Man Jung
  • Patent number: 10264681
    Abstract: A substrate includes a core substrate; a cavity formed on an upper surface side of the core substrate; a bottom plate of the cavity formed integrally with the core substrate; a through-hole formed in the bottom plate, a component mounting portion formed at a portion of the bottom plate, an electronic component mounted on the component mounting portion so as to be disposed inside the cavity; a first insulating layer formed on an upper surface of the core substrate so as to cover an upper surface of the electronic component; and a second insulating layer formed on a lower surface of the core substrate so as to fill the through-hole and cover a lower surface of the electronic component. The cavity is filled with the first insulating layer and the second insulating layer. The first insulating layer and the second insulating layer are formed of the same insulating resin.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: April 16, 2019
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Kenji Kawai
  • Patent number: 10231336
    Abstract: A printed wiring board includes a first conductor layer forming an inner conductor layer, a second conductor layer forming a first outemiost conductor layer, a third conductor layer forming a second outermost conductor layer, insulating layers including first and second insulating layers, first via conductors connecting the first and second conductor layers, and second via conductors connecting the first and third conductor layers. The first conductor layer has thickness greater than thicknesses of the second and third conductor layers, the second conductor layer includes component mounting pads positioned to mount an electronic component on the second conductor layer and extending outside component mounting region corresponding to projection region of the component, and the first via conductors include a first set of the first via conductors formed directly underneath the component mounting region and a second set of the first via conductors formed on outer side of the component mounting region.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: March 12, 2019
    Assignee: IBIDEN CO., LTD.
    Inventors: Toshiki Furutani, Takema Adachi, Toshihide Makino, Hidetoshi Noguchi
  • Patent number: 10229915
    Abstract: A semiconductor structure and a method for fabricating the same. The semiconductor structure includes a substrate and a bonding layer in contact with a top surface of the substrate. At least one transistor contacts the bonding layer. The transistor includes at least one gate structure disposed on and in contact with a bottom surface of a semiconductor layer of the transistor. The semiconductor further includes a capacitor disposed adjacent to the transistor. The capacitor contacts the semiconductor layer of the transistor and extends down into the substrate. The method includes forming at least one transistor and then flipping the transistor. After the transistor has been flipped, the transistor is bonded to a new substrate. An initial substrate of the transistor is removed to expose a semiconductor layer. A capacitor is formed adjacent to the transistor and contacts with the semiconductor layer. A contact node is formed adjacent to the capacitor.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: March 12, 2019
    Assignee: International Business Machines Corporation
    Inventors: Terence B. Hook, Joshua M. Rubin, Tenko Yamashita
  • Patent number: 10217695
    Abstract: An electronic device comprising a semiconductor package having a first main surface region and a second main surface region and comprising a semiconductor chip comprising at least one chip pad in the second main surface region and a connector block comprising at least one first electrically conductive through connection and at least one second electrically conductive through connection extending with different cross-sectional areas between the first main surface region and the second main surface region and being arranged side-by-side with the semiconductor chip.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: February 26, 2019
    Assignee: Infineon Technologies AG
    Inventors: Thorsten Meyer, Klaus Pressel, Maciej Wojnowski
  • Patent number: 10143085
    Abstract: A multilayer electronic component includes a first multilayer capacitor electrically connected to a first surface of a support plate formed of an insulating material; and first and second metal frames electrically connected to first and second ends of the support plate, respectively. The first and second metal frames extend in an amount greater than a thickness of the first multilayer capacitor so that a first end of the first and second metal frames constitutes a mounting part.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: November 27, 2018
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Heung Kil Park, Jong Hwan Park, Young Ghyu Ahn
  • Patent number: 10141394
    Abstract: The disclosed technology relates to a metal-insulator-metal capacitor (MIMCAP) integrated as part of a back-end-of-line of an integrated circuit (IC). In one aspect, a MIMCAP comprises a first planar electrode having perforations formed therethrough, and a metal-insulator-metal (MIM) stack lining inner surfaces of cavities formed in the perforations and extending into the substrate. The MIMCAP additionally comprises a second electrode having a planar portion and metal extensions extending from the planar portion into the cavities. The first electrode and the planar portion of the second electrode are formed of or comprise planar metal areas of the respective metallization levels, which can be formed by a damascene process, which allows for a reduction of the series resistance. A low aspect ratio can be obtained using one electrode having a 3D-structure (the electrode having extensions extending into the cavities).
    Type: Grant
    Filed: November 23, 2016
    Date of Patent: November 27, 2018
    Assignee: IMEC vzw
    Inventor: Mikael Detalle
  • Patent number: 10103132
    Abstract: A semiconductor device and method of manufacture is provided. A reflowable material is placed in electrical connection with a through via, wherein the through via extends through an encapsulant. A protective layer is formed over the reflowable material. In an embodiment an opening is formed within the protective layer to expose the reflowable material. In another embodiment the protective layer is formed such that the reflowable material is extending away from the protective layer.
    Type: Grant
    Filed: February 15, 2017
    Date of Patent: October 16, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Po-Hao Tsai, Li-Hui Cheng
  • Patent number: 10080295
    Abstract: Provided are a circuit board structure and a fabrication method thereof, including the steps of: forming a first circuit layer in a first dielectric layer and exposing the first circuit layer therefrom; forming a second dielectric layer on the first dielectric layer and the first circuit layer, and forming a second circuit layer on the second dielectric layer; forming a plurality of first conductive vias in the second dielectric layer for electrically connecting to the first circuit layer to thereby dispense with a core board and electroplated holes and thus facilitate miniaturization. Further, the first dielectric layer is liquid before being hardened and is formed on the first dielectric layer that enhances the bonding between layers of the circuit board and the structure.
    Type: Grant
    Filed: November 2, 2012
    Date of Patent: September 18, 2018
    Assignee: Unimicron Technology Corp.
    Inventor: Kun-Chen Tsai
  • Patent number: 10074615
    Abstract: A package structure including at least one conductive plate, a redistribution layer, a first semiconductor chip, a conductive shielding structure and an insulating encapsulant is provided. The first semiconductor chip is sandwiched in between the at least one conductive plate and the redistribution layer, wherein the first semiconductor chip is disposed on the at least one conductive plate and electrically connected to the redistribution layer. The conductive shielding structure is sandwiched in between the at least one conductive plate and the redistribution layer, wherein the conductive shielding structure surrounds the first semiconductor chip and electrically connects the at least one conductive plate with the redistribution layer. The insulating encapsulant is disposed on the redistribution layer, encapsulating the first semiconductor chip, the conductive shielding structure, and surrounding the at least one conductive plate.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: September 11, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ying-Cheng Tseng, Chih-Hua Chen, Hsiu-Jen Lin, Hao-Yi Tsai, Kuo-Chung Yee, Chia-Hung Liu
  • Patent number: 9991193
    Abstract: A semiconductor device package includes a first conductive base, a first semiconductor die, a dielectric layer, a first patterned conductive layer, and a second patterned conductive layer. The first conductive base defines a first cavity. The first semiconductor die is on a bottom surface of the first cavity. The dielectric layer covers the first semiconductor die, the first surface and the second surface of the first conductive base and fills the first cavity. The first patterned conductive layer is on a first surface of the dielectric layer. The second patterned conductive layer is on a second surface of the dielectric layer.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: June 5, 2018
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Kay Stefan Essig, Chi-Tsung Chiu, Hui Hua Lee
  • Patent number: 9872410
    Abstract: An inductor includes a first core, a conducting wire, a second core and a first lead frame. There is an accommodating space formed on a first side of the first core and there is a recess portion formed on a second side of the first core, wherein the first side is opposite to the second side. The first core has a first height. The conducting wire is disposed in the accommodating space. The second core is disposed on the first side of the first core and covers the accommodating space. The first lead frame has an embedded portion embedded in the recess portion. The embedded portion has a second height. After embedding the embedded portion in the recess portion of the first core, a total height of the embedded portion and the first core is smaller than the sum of the first height and the second height.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: January 16, 2018
    Assignee: CYNTEC CO., LTD.
    Inventor: Tsung-Chan Wu
  • Patent number: 9837343
    Abstract: A chip embedded substrate includes: an insulating layer having outer layer circuit patterns provided on any one of an upper surface and a lower surface thereof; a chip embedded in the insulating layer; and internal circuit patterns included in the insulating layer and disposed between a height of a top surface of the chip and a height of a bottom surface thereof.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: December 5, 2017
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Joon Sung Kim, Yong Ho Baek, Jung Hyun Cho, Eung Suek Lee, Jae Hoon Choi, Young Gwan Ko
  • Patent number: 9825388
    Abstract: A layout method applied to a connector is provided. The connector is electrically connected between a flexible printed circuit (FPC) and a printed circuit board (PCB). The FPC includes M pairs of differential lines and X shield lines. The PCB includes M pairs of differential lines and Z shield lines. The layout method includes following steps. Firstly, M pairs of conductive lines are disposed on the connector. The M conductive lines are correspondingly electrically connected to the M differential lines of the FPC and the M differential lines of the PCB. Then; Y conductive lines are disposed on the connector, wherein Y is smaller than X. Furthermore, at least one of the Y conductive lines is electrically connected to at least one of the X shield lines and at least one of the Z shield lines.
    Type: Grant
    Filed: August 12, 2014
    Date of Patent: November 21, 2017
    Assignee: NOVATEK MICROELECTRONICS CORP.
    Inventors: Chun-Yi Chou, Yu-Chang Pai, Teng-Yang Tan, Shih-Wei Tseng
  • Patent number: 9824902
    Abstract: An integrated fan-out package including a chip module, a second integrated circuit, a second insulating encapsulation, and a redistribution circuit structure is provided. The chip module includes a first insulating encapsulation and a first integrated circuit embedded in the first insulating encapsulation, and the first integrated circuit includes a first surface and first conductive terminals on the first surface. The second integrated circuit includes a second surface and second conductive terminals on the second surface. The chip module and the second integrated circuit are embedded in the second insulating encapsulation. The first and second conductive terminals are accessibly exposed from the first and second insulating encapsulation. The redistribution circuit structure covers the first surface, the second surfaces, the first insulating encapsulation, and the second insulating encapsulation. The redistribution circuit structure is electrically connected to the first and second conductive terminals.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: November 21, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hao-Cheng Hou, Chien-Hsun Lee, Chen-Hua Yu, Chung-Shi Liu, Jung-Wei Cheng, Ping-Kang Huang, Sao-Ling Chiu, Tsung-Ding Wang
  • Patent number: 9722302
    Abstract: The present invention discloses a planar antenna microwave module, including an oscillation circuit board and a planar antenna board. The oscillation circuit board is a double-sided printed circuit board. The planar antenna board is a double-sided PCB independent of the oscillation circuit board. PCB copper foil of the planar antenna board forms a transmitting/receiving planar antenna. The planar antenna is laminated on a bottom surface of the oscillation circuit board by using a solder joint that runs through and electrically connects two layers of PCB copper foil, and is electrically connected to the oscillation circuit board through the solder joint. The antenna boards in the present invention are of independent and separate structures, and have a small design size, a simple manufacturing process, a short production cycle, low costs, and high economic benefits.
    Type: Grant
    Filed: May 5, 2015
    Date of Patent: August 1, 2017
    Assignee: HYTRONIK ELECTRONICS CO., LTD
    Inventor: Yabing Cheng
  • Patent number: 9530761
    Abstract: A package system includes at least one active circuitry disposed over a substrate. A passivation structure is disposed over the at least one active circuitry. The passivation structure has at least one opening that is configured to expose at least one first electrical pad. At least one passive electrical component is disposed over the passivation structure. The at least one passive electrical component is electrically coupled with the at least one first electrical pad.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: December 27, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Alan Roth, Eric Soenen, Chaohao Wang
  • Patent number: 9449947
    Abstract: A first package is bonded to a first substrate with first external connections and second external connections. The second external connections are formed using materials that are different than the first external connections in order to provide a thermal pathway from the first package. In a particular embodiment the first external connections are solder balls and the second external connections are copper blocks.
    Type: Grant
    Filed: July 1, 2014
    Date of Patent: September 20, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Shin-Puu Jeng, Der-Chyang Yeh, Hsien-Wei Chen, Cheng-Chieh Hsieh, Ming-Yen Chiu
  • Patent number: 9431327
    Abstract: A semiconductor device includes a lead frame, a first semiconductor component, a second semiconductor component, and a first conductive member. The lead frame includes a first segment having a first bottom plate, and a second segment having a second bottom plate. The first segment and the second segment are arranged side by side, the first bottom plate is spatially isolated from the second bottom plate, and the first bottom plate is thicker than the second bottom plate. The first semiconductor component is disposed on the first bottom plate, and the second semiconductor component is disposed on the second bottom plate. The second semiconductor component is thicker than the first semiconductor component. The first conductive member electrically connects the second semiconductor component to the first segment.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: August 30, 2016
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Hsin-Chang Tsai, Chia-Yen Lee, Peng-Hsin Lee
  • Patent number: 9426891
    Abstract: The present disclosure relates to a semiconductor device substrate and a method for making the same. The semiconductor device substrate includes a first dielectric layer, a second dielectric layer and an electronic component. The first dielectric layer includes a body portion, and a wall portion protruded from a first surface of the body portion. The wall portion has an end. The second dielectric layer has a first surface and an opposing second surface. The first surface of the second dielectric layer is adjacent to the first surface of the body portion. The second dielectric layer surrounds the wall portion. The end of the wall portion extends beyond the second surface of the second dielectric layer. The electronic component includes a first electrical contact and a second electrical contact. At least a part of the electronic component is surrounded by the wall portion.
    Type: Grant
    Filed: November 21, 2014
    Date of Patent: August 23, 2016
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Li-Chuan Tsai, Chih-Cheng Lee
  • Patent number: 9425121
    Abstract: A bottom package includes a molding compound, a buffer layer over and contacting the molding compound, and a through-via penetrating through the molding compound. A device die is molded in the molding compound. A guiding trench extends from a top surface of the buffer layer into the buffer layer, wherein the guiding trench is misaligned with the device die.
    Type: Grant
    Filed: September 11, 2013
    Date of Patent: August 23, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Hao Tsai, Feng-Cheng Hsu, Li-Hui Cheng, Jui-Pin Hung, Jing-Cheng Lin
  • Patent number: 9385075
    Abstract: A device includes a semiconductor material having a first main surface, an opposite surface opposite to the first main surface and a side surface extending from the first main surface to the opposite surface. The device further includes a first electrical contact element arranged on the first main surface of the semiconductor material and a glass material. The glass material includes a second main surface wherein the glass material contacts the side surface of the semiconductor material and wherein the first main surface of the semiconductor material and the second main surface of the glass material are arranged in a common plane.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: July 5, 2016
    Assignee: Infineon Technologies AG
    Inventors: Alexander Breymesser, Andre Brockmeier, Franz Dielacher, Francisco Javier Santos Rodriguez
  • Patent number: 9349708
    Abstract: A chip stacked package structure includes a first chip and a second chip, where the second chip is stacked with the first chip and the second chip includes a package layer and a first routing layer, where the package layer includes at least two dies and an attaching part configured to attach the at least two dies, where the attaching part is provided with multiple vias, with a part of vias in the multiple vias disposed at an outer periphery of the at least two dies, and the other part of vias in the multiple vias disposed between the at least two dies, and the first routing layer electrically connects the at least two dies; where the package layer is located between the first routing layer and the first chip, an electrically conductive material is provided in the multiple vias.
    Type: Grant
    Filed: June 3, 2015
    Date of Patent: May 24, 2016
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Huili Fu, Xiaodong Zhang
  • Patent number: 9337182
    Abstract: The present disclosure is directed to an apparatus and method for manufacture thereof. The apparatus includes a first passive substrate bonded to a second active substrate by a conductive metal interface. The conductive metal interface allows for integration of different function devices at a wafer level.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: May 10, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuei-Sung Chang, Chun-Wen Cheng, Alex Kalnitsky, Chia-Hua Chu
  • Patent number: 9247646
    Abstract: An electronic component built-in substrate comprises a substrate having a core member with an opening in which an electronic component is disposed, a first auxiliary insulating layer formed on a first surface of the core member; a second auxiliary insulating layer formed on a second surface of the core member, the second auxiliary insulating layer having a first via hole, a filling resin portion filling a gap between the electronic component and a side surface of the opening of the core member, and a first wiring layer formed on the second auxiliary insulating layer and connected to the connection terminal of the electronic component through the first via hole. The whole of the first surface and the whole of the second surface of the core member are in direct contact with the first auxiliary insulating layer and the second auxiliary insulating layer, respectively.
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: January 26, 2016
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Junji Sato, Tomohiro Nomura, Kazuhiro Oshima
  • Patent number: 9231547
    Abstract: The present invention discloses a filter for removing noise, which includes: a lower magnetic body; an insulating layer disposed on the lower magnetic body and including at least one conductor pattern; input and output stud terminals electrically connected to the conductor pattern for electrical input and output of the conductor pattern; and an upper magnetic body consisting of an inner upper magnetic body including ferrite powder with a size corresponding to the interval between the input and output stud terminals and an outer upper magnetic body including ferrite powder with a size corresponding to the interval between the input and output stud terminals and an outer surface of the lower magnetic body. According to the present invention, it is possible to implement a coil part with high performance and characteristics by increasing permeability and improving impedance characteristics through simple structure and process.
    Type: Grant
    Filed: December 13, 2012
    Date of Patent: January 5, 2016
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Sang Moon Lee, Sung Kwon Wi, Jeong Bok Kwak, Won Chul Sim, Young Seuck Yoo, Yong Suk Kim
  • Patent number: 9196586
    Abstract: Embodiments of the present disclosure include semiconductor packages and methods of forming the same. An embodiment is a semiconductor package including a first package including one or more dies, and a package substrate bonded to a first side of the first package with by a first set of connectors. The semiconductor package further includes a surface mount device mounted to the first side of the first package, the surface mount device consisting essentially of one or more passive devices.
    Type: Grant
    Filed: February 13, 2014
    Date of Patent: November 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Ying-Ju Chen, Ming-Yen Chiu, Der-Chyang Yeh
  • Patent number: 9166298
    Abstract: According to one embodiment, a wireless device includes a circuit board, a semiconductor chip, a nonconductive layer, and a conductive film. The semiconductor chip includes a transmitting/receiving circuit and is mounted on the circuit board. The nonconductive layer is to seal the semiconductor chip. The conductive film is to cover a surface of the nonconductive layer, the conductive film being provided with a plurality of apertures serving as radiating elements. At least one aperture of the plurality of apertures is fed with power.
    Type: Grant
    Filed: July 11, 2013
    Date of Patent: October 20, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Koh Hashimoto, Yukako Tsutsumi, Takayoshi Ito, Koji Akita
  • Patent number: 9048222
    Abstract: An interconnect structure and a method of forming an interconnect structure are provided. The interconnect structure is formed over a carrier substrate, upon which a die may also be attached. Upon removal of the carrier substrate and singulation, a first package is formed. A second package may be attached to the first package, wherein the second package may be electrically coupled to through vias formed in the first package.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: June 2, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jui-Pin Hung, Jing-Cheng Lin, Po-Hao Tsai, Yi-Jou Lin, Shuo-Mao Chen, Chiung-Han Yeh, Der-Chyang Yeh
  • Patent number: 9042112
    Abstract: A converter power unit comprises: a heat sink; n power switch modules on the heat sink; a first group of laminated bus bars comprising a first and a second bus bar; a capacitor group comprising m capacitor; a second group of laminated bus bars comprising a third and a fourth bus bar, the first bus bar is connected with the third bus bar, the second bus bar is connected with the fourth bus bar; providing that vertical projection areas projected by an area occupied by the n power switch modules and projected by the capacitor group on a first plane perpendicular to an axial direction of the capacitor group are defined as a first and a second projection areas respectively, the first and the second projection area have an overlapped area. The present application can reduce the stray inductances in the commutating loop of the converter.
    Type: Grant
    Filed: November 20, 2012
    Date of Patent: May 26, 2015
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Wei Guan, Jian Jiang, Bagao Li, Kaitian Yan, Hongyang Wu
  • Patent number: 9035194
    Abstract: Embodiments of the present disclosure are directed towards a circuit board having integrated passive devices such as inductors, capacitors, resistors and associated techniques and configurations. In one embodiment, an apparatus includes a circuit board having a first surface and a second surface opposite to the first surface and a passive device integral to the circuit board, the passive device having an input terminal configured to couple with electrical power of a die, an output terminal electrically coupled with the input terminal, and electrical routing features disposed between the first surface and the second surface of the circuit board and coupled with the input terminal and the output terminal to route the electrical power between the input terminal and the output terminal, wherein the input terminal includes a surface configured to receive a solder ball connection of a package assembly including the die. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: October 30, 2012
    Date of Patent: May 19, 2015
    Assignee: Intel Corporation
    Inventors: M D Altaf Hossain, Jin Zhao, John T. Vu
  • Patent number: 9013893
    Abstract: An embedded capacitor module includes an electrode lead-out portion and at least one solid electrolytic capacitor portion adjacently disposed with the electrode lead-out portion. The electrode lead-out portion comprises a first substrate, a second substrate, a first insulating material disposed between the first substrate and the second substrate, a first porous layer formed on at least one surface of the first substrate, and a first oxide layer disposed on the first porous layer. The solid electrolytic capacitor portion comprises the first substrate, the second substrate, the first porous layer, the first oxide layer, all of which are extended from the electrode lead-out portion, a first conductive polymer layer disposed on the first oxide layer, a first carbon layer disposed on the first conductive polymer layer, and a first conductive adhesive layer disposed on the first carbon layer.
    Type: Grant
    Filed: May 17, 2013
    Date of Patent: April 21, 2015
    Assignee: Industrial Technology Research Institute
    Inventors: Chien-Min Hsu, Min-Lin Lee, Cheng-Liang Cheng, Li-Duan Tsai
  • Patent number: 9006585
    Abstract: There is provided a device (1) for surface mounting that has a substrate (10) and a capacitor element loaded on a loading-side surface of the substrate and is integrally molded including the substrate (10) and the capacitor element using a packaging resin. The substrate (10) includes a first terminal electrode (51) electrically connected to a first electrode of the capacitor element and a second terminal electrode (52) electrically connected to a second electrode of the capacitor element, at least part of a mounting-side surface (12) on an opposite side to the loading-side surface of the substrate (10) is exposed on a mounting surface (2) of the device (1), and the first terminal electrode (51) and the second terminal electrode (52) are adjacently disposed around an entire circumference of the mounting surface (2) of the device (1).
    Type: Grant
    Filed: July 21, 2014
    Date of Patent: April 14, 2015
    Assignees: Rubycon Corporation, Rubycon Carlit Co., Ltd., Carlit Holdings Co., Ltd.
    Inventors: Takuya Miyahara, Tetsuo Shiba
  • Patent number: 9001519
    Abstract: A protective circuit module and a battery pack having the same are disclosed. In one embodiment, the protective circuit module includes a printed circuit board, an electronic device mounted on a first surface of the printed circuit board, and a pattern part mounted on a second surface opposite to the first surface of the printed circuit board. The electronic device comprises an integrated circuit chip, and one or more electronic components electrically connected to the integrated circuit chip and at least one of the one or more electronic components is electrically connected to the pattern part.
    Type: Grant
    Filed: October 24, 2012
    Date of Patent: April 7, 2015
    Assignee: Samsung SDI Co., Ltd.
    Inventors: Kwangsig Jung, Doosun Hwang, Jaeseung Ryu
  • Patent number: 8995146
    Abstract: An electrical or electro-optical assembly comprising a substrate comprising an insulating material, at least one conductive track present on at least one surface of the substrate, at least one electrical or electro-optical component connected to at least one of the at least one conductive track, and a continuous coating comprising one or more plasma-polymerized polymers completely covering the at least one surface of the substrate, the at least one conductive track and the at least one electrical or electro-optical component.
    Type: Grant
    Filed: June 19, 2012
    Date of Patent: March 31, 2015
    Assignee: Semblant Limited
    Inventors: Andrew Simon Hall Brooks, Timothy Allan Von Werne
  • Patent number: 8971053
    Abstract: A wiring board includes a first substrate having a penetrating hole penetrating through the first substrate, a built-up layer formed on a surface of the first substrate and including interlayer resin insulation layers and wiring layers, the built-up layer having an opening portion communicated with the penetrating hole of the first substrate and opened to the outermost surface of the built-up layer, an interposer accommodated in the opening portion of the built-up layer and including a second substrate and a wiring layer formed on the second substrate, the wiring layer of the interposer including conductive circuits for being connected to semiconductor elements, a filler filling the opening portion such that the interposer is held in the opening portion of the built-up layer, and mounting pads formed on the first substrate and positioned to mount the semiconductor elements. The mounting pads are positioned to form a matrix on the first substrate.
    Type: Grant
    Filed: January 22, 2014
    Date of Patent: March 3, 2015
    Assignee: Ibiden Co., Ltd.
    Inventors: Takashi Kariya, Toshiki Furutani
  • Patent number: 8971054
    Abstract: A component assembly that can be easily built in a main substrate with high accuracy is formed such that a glass transition temperature of a built-in-component layer of an assembly substrate in which multiple capacitors are embedded is higher than a glass transition temperature of a built-in-component layer of a built-in-component substrate. Thus, thermal deformation of the component assembly is prevented when the built-in-component substrate in which the component assembly is built is heated during reflow, for example. The component assembly can thus be highly accurately built in the built-in-component substrate. Moreover, when the component assembly in which the multiple capacitors are embedded is built in the built-in-component substrate, electrode pads of the component assembly in which the multiple capacitors are embedded can be electrically connected to wiring layers of the built-in-component substrate by soldering despite the variation in height among the capacitors.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: March 3, 2015
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Masanori Fujidai, Kazuo Hattori, Isamu Fujimoto
  • Patent number: 8964409
    Abstract: An electronic module with EMI protection is disclosed. The electronic module comprises a component (1) with contact terminals (2) and conducting lines (4) in a first wiring layer (3). There is also a dielectric (5) between the component (1) and the first wiring layer (3) such that the component (1) is embedded in the dielectric (5). Contact elements (6) provide electrical connection between at least some of the contact terminals (2) and at least some of the conducting lines (4). The electronic module also comprises a second wiring layer (7) inside the dielectric (5). The second wiring layer (7) comprises a conducting pattern (8) that is at least partly located between the component (1) and the first wiring layer (3) and provides EMI protection between the component (1) and the conducting lines (4).
    Type: Grant
    Filed: February 5, 2010
    Date of Patent: February 24, 2015
    Assignee: GE Embedded Electronics Oy
    Inventor: Risto Tuominen
  • Patent number: 8963322
    Abstract: An electric power conversion apparatus includes a stacked body, a capacitor, a metal frame and a case. The stacked body is formed by stacking semiconductor modules with coolant passages formed therebetween. The frame has both the stacked body and the capacitor fixed therein. The case has all of the stacked body, the capacitor and the frame received therein. Further, the frame has a separation wall that separates the stacked body and the capacitor from each other, a stacked body-surrounding wall that surrounds the stacked body with the help of the separation wall, and a capacitor-surrounding that surrounds the capacitor with the help of the separation wall. The capacitor has a pair of end portions that are opposite to each other in a predetermined direction, in which control terminals of the semiconductor modules of the stacked body protrude, and each at least partially exposed from the capacitor-surrounding wall of the frame.
    Type: Grant
    Filed: March 25, 2014
    Date of Patent: February 24, 2015
    Assignee: Denso Corporation
    Inventors: Yuuya Kiuchi, Akira Nakasaka
  • Patent number: 8953331
    Abstract: A card key has a molded body and an upper and a lower housings. The molded body has a circuit board, to which electronic parts for communicating with an in-vehicle equipment are mounted and which is covered with resin. The molded body is formed in a plate shape. The upper and the lower housings are fixed to each other so that the molded body is arranged between them. An external appearance of the card key is defined by the upper and the lower housings.
    Type: Grant
    Filed: August 1, 2012
    Date of Patent: February 10, 2015
    Assignee: Denso Corporation
    Inventors: Keiichi Sugimoto, Mitsuru Nakagawa
  • Patent number: 8952262
    Abstract: A component-incorporated wiring substrate is provided. Some embodiments include a plate-like component incorporated in a core substrate and a build-up layer having an insulation layer and a conductor layer disposed in alternating layers. The component has terminal electrodes formed at its opposite ends having a side surface and a main surface. An insulation layer disposed on the main surface of the component has via conductors formed therein which are connected to the side surfaces and the main surfaces of the respective terminal electrodes. The via conductors are tapered, such that their via diameter decreases in a direction toward the terminal electrode, and their via diameter at a position where they connect to the main surface is greater than a length of the main surface. Accordingly, the area of connection between the via conductors and the corresponding terminal electrodes is increased, improving connection reliability through enhancement of tolerance for positional deviation.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: February 10, 2015
    Assignee: NGK Spark Plug Co., Ltd.
    Inventors: Daisuke Yamashita, Kazunaga Higo, Tetsuji Tsukada
  • Patent number: 8947887
    Abstract: A package assembly comprises an electronic device; a package body; at least a first plurality of leads having a first geometrical shape and a second plurality of leads having a second geometrical shape, protruding from the package body; each of the first plurality of leads being located in corners of the package body; or the first and the second plurality of leads arranged in at least a first row and a second row located in parallel to the first row; each of the rows comprising at least two leads; the first row being transformable into the second row by mirroring the first row along a symmetry plane of the package body; each of the first plurality of leads having the first geometrical shape different from the second geometrical shape.
    Type: Grant
    Filed: February 23, 2009
    Date of Patent: February 3, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Robert Bauer, Thorsten Hauck
  • Patent number: 8943684
    Abstract: A method for manufacturing a Z-directed component for insertion into a mounting hole in a printed circuit board according to one example embodiment includes simultaneously extruding a plurality of materials in the cross-sectional shape of the Z-directed component to form an extruded object with the plurality of materials arranged relative to each other in their operative positions for the Z-directed component. The extrusion of a first portion of at least one of the materials in the extruded object is staggered relative to the extrusion of a second portion of the at least one of the materials in the extruded object. At least a segment of the extruded object is fired. The fired segment forms the Z-directed component insertable into a mounting hole in a printed circuit board.
    Type: Grant
    Filed: October 28, 2011
    Date of Patent: February 3, 2015
    Assignee: Lexmark International, Inc.
    Inventor: Keith Bryan Hardin
  • Patent number: 8941016
    Abstract: A laminated wiring board, includes: a first substrate in which a conductor circuit is formed on one surface of an insulating layer and an adhesive layer is formed on an other surface of the insulating layer, and conductors are formed in via holes that pass through the insulating layer and the adhesive layer so that the conductor circuit is partially exposed therefrom; an electronic component electrically connected to the conductor circuit by allowing electrodes of the electronic component to be connected to the conductors; an embedding member arranged around the electronic components so that the electronic component is embedded therein; and a second substrate having an adhesive layer laminated to face the adhesive layer of the first substrate and sandwich the electronic component and the embedding member, wherein each of the electrodes of the electronic component is continuous with the conductor circuit through two or more of the conductors.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: January 27, 2015
    Assignee: Fujikura Ltd.
    Inventor: Masahiro Okamoto
  • Patent number: 8941434
    Abstract: A system and method for reducing simultaneous switching output (SSO) noise. In one embodiment, power supply decoupling capacitances are distributed non-uniformly among a plurality of I/O circuits. Transitions between consecutive values on a data bus are either sent by the transmitter as requested at the input of the transmitter, or, in cases for which the noise of the requested transition is high, converted by an encoder to transitions having lower SSO noise. The converted transitions are decoded in a receiver, so that the data at the output of the receiver are the same as the data at the input to the transmitter.
    Type: Grant
    Filed: February 6, 2014
    Date of Patent: January 27, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventor: Minghui Han
  • Patent number: 8942004
    Abstract: Disclosed herein is a printed circuit board having electronic components embedded therein. The printed circuit board having electronic components embedded therein includes: a metal core layer connected to a ground terminal of an external power supply to be grounded and having a cavity or a groove part formed thereon; an electronic component accommodated in the cavity and having a plurality of terminals, a ground terminal included in the plurality of terminals being connected to the metal core layer; an internal insulating layer stacked on both sides of the metal core layer; and circuit patterns formed on an external surface of the internal insulating layer.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: January 27, 2015
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Suk Chang Hong, Bong Kyu Choi, Je Gwang Yoo, Sang Wuk Jun, Sang Kab Park, Jung Soo Byun
  • Patent number: 8942003
    Abstract: A multilayered printed wiring board includes a plurality of insulating layers; a plurality of wiring layers which are located between the corresponding adjacent insulating layers; and a plurality of interlayer connection conductors for electrically connecting the wiring layers through the insulating layers; wherein a cavity is formed through one or more of the insulating layers so as to insert a first electric/electronic component and an area for embedding a second electric/electronic component is defined for the insulating layers.
    Type: Grant
    Filed: February 14, 2013
    Date of Patent: January 27, 2015
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Takahiro Sahara, Atsushi Kobayashi, Kiyoshi Takeuchi, Masahiko Igaue