Capacitor And Electrical Component Patents (Class 361/763)
  • Patent number: 12004331
    Abstract: A low inductance power module with low power loop inductance and high-power density is provided. The power module may include a vertical power loop structure, a cooling layer, and a thermal dissipation structure. The vertical power loop structure may utilize a substrate bottom conduction layer for electrical conduction. The thermal dissipation structure may be disposed between the substrate bottom conduction layer and the cooling layer. The vertical power loop structure may include integrated decoupling capacitors. Alternatively, the structure may include no integrated decoupling capacitors. The vertical power loop structure may include one or more half-bridge structures connected in parallel, each with its own integrated decoupling capacitors. The vertical power loop structure reduces power loop inductance in the power module, and the thermal dissipation structure provides electrical insulation, mechanical support, and thermal conduction.
    Type: Grant
    Filed: August 3, 2023
    Date of Patent: June 4, 2024
    Assignee: Ohio State Innovation Foundation
    Inventors: Xintong Lyu, Jin Wang
  • Patent number: 11982693
    Abstract: Apparatuses and methods of the present disclosure integrate a non-intrusive current sensor in the form of a current mismatch sensor into a power module having paralleled semiconductor structures or components. The current mismatch can be detected by the current sensor by monitoring a magnetic flux density between the paralleled components or devices.
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: May 14, 2024
    Assignee: The University of North Carolina at Charlotte
    Inventors: Babak Parkhideh, Andreas Lauer
  • Patent number: 11876085
    Abstract: A package comprising a substrate and an integrated device coupled to the substrate. The substrate includes at least one dielectric layer, a plurality of interconnects comprising a first interconnect and a second interconnect, a capacitor located at least partially in the substrate, the capacitor comprising a first terminal and a second terminal, a first solder interconnect coupled to a first side surface of the first terminal and the first interconnect, and a second solder interconnect coupled to a second side surface of the second terminal and the second interconnect.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: January 16, 2024
    Assignee: QUALCOMM INCORPORATED
    Inventors: Abinash Roy, Lohith Kumar Vemula, Bharani Chava, Jonghae Kim
  • Patent number: 11632861
    Abstract: The invention, which relates to the technical field of circuit boards, specifically discloses a method for manufacturing an embedded circuit board, an embedded circuit board, and an application thereof. The method includes: providing a substrate, wherein an electronic component is embedded in the substrate, a pad is arranged on a side surface of the electronic component, and an end surface of the pad is flush with a same side surface of the substrate; forming a metallic layer on a side surface of the substrate adjacent to the pad by sputtering, evaporation, electroplating or chemical vapor deposition; and patterning the metallic layer to obtain a circuit board covered with the metallic layer on the pad, wherein the metallic layer on the pad protrudes beyond the same side surface of the substrate.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: April 18, 2023
    Assignee: SHENNAN CIRCUITS CO., LTD.
    Inventors: Lixiang Huang, Zedong Wang, Hua Miao
  • Patent number: 11546990
    Abstract: A component carrier with an electrically insulating layer structure has opposed main surfaces, a through-hole, and an electrically conductive bridge structure connecting opposing sidewalls delimiting the through-hole. The sidewalls have a first tapering portion extending from a first main surface and a second tapering portion extending from a second main surface. A first demarcation surface faces the first main surface and a second demarcation surface faces the second main surface. A central bridge plane extends parallel to the first main surface and the second main surface and is at a vertical center between a lowermost point of the first demarcation surface and an uppermost point of the second demarcation surface. A first intersection point is between the central bridge plane and one of the sidewalls delimiting the through hole. A length of a shortest distance from the first intersection point to the first demarcation surface is at least 8 ?m.
    Type: Grant
    Filed: January 23, 2020
    Date of Patent: January 3, 2023
    Assignee: AT&S Austria Technologie & Systemtechnik Aktiengesellschaft
    Inventor: Mikael Tuominen
  • Patent number: 11424621
    Abstract: In certain aspects, a device comprises a first processing unit; a first power distribution network coupled to the first processing unit; a first decoupling capacitor coupled to the first power distribution network; a second processing unit configured to be identical to the first processing unit; a second power distribution network coupled to the second processing unit; and a second decoupling capacitor coupled to the second power distribution network, wherein the second decoupling capacitor is configured to have different effect on the second power distribution network than the first decoupling capacitor on the first power distribution network.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: August 23, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Palkesh Jain, Rahul Gulati
  • Patent number: 11404388
    Abstract: A device that includes a substrate including a plurality of metal layers, and a plurality of dielectric layers. The device further includes a first passive component including a first terminal, a second terminal, and a first body, mounted to the substrate on one of the plurality of metal layers. The first terminal is coupled to a first ground signal and the second terminal is coupled to a second ground signal such that the first passive component is shorted. The first passive component may be an inductor, a capacitor or a resistor. The first passive component is operable as a heat sink, a heat shield, an electromagnetic shield, or as a tuning inductor.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: August 2, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Yu-Chun Liu, Peter Mark Davulis
  • Patent number: 11350529
    Abstract: A substrate structure and electronic device provide improved power integrity and simplified manufacturing. The substrate structure includes a first printed circuit board, having a first side and a second side opposing each other, and a plurality of passive components embedded in the first printed circuit board. The plurality of passive components includes a first group, including a plurality of first passive components disposed adjacent to each other, and a second group, including a plurality of second passive components disposed adjacent to each other. A smallest distance between the first and second groups is greater than at least one of a smallest distance between adjacent first passive components and a smallest distance between adjacent second passive components.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: May 31, 2022
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Seung Eun Lee, Yong Hoon Kim
  • Patent number: 11330712
    Abstract: An electronic circuit device according to the present invention includes a base substrate having a wiring layer, at least one first electronic circuit element having a first surface fixed to the base substrate and having a connection part on a second surface opposed to the first surface, a re-distribution layer including a photosensitive resin layer, the photosensitive resin layer enclosing the first electronic circuit element on the base substrate and embedding a first wiring photo via, a second wiring photo via, and a wiring, the first wiring photo via electrically connected to the connection part of the first electronic circuit element, the second wiring photo via arranged at the outer periphery of the first electronic circuit element and electrically connected to a connection part of the wiring layer, the wiring arranged on the second surface and electrically connected to the first wiring photo via and the second wiring photo via.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: May 10, 2022
    Assignee: RISING TECHNOLOGIES CO., LTD.
    Inventor: Shuzo Akejima
  • Patent number: 11317503
    Abstract: A circuit board is provided, including: a core board, defining a plurality of slots, the plurality of slots including a plurality of first sub-slots and a plurality of second sub-slots disposed beneath the first sub-slots. Each of the second sub-slots is located beneath a corresponding first sub-slot of the first sub-slots; and a plurality of chip assemblies, arranged in the slots and including a plurality of first chips located in the first sub-slots and a plurality of second chips located in the second sub-slots. Each of the first chips is connected in series with one of the second chips at a corresponding position to form a plurality of chipsets; the chipsets are connected in parallel with each other; an end of the chipsets is connected to a first power signal layer, and the other end of the plurality of chipsets is connected to a ground layer.
    Type: Grant
    Filed: December 27, 2020
    Date of Patent: April 26, 2022
    Assignee: SHENNAN CIRCUITS CO., LTD.
    Inventors: Lixiang Huang, Zedong Wang, Hua Miao
  • Patent number: 11316249
    Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a first substrate having a first surface and a second surface opposite to the first surface, an antenna module disposed on the first surface of the first substrate, an electronic component module disposed on the first surface of the first substrate, and a first package body encapsulating the antenna module and the electronic component module. The antenna module has a first surface facing the first surface of the first substrate, a second surface opposite to the first surface of the antenna module, and a lateral surface extending between the first surface of the antenna module and the second surface of the antenna module. The lateral surface of the antenna module faces the electronic component module. A method of manufacturing a semiconductor device package is also provided.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: April 26, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Hung-Hsiang Cheng
  • Patent number: 11309239
    Abstract: A package assembly includes a substrate and at least a first die having a first contact array and a second contact array. First and second via assemblies are respectively coupled with the first and second contact arrays. Each of the first and second via assemblies includes a base pad, a cap assembly, and a via therebetween. One or more of the cap assembly or the via includes an electromigration resistant material to isolate each of the base pad and the cap assembly. Each first cap assembly and via of the first via assemblies has a first assembly profile less than a second assembly profile of each second cap assembly and via of the second via assemblies. The first and second cap assemblies have a common applied thickness in an application configuration. The first and second cap assemblies have a thickness variation of ten microns or less in a reflowed configuration.
    Type: Grant
    Filed: October 20, 2020
    Date of Patent: April 19, 2022
    Assignee: Intel Corporation
    Inventors: Srinivas Pietambaram, Jung Kyu Han, Ali Lehaf, Steve Cho, Thomas Heaton, Hiroki Tanaka, Kristof Darmawikarta, Robert Alan May, Sri Ranga Sai Boyapati
  • Patent number: 11296613
    Abstract: The inductance of a noise filter circuit is reduced, and an output is increased, whereby positive and negative electrode power supply side conductors each include a first and second conductor portions having a side surface and a main surface having an area larger than an area of the side surface. The first conductor portions are arranged on one surface of a base portion with an insulating member interposed therebetween. The second conductor portions penetrate through a core member in a state in which the main surfaces face each other. A width of a portion of the first conductor portion which is in contact with the insulating member in a direction perpendicular to current flow direction is larger than a width of a portion of the second conductor portion which is disposed within the core member in the direction perpendicular to current flow direction.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: April 5, 2022
    Assignee: HITACHI AUTOMOTIVE SYSTEMS, LTD.
    Inventors: Youhei Nishizawa, Fusanori Nishikimi, Yusaku Katsube
  • Patent number: 11264360
    Abstract: Some embodiments include apparatus, systems, and methods having a base, a first die, a second arranged in a stacked with the first die and the base, and a structure located in the stack and outside at least one of the first and second dice and configured to transfer signals between the base and at least one of the first and second dice.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: March 1, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Brent Keeth, Mark Hiatt, Terry R. Lee, Mark Tuttle, Rahul Advani, John F. Schreck
  • Patent number: 11246244
    Abstract: A power electronics assembly comprises a heat sink, at least two half bridge modules mounted on one side of the heat sink, a circuit board mounted on the half bridge modules, and at least one capacitor mounted on the circuit boards, wherein each of the half bridge modules has a housing that has a cold side that is mounted on the heat sink, and the housing has a connection side from which numerous connection pins project for each DC connection in the half bridge module that are connected to the circuit board, and wherein conductors in the circuit board are designed to connect the half bridge modules in parallel and connect them to the at least one capacitor to form a DC link.
    Type: Grant
    Filed: February 5, 2019
    Date of Patent: February 8, 2022
    Assignee: ZF FRIEDRICHSHAFEN AG
    Inventors: Marco Denk, Johannes Hager, Michael Sperber
  • Patent number: 11239194
    Abstract: A chip package structure is provided. The chip package structure includes a first redistribution structure including a dielectric structure and wiring layers in the dielectric structure. The chip package structure includes a first chip over the first surface. The chip package structure includes a first conductive pillar over the first surface and electrically connected to the wiring layers. The chip package structure includes a second chip over the second surface. The second chip includes a second substrate and a second conductive pad over the second substrate, and the second conductive pad is between the second substrate and the first redistribution structure. The chip package structure includes a second conductive pillar over the second surface and electrically connected to the wiring layers.
    Type: Grant
    Filed: January 23, 2020
    Date of Patent: February 1, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Shin-Puu Jeng, Shuo-Mao Chen, Feng-Cheng Hsu
  • Patent number: 11229119
    Abstract: A printed circuit board includes a core layer having a first through-portion, a coil structure disposed in the first through-portion and comprising a support member, a first coil pattern in a planar spiral form disposed on one surface of the support member, and a body comprising a magnetic substance, wherein the support member and the first coil pattern are accommodated in the body, a first build-up layer covering at least a portion the core layer and disposed in at least a portion of the first through-portion, a first wiring layer disposed on one surface of the first build-up layer, and a first via layer passing through at least a portion of the first build-up layer and connected to the first wiring layer. The first via layer comprises a first wiring via connecting at least a portion of the first wiring layer to the first coil pattern.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: January 18, 2022
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Ki Jung Sung, Tae Seong Kim, Jae Woong Choi
  • Patent number: 11217542
    Abstract: A three-dimensional (3-D) module with integrated passive components includes a plurality of vertically stacked sub-modules. Each sub-module comprises a device level comprising a high-k dielectric (e.g. ceramic) material and an interconnect level comprising a low-k dielectric (e.g. organic) material. The passive components in the device level are fired integrally, whereas the device level and the interconnect level are fired independently.
    Type: Grant
    Filed: July 10, 2020
    Date of Patent: January 4, 2022
    Assignee: Southern University of Science and Technology
    Inventors: Guobiao Zhang, Hongyu Yu, Yuejin Guo, Shengming Zhou, Guoxing Zhang, Guangzhao Liu, Mingtao Hu, Wang Zhang
  • Patent number: 11211368
    Abstract: A semiconductor device includes a substrate having a main surface, a plurality of first wirings, each having a first embedded part embedded in the substrate and exposed from the main surface, and a mounted part which is in contact with the main surface and is connected to the first embedded part, a semiconductor element having an element rear surface and a plurality of electrodes bonded to the mounted parts, a plurality of second wirings, each having a second embedded part embedded in the substrate and exposed from the main surface and a columnar part protruding from the second embedded part in the thickness direction, and being located outward from the semiconductor element as viewed in the thickness direction; and a passive element located on the side facing the main surface in the thickness direction more than the semiconductor element, and electrically connected to the plurality of second wirings.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: December 28, 2021
    Assignee: ROHM CO., LTD.
    Inventors: Isamu Nishimura, Mamoru Yamagami
  • Patent number: 11165155
    Abstract: A film antenna according to an embodiment of the present invention includes a first electrode layer, a dielectric layer having a thickness in a range from 50 ?m to 1,000 ?m and having a dielectric constant in a range from 2 to 10 on the first electrode layer, and a second electrode layer on the dielectric layer. The dielectric constant and the thickness of the dielectric layer are controlled to improve high-frequency driving property of the film antenna.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: November 2, 2021
    Assignees: DONGWOO FINE-CHEM CO., LTD., POSTECH RESEARCH AND BUSINESS DEVELOPMENT FOUNDATION
    Inventors: Yoon Ho Huh, Jong Min Kim, Han Sub Ryu, Won Bin Hong
  • Patent number: 11152289
    Abstract: A semiconductor device comprises: a lead-frame comprising a die pad having at least one electrically conductive die pad area an insulating layer applied onto the electrically conductive die pad area. An electrically conductive layer is applied onto the insulating layer with one or more semiconductor dice coupled, for instance adhesively, to the electrically conductive layer. The electrically conductive die pad area, the electrically conductive layer and the insulating layer sandwiched therebetween form at least one capacitor integrated in the device. The electrically conductive die pad area comprises a sculptured structure with valleys and peaks therein; the electrically conductive layer comprises electrically conductive filling material extending into the valleys in the sculptured structure of the electrically conductive die pad area.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: October 19, 2021
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Fulvio Vittorio Fontana, Giovanni Graziosi, Michele Derai
  • Patent number: 11094660
    Abstract: A semiconductor package includes: a connection structure having first and second surfaces opposing each other and including a redistribution layer; a semiconductor chip disposed on the first surface of the connection structure and having connection pads connected to the redistribution layer; an encapsulant disposed on the first surface of the connection structure and encapsulating the semiconductor chip; a passivation layer disposed on the second surface of the connection structure and having a plurality of first and second openings exposing, respectively, first and second regions of the redistribution layer; and a plurality of underbump metal layers connected to the first region of the redistribution layer through the plurality of first openings, respectively.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: August 17, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung Soo Kim, Pyung Hwa Han, Sung Hawn Bae, Jin Won Lee
  • Patent number: 11088206
    Abstract: A non-volatile memory uses phase change memory (PCM) cells in a three dimensional vertical cross-point structure, in which multiple layers of word lines run in a horizontal direction and bit lines run in a vertical direction. The memory cells are located in a recessed region of the word lines and are separated from the bit line by an ovonic threshold switch. A surfactant lining of the word line recess in which the phase change memory material is placed improves stability of the resistance state of the memory cells, allowing for improved multi-state operation.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: August 10, 2021
    Assignee: SanDisk Tehnologies LLC
    Inventors: Federico Nardi, Christopher J Petti, Gerrit Jan Hemink
  • Patent number: 11089688
    Abstract: A sensor device includes a printed circuit board (PCB) substrate having a top surface, a bottom surface, a slot between the top and bottom surfaces, and two holes through the top surface and reaching into the slot. The sensor device further includes a sensor chip mounted on the top surface of the PCB substrate and above one of the two holes. The sensor device further includes a molding compound covering the sensor chip and sidewall surfaces and the top surface of the PCB substrate.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: August 10, 2021
    Assignee: TT ELECTRONICS PLC
    Inventors: Brent Hans Larson, Shivesh Langhanoja
  • Patent number: 11069665
    Abstract: Integrated passive devices (IPDs), electronic packaging structures, and methods of testing IPDs are described. In an embodiment, an electronic package structure includes an IPD with an array of capacitor banks that are electrically separate in the IPD, and a package routing that includes an interconnect electrically connected to an IC and a plurality of the capacitor banks in parallel.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: July 20, 2021
    Assignee: Apple Inc.
    Inventors: Vidhya Ramachandran, Chonghua Zhong, Jun Zhai, Long Huang, Mengzhi Pang, Rohan U. Mandrekar
  • Patent number: 11056436
    Abstract: A method of forming a package assembly includes forming a first dielectric layer over a carrier substrate; forming a conductive through-via over the first dielectric layer; treating the conductive through-via with a first chemical, thereby roughening surfaces of the conductive through-via; and molding a device die and the conductive through-via in a molding material.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: July 6, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih Ting Lin, Szu-Wei Lu, Jing-Cheng Lin, Chen-Hua Yu
  • Patent number: 11043441
    Abstract: A semiconductor package includes: a semiconductor chip having an active surface, having connection pads disposed thereon, and an inactive surface, opposing the active surface; an encapsulant covering the inactive surface of the semiconductor chip; a thermally conductive via penetrating through at least a portion of the encapsulant on the inactive surface of the semiconductor chip and physically spaced apart from the inactive surface of the semiconductor chip; and a connection structure disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: June 22, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Doo Hwan Lee, Tae Je Cho
  • Patent number: 10993328
    Abstract: A module-embedded multilayer circuit board includes an inner circuit board, component embedded module embedded in the through opening, a first outer circuit board, and a second outer circuit board. A through opening is defined in the inner circuit board. The component embedded module includes a top surface and side surfaces. The top surface has a length greater than that of the two side surfaces. Each component embedded module includes a component, upper circuit patterns formed on the top surface, and side circuit patterns formed on the side surface and exposed from the through opening. The first and the second outer circuit board are formed on the inner circuit board. One end of the side circuit patterns is electrically connected to the first and the second outer circuit board, the other end of the side circuit patterns is electrically connected to the component by the upper circuit patterns, respectively.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: April 27, 2021
    Assignees: HongQiSheng Precision Electronics (QinHuangDao) Co., Ltd., Avary Holding (Shenzhen) Co., Limited.
    Inventor: Chih-Chieh Fu
  • Patent number: 10925172
    Abstract: A carrier structure includes a carrier having at least one through hole penetrating the carrier and a build-up circuit layer located on the carrier and including at least one first circuit layer, at least one first dielectric layer, a second circuit layer, a second dielectric layer, and a plurality of conductive vias. The first circuit layer is located on a first surface of the carrier and includes at least one first pad disposed relative to the through hole. The first dielectric layer is located on the first circuit layer. The second circuit layer is located on the first dielectric layer and includes at least one second pad. The second dielectric layer is located on the second circuit layer and includes at least one opening exposing the second pad. The conductive vias penetrate the first dielectric layer and are electrically connected to the first and second circuit layers.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: February 16, 2021
    Assignee: Unimicron Technology Corp.
    Inventors: Tzyy-Jang Tseng, Cheng-Ta Ko, Pu-Ju Lin, Tse-Wei Wang
  • Patent number: 10916938
    Abstract: An ESD-protective surface-mount composite component that includes a surface-mount inductor and a thin-film component. The surface-mount inductor includes a body, a first outer conductor and a second outer conductor individually formed at both ends of the body in a first direction, and a third outer conductor formed at an intermediate position of the body in the first direction. The thin-film component includes a flat plate-like body, an ESD protection element formed inside the body, a first terminal conductor connected to the ESD protection element and formed on a front surface of the body, and a second terminal conductor connected to the ESD protection element and formed on the front surface of the body. The first terminal conductor is joined to the first outer conductor, and the second terminal conductor is joined to the third outer conductor.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: February 9, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Toshiyuki Nakaiso
  • Patent number: 10886246
    Abstract: A fan-out semiconductor package includes: a frame including first to third insulating layers, a first wiring layer disposed on a first surface of the first insulating layer and embedded in the second insulating layer, and a second wiring layer disposed on the third insulating layer, and having a through-hole penetrating through the first to third insulating layers; a semiconductor chip disposed in the through-hole and having an active surface on which connection pads are disposed and an inactive surface opposing the active surface; an encapsulant covering at least portions of each of the frame and the semiconductor chip and filling at least portions of the through-hole; and a connection structure disposed on the frame and the active surface of the semiconductor chip and including redistribution layers electrically connected to the connection pads. The first and second wiring layers are electrically connected to the connection pads.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: January 5, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Bong Soo Kim
  • Patent number: 10886219
    Abstract: An electronic component mounting package includes a semiconductor element which is disposed such that an active surface faces a main surface of a wiring portion, and which is electrically connected to the wiring portion via a first terminal; and a thin film passive element which is disposed between the active surface of the semiconductor element and the main surface of the wiring portion when seen in a lamination direction, and which is electrically connected to the semiconductor element. A part of the first terminal is disposed on an outer side with respect to the thin film passive element in a plan view. A length of the first terminal in the lamination direction disposed on the outer side with respect to the thin film passive element is larger than a thickness of the thin film passive element in the lamination direction.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: January 5, 2021
    Assignee: TDK CORPORATION
    Inventors: Kazuhiro Yoshikawa, Mitsuhiro Tomikawa, Kenichi Yoshida
  • Patent number: 10879220
    Abstract: A package-on-package structure including a first and second package is provided. The first package includes a first semiconductor die, a plurality of conductive pins, an insulating encapsulant, a backside connection structure and a redistribution layer. The conductive pins are surrounding the first semiconductor die and have a base portion with a first width and a body portion with a second width, the base portion is connected to the body portion and the first width being larger than the second width. The insulating encapsulant is encapsulating the first semiconductor die and the conductive pins. The backside connection structure is disposed on the first semiconductor die and electrically connected to the conductive pins. The redistribution layer is disposed on the first semiconductor die, and electrically connected to the first semiconductor die and the conductive pins. The second package is stacked on the first package and electrically connected to the backside connection structure.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Kuo-Chung Yee, Chun-Hui Yu
  • Patent number: 10863627
    Abstract: An electronic component-embedded substrate of the present disclosure includes a core structure including an insulating layer, a first wiring layer disposed on an upper surface of the insulating layer and a through-portion passing through the insulating layer; a first electronic component disposed in the through-portion and including a connection electrode; an insulator disposed in a portion of the through-portion between the core structure and a portion of the first electronic component; and a first metal layer disposed on an upper surface of the insulator. At least a portion of the first metal layer is included on the first wiring layer and physically in contact with at least a portion of the connection electrode.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: December 8, 2020
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Je Sang Park, Sang Ho Jeong, Chang Yul Oh
  • Patent number: 10854541
    Abstract: A package assembly includes a substrate and at least a first die having a first contact array and a second contact array. First and second via assemblies are respectively coupled with the first and second contact arrays. Each of the first and second via assemblies includes a base pad, a cap assembly, and a via therebetween. One or more of the cap assembly or the via includes an electromigration resistant material to isolate each of the base pad and the cap assembly. Each first cap assembly and via of the first via assemblies has a first assembly profile less than a second assembly profile of each second cap assembly and via of the second via assemblies. The first and second cap assemblies have a common applied thickness in an application configuration. The first and second cap assemblies have a thickness variation of ten microns or less in a reflowed configuration.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: December 1, 2020
    Assignee: Intel Corporation
    Inventors: Srinivas Pietambaram, Jung Kyu Han, Ali Lehaf, Steve Cho, Thomas Heaton, Hiroki Tanaka, Kristof Darmawikarta, Robert Alan May, Sri Ranga Sai Boyapati
  • Patent number: 10856411
    Abstract: A printed circuit board (PCB) includes a plurality of layers and electronic components connected to its top surface. The PCB also includes a plurality of trace layers, each located at a respective depth within the layers of the PCB. A plurality of vias provide signal pathways for the trace layer. Upon their manufacture, the vias include a stub portion not necessary for the signal pathways and causing degradation of the integrity of these signal pathways. Embodiments mill the bottom of the PCB to form a variable-depth cavity. The different milling depths of the variable-depth cavity are selected to remove the stub portions of the plurality of vias and the dielectric material between the stubs. By configuring the PCB power planes as the topmost trace layers, decoupling capacitors may be located at the greatest depth of the variable-depth cavity, thus reducing the loop inductance in the power circuit of the PCB.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: December 1, 2020
    Assignee: Dell Products, L.P.
    Inventors: Sandor Farkas, Bhyrav M. Mutnury, Steven Richard Ethridge
  • Patent number: 10818428
    Abstract: An inductor built-in substrate includes a core substrate having openings and first through holes, a magnetic resin filled in the openings and having second through holes, first through-hole conductors formed in the first through holes respectively such that each of the first through-hole conductors includes a metal film, second through-hole conductors formed in the second through holes respectively such that each of the second through-hole conductors includes a metal film, first through-hole lands formed on the core substrate such that each of the first through-hole lands includes a lowermost layer including a metal foil and that the first through-hole lands are connected to the first through-hole conductors respectively, and second through-hole lands formed on the magnetic resin such that each of the second through-hole lands includes a lowermost layer including a plating film and that the second through-hole lands are connected to the second through-hole conductors respectively.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: October 27, 2020
    Assignee: IBIDEN CO., LTD.
    Inventors: Hiroaki Kodama, Kazuro Nishiwaki, Kazuhiko Kuranobu, Hiroaki Uno
  • Patent number: 10779406
    Abstract: A wiring substrate includes a first insulating layer, an electronic component, a resin layer, a second insulating layer, a wiring pattern, and a via interconnect. The first insulating layer includes a cavity. The electronic component includes a first surface at which a pad is formed and a second surface facing away from the first surface and fixed in the cavity via an adhesive layer. The resin layer is on the first surface of the electronic component and covers the pad. The second insulating layer is on the first insulating layer and covers the resin layer. The wiring pattern is on the second insulating layer. The via interconnect pierces through the second insulating layer and the resin layer to electrically connect the wiring pattern to the pad.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: September 15, 2020
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Toru Hizume
  • Patent number: 10779414
    Abstract: A printed circuit board and method thereof include an electronic component embedded in an insulation layer and comprising a connection terminal exposed on a surface of the insulation layer. The printed circuit board and method thereof also include a bump formed on the connection terminal of the electronic component and exposed on the surface of the insulation layer.
    Type: Grant
    Filed: January 21, 2016
    Date of Patent: September 15, 2020
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Ho-Sik Park, Dong-Keun Lee, Jae-Hoon Choi, Sang-Jae Lee, Sung-Taek Lim
  • Patent number: 10681817
    Abstract: Aspects of the disclosure are directed to an edge card that includes a printed circuit board having a top side and a bottom side. The top side of the printed circuit board can include one or more top-side circuit components, and a plurality of top-side metal contact fingers, at least some of the top-side metal contact fingers electrically connected to at least one of the one or more circuit components. The bottom side of the printed circuit board can include one or more bottom-side circuit components. The bottom side of the printed circuit board can also include a substrate interposer having a top side and a bottom side. The top side of the substrate interposer can include one or more passive circuit components at least partially embedded in the substrate interposer, and one or more solder balls arranged around the one or more passive circuit components.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: June 9, 2020
    Assignee: Intel Corporation
    Inventor: Brian J. Long
  • Patent number: 10658258
    Abstract: A chip package including a first semiconductor die, a support structure and a second semiconductor die is provided. The first semiconductor die includes a first dielectric layer and a plurality of conductive vias, the first dielectric layer includes a first region and a second region, the conductive vias is embedded in the first region of the first dielectric layer; a plurality of conductive pillars is disposed on and electrically connected to the conductive vias. The second semiconductor die is stacked over the support structure and the second region of the first dielectric layer; and an insulating encapsulant encapsulates the first semiconductor die, the second semiconductor die, the support structure and the conductive pillars, wherein the second semiconductor die is electrically connected to the first semiconductor die through the conductive pillars.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: May 19, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Lung Pan, Hao-Yi Tsai, Tin-Hao Kuo
  • Patent number: 10622293
    Abstract: A semiconductor device has a semiconductor die with an encapsulant deposited over and around the semiconductor die. An interconnect structure is formed over a first surface of the encapsulant. An opening is formed from a second surface of the encapsulant to the first surface of the encapsulant to expose a surface of the interconnect structure. A bump is formed recessed within the opening and disposed over the surface of the interconnect structure. A semiconductor package is provided. The semiconductor package is disposed over the second surface of the encapsulant and electrically connected to the bump. A plurality of interconnect structures is formed over the semiconductor package to electrically connect the semiconductor package to the bump. The semiconductor package includes a memory device. The semiconductor device includes a height less than 1 millimeter. The opening includes a tapered sidewall formed by laser direct ablation.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: April 14, 2020
    Assignee: JCET Semiconductor (Shaoxing) Co., Ltd.
    Inventors: Seung Wook Yoon, Jose A. Caparas, Yaojian Lin, Pandi C. Marimuthu, Kang Chen, Xusheng Bao, Jianmin Fang
  • Patent number: 10497678
    Abstract: A semiconductor package assembly includes a first substrate. A first semiconductor die is disposed on the first substrate. A passive device is located directly on the first semiconductor die. The passive device is disposed within a boundary of the first semiconductor die in a plan view.
    Type: Grant
    Filed: October 6, 2017
    Date of Patent: December 3, 2019
    Assignee: MediaTek Inc.
    Inventors: Che-Hung Kuo, Ying-Chih Chen, Che-Ya Chou
  • Patent number: 10470309
    Abstract: An integrated circuit device, such as a system-on-a-chip (SOC) device that includes an integrated or embedded voltage regulator, comprises an integrated capacitor and an integrated inductor having a magnetic core that can be fabricated in the same process as the capacitive structure of the integrated capacitor.
    Type: Grant
    Filed: September 20, 2015
    Date of Patent: November 5, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Mete Erturk, Farsheed Mahmoudi, James Thomas Doyle, Ravindra Vaman Shenoy, Jitae Kim
  • Patent number: 10431537
    Abstract: A package assembly includes a substrate and at least a first die having a first contact array and a second contact array. First and second via assemblies are respectively coupled with the first and second contact arrays. Each of the first and second via assemblies includes a base pad, a cap assembly, and a via therebetween. One or more of the cap assembly or the via includes an electromigration resistant material to isolate each of the base pad and the cap assembly. Each first cap assembly and via of the first via assemblies has a first assembly profile less than a second assembly profile of each second cap assembly and via of the second via assemblies. The first and second cap assemblies have a common applied thickness in an application configuration. The first and second cap assemblies have a thickness variation of ten microns or less in a reflowed configuration.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: October 1, 2019
    Assignee: Intel Corporation
    Inventors: Srinivas Pietambaram, Jung Kyu Han, Ali Lehaf, Steve Cho, Thomas Heaton, Hiroki Tanaka, Kristof Darmawikarta, Robert Alan May, Sri Ranga Sai Boyapati
  • Patent number: 10396044
    Abstract: A semiconductor device includes a wiring substrate including a first surface and a second surface opposite to the first surface, a semiconductor chip including a plurality of chip electrodes and mounted over the wiring substrate, a first capacitor arranged at a position overlapping with the semiconductor chip in plan view and incorporated in the wiring substrate, and a second capacitor arranged between the first capacitor and a peripheral portion of the wiring substrate in plan view. Also, the second capacitor is inserted in series connection into a signal transmission path through which an electric signal is input to or output from the semiconductor chip.
    Type: Grant
    Filed: October 15, 2015
    Date of Patent: August 27, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kazuyuki Nakagawa, Keita Tsuchiya, Yoshiaki Sato, Shinji Baba
  • Patent number: 10306764
    Abstract: The invention relates to a variable sensor interface for a control unit, this variable sensor interface including a circuit board which is provided with components. In a sensor interface which can easily be used for the use of different sensor types, the circuit board has a predefined conductive track layout having a plurality of predefined mounting locations, the mounting locations being provided with components in a sensor-specific manner.
    Type: Grant
    Filed: March 20, 2015
    Date of Patent: May 28, 2019
    Assignee: SCHAEFFLER TECHNOLOGIES AG & CO. KG
    Inventors: Daniel Ritter, Steffen Linz, Thomas Wacker
  • Patent number: 10264681
    Abstract: A substrate includes a core substrate; a cavity formed on an upper surface side of the core substrate; a bottom plate of the cavity formed integrally with the core substrate; a through-hole formed in the bottom plate, a component mounting portion formed at a portion of the bottom plate, an electronic component mounted on the component mounting portion so as to be disposed inside the cavity; a first insulating layer formed on an upper surface of the core substrate so as to cover an upper surface of the electronic component; and a second insulating layer formed on a lower surface of the core substrate so as to fill the through-hole and cover a lower surface of the electronic component. The cavity is filled with the first insulating layer and the second insulating layer. The first insulating layer and the second insulating layer are formed of the same insulating resin.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: April 16, 2019
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Kenji Kawai
  • Patent number: 10264680
    Abstract: There is provided a multilayer ceramic electronic component embedded in a board including: a ceramic body including dielectric layers; first and second internal electrodes; and first and second external electrodes formed on first and second side surfaces of the ceramic body, respectively, wherein the first external electrode includes a first electrode layer and a first metal layer formed on the first electrode layer, the second external electrode includes a second electrode layer and a second metal layer formed on the second electrode layer, the first and second external electrodes are formed to be extended to first main surface of the ceramic body, and when a maximum width and a minimum width of at least one of the first and second external electrodes formed on the first main surface are defined as BWmax and BWmin, respectively, 0?BWmax?BWmin?100 ?m is satisfied.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: April 16, 2019
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jin Woo Lee, Jin Man Jung
  • Patent number: 10229915
    Abstract: A semiconductor structure and a method for fabricating the same. The semiconductor structure includes a substrate and a bonding layer in contact with a top surface of the substrate. At least one transistor contacts the bonding layer. The transistor includes at least one gate structure disposed on and in contact with a bottom surface of a semiconductor layer of the transistor. The semiconductor further includes a capacitor disposed adjacent to the transistor. The capacitor contacts the semiconductor layer of the transistor and extends down into the substrate. The method includes forming at least one transistor and then flipping the transistor. After the transistor has been flipped, the transistor is bonded to a new substrate. An initial substrate of the transistor is removed to expose a semiconductor layer. A capacitor is formed adjacent to the transistor and contacts with the semiconductor layer. A contact node is formed adjacent to the capacitor.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: March 12, 2019
    Assignee: International Business Machines Corporation
    Inventors: Terence B. Hook, Joshua M. Rubin, Tenko Yamashita