Abstract: A method for electrically interconnecting two substrates, each having a corresponding set of preformed electrical contacts, the substrates comprising an electronic circuit, and the resulting module, is provided. A liquid curable adhesive is provided over the set of contacts of a first substrate, and the set of electrical contacts of the second substrate is aligned with the set of electrical contacts of the first substrate. The sets of electrical contacts of the first and second substrate are compressed to displace the liquid curable adhesive from the inter-contact region, and provide electrical communication between the respective sets of electrical contacts. The liquid curable adhesive is then cured to form a solid matrix which maintains a relative compression between the respective sets of electrical contacts. One embodiment of the module comprises a high-speed superconducting circuit which operates at cryogenic temperatures.

Abstract: A wiring board includes a first resin insulation layer, an electronic component positioned on first surface of the first insulation layer, a second resin insulation layer formed on the first surface of the first insulation layer such that the second insulation layer is embedding the electronic component, a conductive layer formed on the second insulation layer, a third resin insulation layer formed on the conductive layer and second insulation layer, and a connection via conductor formed in the second insulation layer such that the connection via conductor is connecting electrode of the electronic component and conductive layer on the second insulation layer. The first insulation layer has a pad structure on second surface side of the first insulation layer on opposite side of the first surface, and the first insulation layer has coefficient of thermal expansion set lower than coefficients of thermal expansion of the second and third insulation layers.

Abstract: In some embodiments, an apparatus includes a first substrate, a second substrate, a first coupler, and a second coupler. The first substrate is formed from a first material and includes an electrical pad. The second substrate is formed from a second material and includes an electrical pad. The first coupler is configured to mechanically couple the first substrate to the second substrate without a soldered connection. The second coupler includes a first end portion, configured to be soldered to the electrical pad of the first substrate, and a second end portion, configured to be soldered to the electrical pad of the second substrate. The second coupler configured to electrically couple the first substrate to the second substrate.

Abstract: An electronic device may contain components such as flexible printed circuits and rigid printed circuits. Electrical contact pads on a flexible printed circuit may be coupled electrical contact pads on a rigid printed circuit using a coupling member. The coupling member may be configured to electrically couple contact pads on a top surface of the flexible circuit to contact pads on a top surface of the rigid circuit. The coupling member may be configured to bear against a top surface of the flexible circuit so that pads on a bottom surface of the flexible circuit rest against pads on a top surface of the rigid circuit. The coupling member may bear against the top surface of the flexible circuit. The coupling member may include protrusions that extend into openings in the rigid printed circuit. The protrusions may be engaged with engagement members in the openings.

Abstract: In a first conductive layer and a third conductive layer that are respectively closest to a core layer having a storage portion that penetrates therethrough, four first penetrating holes and four first penetrating holes are formed so as to overlap part of an opening edge of the storage portion that is projected onto the first conductive layer and the third conductive layer, respectively.

Abstract: The present invention relates to a device with portions of the device on plural substrate surfaces. The device includes a low resistivity substrate having first and second surfaces with a first electrically-conductive device component disposed over a first surface. An intermediate electrically-insulating layer may be disposed between the electrically-conductive component and the low resistivity substrate. A second electrically-conductive component is disposed over the second surface of the low resistivity substrate. A cavity formed in the low resistivity substrate is at least partially filled with a high resistivity material. One or more electrically-conducting pathways are formed in the high resistivity material electrically connecting the first electrically conductive component and the second electrically-conductive component to form a device. Exemplary devices include inductors, capacitors, antennas and active or passive devices incorporating such devices.

Abstract: Embodiments of the present disclosure describe apparatuses, methods, and systems of thermal via structures with surface features. In some embodiments the surface features may have dimensions greater than approximately one micron. The thermal via structures may be incorporated into a substrate of an integrated circuit device. Other embodiments may be described and/or claimed.

Abstract: An electronic component embedded printed circuit board and a method for manufacturing the same. The printed circuit board includes: a core having a cavity formed therein; an electronic component unit embedded in the cavity, including a plurality of electronic components, and having a coating layer formed on an outer peripheral surface of the electronic component unit to fix the plurality of electronic components; and an insulating layer laminated at least on the top of the core. An outer layer circuit pattern may be formed on the insulating layer.

Abstract: An apparatus includes a coreless substrate with an embedded die that is integral to the coreless substrate, and at least one device assembled on a surface that is opposite to a ball-grid array disposed on the coreless substrate. The apparatus may include an over-mold layer to protect the at least one device assembled on the surface.

Abstract: A printed wiring board includes a core substrate having a penetrating hole, a first conductive layer on a first surface of the substrate, a second conductive layer on a second surface of the substrate, a first electronic component having an electrode and accommodated in the hole such that the electrode faces the first surface, a first structure on the first surface and including a pad for mounting a second electronic component on the first structure and a via conductor connected to the electrode, and a second structure on the second surface. The electrode has an upper surface facing toward the first surface, the first layer has an upper surface facing away from the first surface, and the first component is positioned in the hole such that the upper surface of the electrode forms a gap with the upper surface of the first layer.

Abstract: An embedded device 105 is assembled within a flexible circuit assembly 30 with the embedded device mid-plane intentionally located in proximity to the flexible circuit assembly central plane 115 to minimize stress effects on the embedded device. The opening 18, for the embedded device, is enlarged in an intermediate layer 10 to enhance flexibility of the flexible circuit assembly.

Abstract: An embedded chip-on-chip package includes a printed circuit board having a recessed semiconductor chip mounting unit constituted by a recess in the printed circuit board and a circuit pattern at the bottom of the recess, a first semiconductor chip embedded in the recessed semiconductor chip mounting unit and electrically connected to the circuit pattern at the bottom of the recess, and a second semiconductor chip mounted to the recessed semiconductor chip mounting unit and electrically connected to the first semiconductor chip and the printed circuit board independently of each other.

Abstract: A MMIC having: a substrate; a plurality of active and passive electrical elements disposed on a top surface of the substrate; a plurality of coplanar waveguide transmission line sections disposed on the top surface of the substrate for electrically interconnecting the active and passive electrical elements; an electrical conductor disposed on a bottom surface of the substrate under the coplanar waveguide section. Edges of ground plane conductors of the coplanar waveguide (CPW) sections have slots therein in regions thereof connected to the active and passive devices. The design of such circuit includes mathematical models of the CPW with the pair of local ground planes and the strip conductor thereof have relatively narrow connectable ports.

Abstract: An electronic component is mounted on a circuit board. The electronic component includes: a lead frame including a fixed portion, a lead portion connected to the fixed portion, and a heat-dissipating portion connected to the fixed portion; a semiconductor chip fixed on the fixed portion by a first binder; and an encapsulation resin for encapsulating the fixed portion, the semiconductor chip, and a base portion of the lead portion. A groove is provided in the fixed portion and the heat-dissipating portion of the lead frame. The groove extends from a portion of the fixed portion where the first binder is present toward the heat-dissipating portion.

Abstract: Embodiments disclosed herein generally include using a large number of small MEMS devices to replace the function of an individual larger MEMS device or digital variable capacitor. The large number of smaller MEMS devices perform the same function as the larger device, but because of the smaller size, they can be encapsulated in a cavity using complementary metal oxide semiconductor (CMOS) compatible processes. Signal averaging over a large number of the smaller devices allows the accuracy of the array of smaller devices to be equivalent to the larger device. The process is exemplified by considering the use of a MEMS based accelerometer switch array with an integrated analog to digital conversion of the inertial response. The process is also exemplified by considering the use of a MEMS based device structure where the MEMS devices operate in parallel as a digital variable capacitor.

Abstract: Substrates for integrated passive devices are described herein. Embodiments of the present invention provide substrates including a glass layer and at least one passive device disposed thereon. According to various embodiments of the present invention, the glass layer may have a thickness adapted to minimize conductive and/or other interactions between the substrate and the at least one passive device. Other embodiments may be described and claimed.

Abstract: In order to keep impedance characteristics to desired values across the entire operating frequency band, an electronic circuit of the present invention includes an integrated circuit, a decoupling capacitor, and a multilayer circuit board on which the integrated circuit and the decoupling capacitor are mounted. In the electronic circuit, a planar land is formed on one or both of a power layer and a ground layer of the multilayer circuit board, the land having densely disposed therein a plurality of via holes that connect a terminal of the integrated circuit and a corresponding terminal of the decoupling capacitor, and the land formed on the power layer or the ground layer is discontinuously disposed at a predetermined interval with a gap having a predetermined width provided therebetween.

Abstract: The present disclosure relates to reducing unwanted RF noise in a printed circuit board (PCB) containing an RF device. An isolation filter is embedded in a PCB containing an RDF device. By placing the isolation filter as close as possible to the RF device in order to dramatically reduce unwanted RF noise due to unavoidable coupling between Vias and planes in the PCB structure.

Abstract: A method for manufacturing a printed circuit board includes forming an opening portion in a substrate, positioning chip capacitors in the opening portion of the substrate such that the chip capacitors are accommodated in the opening portion of the substrate, forming a buildup structure including an interlayer resin insulating layer and a conductive layer over a surface of the substrate and the chip capacitors accommodated in the opening portion of the substrate, and forming on a surface of the buildup structure bump structures positioned to mount an IC chip such that the chip capacitors in the opening portion of the substrate are positioned directly below the IC chip.

Abstract: Embodiments of the present invention are directed to shifting the resonant frequency in a high-frequency chip package away from an operational frequency by connecting a capacitance between an open-ended plating stub and ground. One embodiment provides a multi-layer substrate for interfacing a chip with a printed circuit board. A first outer layer provides a chip mounting location. A signal interconnect is spaced from the chip mounting location, and a signal trace extends from near the chip mounting location to the signal interconnect. A chip mounted at the chip mounting location may be connected to the signal trace by wirebonding. A plating stub extends from the signal interconnect, such as to a periphery of the substrate. A capacitor is used to capacitively couple the plating stub to a ground layer.

Abstract: A printed circuit board according to one example embodiment includes a Z-directed component mounted in a mounting hole in the printed circuit board. The Z-directed component includes a body having a top surface, a bottom surface and a side surface. Four conductive channels extend through a portion of the body along the length of the body. The four conductive channels are spaced substantially equally around a perimeter of the body. An integrated circuit is mounted on a surface of the printed circuit board. The integrated circuit has a ball grid array that includes four conductive balls electrically connected to a corresponding one of the four conductive channels of the Z-directed component.

Abstract: A planar transformer assembly, for use in charging capacitors of an ICD, includes windings arranged to minimize voltage across intervening dielectric layers. Each secondary winding of a preferred plurality of secondary windings is arranged relative to a primary winding, in a hierarchical fashion, such that the DC voltage, with respect to ground, of a first secondary winding, of the plurality of secondary windings, is lower than that of a second secondary winding, with respect to ground, wherein the first secondary winding is in closest proximity to the primary winding. The primary winding and each secondary winding are preferably formed on a corresponding plurality of dielectric layers.

Abstract: A printed circuit board including a core substrate including a first resin substrate, a second resin substrate having an opening and a third resin substrate in a multilayer manner while interposing bonding plates, insulating layers and conductive circuit layers alternately laminated on the core substrate, solder bumps formed on an outer surface of the printed circuit board, a first capacitor formed in the opening of the second resin substrate, a conductive pad formed on the first resin substrate and connected to an electrode of the first capacitor, a via hole formed in the first resin substrate and directly connected to the conductive pad and a conductive circuit on the core substrate, and a second capacitor mounted on a surface of the printed circuit board.

Abstract: A packaging substrate includes: a dielectric layer unit having top and bottom surfaces; a positioning pad embedded in the bottom surface of the dielectric layer unit; at least a passive element having a plurality of electrode pads disposed on upper and lower surfaces thereof, the passive element being embedded in the dielectric layer unit and corresponding to the positioning pad; a first circuit layer disposed on the top surface of the dielectric layer unit, the first circuit layer having first conductive vias electrically connected to the electrode pads disposed on the upper surface of the passive element; and a second circuit layer disposed on the bottom surface of the dielectric layer unit, the second circuit layer having second conductive vias electrically connected to the electrode pads disposed on the lower surface of the passive element. Through the embedding of the passive element, the overall structure may have a reduced height.

Abstract: A printed circuit board includes an accommodating layer, chip capacitor devices accommodated in the accommodating layer, and a buildup structure formed on the accommodating layer such that the buildup structure covers the chip capacitor devices in the accommodating layer. The buildup structure has mounting conductor structures positioned to mount an IC chip device on a surface of the buildup structure such that the IC chip device is mounted directly over the chip capacitor devices, each of the chip capacitor devices has a dielectric body having a surface facing the buildup structure, a first electrode formed on the dielectric body and extending on the surface of the dielectric body, and a second electrode formed on the dielectric body and extending on the surface of the dielectric body, and the dielectric body is interposed between the first electrode and the second electrode.

Abstract: A single-layer component package comprising: a single conductive-pattern layer having a first surface; an insulating-material layer on the first surface of the single conductive-pattern layer; in an installation cavity inside the insulating-material layer, a semiconductor component having flat contact zones; and solid contact pillars containing copper and solderlessly, metallurgically and electrically connecting the flat contact zones to the single conductive-pattern layer.

Abstract: In a high-frequency module, a laminate including a plurality of dielectric layers each including an electrode pattern located thereon, and a switch element which includes a test terminal arranged to output a negative voltage applied to the switch element and which is mounted on the laminate, are integrally formed. A test external terminal for external connection which outputs a signal to the outside is provided on a back surface of the laminate. The laminate includes a voltage transmission path electrically connecting the test terminal to the test external terminal.

Abstract: There is provided a device for surface mounting that has a substrate and a capacitor element loaded on a loading-side surface of the substrate and is integrally molded including the substrate and the capacitor element using a packaging resin. The substrate includes a first terminal electrode electrically connected to a first electrode of the capacitor element and a second terminal electrode electrically connected to a second electrode of the capacitor element, at least part of a mounting-side surface on an opposite side to the loading-side surface of the substrate is exposed on a mounting surface of the device, and the first terminal electrode and the second terminal electrode are adjacently disposed around an entire circumference of the mounting surface of the device.

Abstract: A ceramic multilayer substrate incorporating a chip-type ceramic component, in which, even if the chip-type ceramic component is mounted on the surface of the ceramic multilayer substrate, bonding strength between the chip-type ceramic component and an internal conductor or a surface electrode of the ceramic multilayer substrate is greatly improved and increased. The ceramic multilayer substrate includes a ceramic laminate in which a plurality of ceramic layers are stacked, an internal conductor disposed in the ceramic laminate, a surface electrode disposed on the upper surface of the ceramic laminate, and a chip-type ceramic component bonded to the internal conductor or the surface electrode through an external electrode. The internal conductor or the surface electrode is bonded to the external electrode through a connecting electrode, and the connecting electrode forms a solid solution with any of the internal conductor, the surface electrode, and the external electrode.

Abstract: A wiring substrate includes an electronic component and a core substrate. A through hole extends through the core substrate and accommodates the electronic component, which includes a main body and connection terminals. The main body includes opposing first side surfaces, opposing second side surfaces, and opposing third side surfaces. The connection terminals cover the first side surfaces. First projections project from walls of the through hole toward the first side surfaces. Each first projection includes a distal end that contacts one of the connection terminals. Second projections project from walls of the through hole toward the second side surfaces. The opposing second projections include distal ends spaced apart by a distance longer than the distance between the second side surfaces and shorter than the distance between two farthest points on a periphery of each first side surface.

Abstract: A connector for connecting surface mount devices, such as light emitting diodes (LEDs), to printed circuit boards (PCBs). The connector may be prepackage with an LED assembly or on a PCB to which the LED assembly will be mounted. Connection complexity can be moved from the PCB to the connector, and LED assemblies may be customized differently for different customers. One to many and many to one connections are readily supported with variations on the connector.

Abstract: According to one embodiment, coupling capacitance in a state in which a first heat radiation member is arranged between parallel flat plates of a first capacitor formed by a surface of a housing opposed to one surface of a printed circuit board and the printed circuit board is smaller than coupling capacitance in a state in which an integrally formed object having a relative dielectric constant of 5.8 is arranged between the first capacitor to cover a first radiating region containing the controller and the first nonvolatile semiconductor memories.

Abstract: A printed circuit board that include: an electronic component having a plating electrode pad having a predetermined thickness; an insulating resin layer that exposes a lower surface of the electrode pad, receives the electronic component, and embodies the electronic component so that the center of the base body forming the electronic component is positioned at the center of the insulating resin layer; and circuit layers that include a circuit pattern disposed on the electrode pad, form inter-layer connection, and are disposed on both surfaces of the insulating resin layer, respectively, the plating electrode pad having a thickness that conforms to a thickness from an upper surface of the electronic component to an upper surface of the insulating resin.

Abstract: A printed circuit board includes an accommodating layer, chip capacitor devices accommodated in the accommodating layer, and a buildup structure formed on the accommodating layer such that the buildup structure covers the chip capacitor devices in the accommodating layer. The buildup structure has mounting conductor structures positioned to mount an IC chip device on a surface of the buildup structure such that the IC chip device is mounted directly over the chip capacitor devices, each of the chip capacitor devices has a dielectric body having a surface facing the buildup structure, a first electrode formed on the dielectric body and extending on the surface of the dielectric body, and a second electrode formed on the dielectric body and extending on the surface of the dielectric body, and the dielectric body is interposed between the first electrode and the second electrode.

Abstract: The instant disclosure provides a self-sealed stacked structure which includes a substrate unit, a first frame, a conductive unit and a blocker unit. The substrate unit includes a first and a second substrate, and a first frame sandwiched there-between. The conductive unit includes a plurality of first conductors and second conductors electrically connecting the first substrate, the first frame and the second substrate. The first and the second conductors are in electrical connection. A blocker unit including at least two first and at least two second blockers are surroundingly arranged around the plurality of first and second conductors, respectively. The first substrate and the first frame are connected in a sealed manner through the first blockers combined by the solder, where the first frame and the second substrate are connected in a sealed manner through the second blockers combined by the solder.

Abstract: Stacked arrays of components are disclosed. In one embodiment, a first and a second layer of components are electrically and mechanically coupled to an interposer with an encapsulated third layer of components disposed between the first and second layers. The first layer can be configured to attach the stacked array to a host printed circuit board. The interposer can couple signals between the components on the first and second layers.

Abstract: An electronic device comprises a functional stack (10) and a cover (50) coupled thereto by an insulating adhesive layer (30). The functional stack (10) comprises a first transparent and electrically conductive layer (22), a second electrically conductive layer (24) and a functional structure (26), comprising at least one layer, sandwiched between said first and second conductive layer. The cover (50) includes a substrate (52) and at least a first conductive structure (66, 68) that is arranged in a first plane between the adhesive layer (28) and the substrate (52). First and second transverse electrical conductors (32, 34) transverse to the first plane (61) electrically interconnect the first and the second electrically conductive layer (22, 24) with the first and the second conductive structure (66, 68) in the first plane (61).

Abstract: A wiring board includes a substrate having an opening portion, multiple electronic devices positioned in the opening portion such that the electronic devices are arrayed in the lateral direction of each of the electronic devices, and an insulation layer formed on the substrate such that the insulation layer covers the electronic devices in the opening portion of the substrate. The substrate has a wall surface defining the opening portion and formed such that the opening portion is partially partitioned and the electronic devices are kept from making contact with each other.

Abstract: Substrates having power planes, such as, for example, printed circuit boards, include at least one noise suppression structure configured to suppress electrical waves propagating through at least one of a first power plane and a second power plane. The at least one noise suppression structure may include a first power plane extension that extends from the first power plane generally toward the second power plane, and a second power plane extension that extends from the second power plane generally toward the first power plane. Methods for suppressing noise in at least one of the first power plane and second power plane include providing such noise suppression structures between the power planes.

Abstract: An apparatus having a power converter circuit having a first active layer having a first set of active devices disposed on a face thereof, a first passive layer having first set of passive devices disposed on a face thereof, and interconnection to enable the active devices disposed on the face of the first active layer to be interconnected with the non-active devices disposed on the face of the first passive layer, wherein the face on which the first set of active devices on the first active layer is disposed faces the face on which the first set of passive devices on the first passive layer is disposed.

Abstract: In one embodiment, a circuit board is disclosed. The circuit board includes a first metal core; a second metal core spaced apart from the first metal core in a first direction when viewed as a cross section, such that a first side of the first metal core faces a first side of the second metal core; a first electrode electrically connected to the first side of the first metal core; a second electrode electrically connected to the first side of the second metal core facing the first metal core; and a dielectric layer between the first and second electrodes.

Abstract: Disclosed is a wiring board with a built-in component and a method for manufacturing the same, the wiring board including: a wiring pattern; an electric/electronic component electrically and mechanically connected with a surface of said wiring pattern; and an insulating layer formed on the same surface of said wiring pattern as said electric/electronic component is connected and configured so as to embed said electric/electronic component, said insulating layer having an insulating resin and a reinforcing material included in the insulating resin, wherein the reinforcing material of said insulating layer exists in the insulating resin without reaching a region of said electric/electronic component in a lateral direction, and wherein the insulating resin of said insulating layer reaches said electric/electronic component so as to adhere to said electric/electronic component.

Abstract: An electric power conversion apparatus is provided which includes electronic components, a cooler, an internal unit, a capacitor, and a case. The internal unit has a frame to which at least one of the electronic components and the cooler are secured and which surrounds all around the one of the electronic components. The frame includes unit fixing sections through which the internal unit is fixed to the case and capacitor fixing sections through which the capacitor is fixed to the internal unit. The capacitor fixing sections are located inward of the frame more than the unit fixing sections. The internal unit is fixed to the case and thus works as a beam to increase the mechanical rigidity of the case. The fixing of the internal unit to the case minimizes external force to be exerted through the case on the electronic component and the cooler.

Abstract: Data carrier for contactless data transmission comprising a substrate, a chip having at least one connection pad, wherein the chip is arranged by its side remote from the connection pad on the substrate and a first copper-coated prepreg layer is arranged on the chip and at least partly on the substrate and has a contact opening to the connection pad. A plated-through hole is situated within the contact opening for producing an electrically conductive connection between the connection pad of the chip and the copper layer of the first copper-coated prepreg layer, wherein a first antenna structure is formed in the copper layer of the first copper-coated prepreg layer.

Abstract: A capacitive interposer, electronic package having the capacitive interposer and electronic device with the electronic package is described. The interposer has a first planar face and a second planar face. An array of upper connections is on the first planar face and opposing lower connections are on the second planar face with conduction paths between each upper connection of the upper connections and a lower connection of the lower connections. At least one power feed-through capacitor is provided. The capacitor is mounted on the first planar face with the first external termination in direct electrical contact with a first upper connection and the second external termination is in direct electrical contact with a second upper connection. At least one upper connection, first external termination and second external termination are arranged for direct electrical contact with element contact pads of a common element.

Abstract: The present technology relates to fused capacitor structures provided with a leadframe design configured to accepting a plurality of selectively placed fuses. The leadframe and fuse configuration enables construction of fused capacitors exhibiting low Equivalent Series Resistance (ESR) and allows construction of a variety of fuse configuration using a single leadframe design.

Abstract: A printed circuit board includes a core substrate having an opening portion, an electronic component provided in the opening portion of the core substrate and including a dielectric body, a first electrode formed over the dielectric body, and a second electrode formed over the dielectric body such that the dielectric body is interposed between the first electrode and the second electrode, and a resin filling a gap between the core substrate and the electronic component in the opening portion of the core substrate. The resin filling the gap includes a filler.

Abstract: A printed wiring board (PWB) including one or more embedded capacitors. The PWB defines a planar area and includes a plurality of first conductive plates that are substantially parallel to the planar area and extend from a first normal axis towards a second normal axis. The first normal axis and the second normal axis extend substantially perpendicularly through the planar area. The PWB also includes one or more second conductive plates that are substantially parallel to the planar area and extend from the second normal axis towards the first normal axis. The second conductive plates are positioned between the first conductive plates. A non-conductive material is positioned between the first and second conductive plates. At least one first conductive via extends substantially collinear with the first normal axis in contact with the first conductive plates. A plurality of second conductive vias extends substantially collinear with the second normal axis in contact with the second conductive plate.

Abstract: A printed wiring board includes a core substrate having opening, an electronic component device accommodated in the opening of the substrate and including inductor and passive components, a wiring structure connecting the inductor and passive components in the electronic device, a filler resin body filling space formed between the substrate and electronic device in the opening of the substrate, a first buildup layer including a first interlayer insulation layer on first surface of the substrate, a first conductive layer on the first insulation layer, and a first via conductor in the first insulation layer, and a second buildup layer including a second interlayer insulation layer on second surface of the substrate on the opposite side of the first surface of the substrate, a second conductive layer on the second insulation layer, and a second via conductor in the second insulation layer.

Abstract: A circuit board having a semiconductor chip embedded therein includes: a core board having opposing first and second surfaces and a through-hole; a semiconductor chip received in the through-hole and having a first active surface and an opposing second active surface, wherein first electrode pads comprising signal pads, power pads, and ground pads are provided on the first active surface; a first dielectric layer provided on the first surface of the core board and the first active surface of the semiconductor chip and configured to fill a gap between the through-hole and the semiconductor chip so as to secure the semiconductor chip in position to the through-hole; and a first circuit layer disposed in the first dielectric layer so as to be flush with the first dielectric layer, provided with first conductive vias disposed in the first dielectric layer, and electrically connected to the first electrode pads.