Abstract: A protective, anti-tamper coating and methods of coating creation and application are provided. The coating may include an elastomeric layer to allow for strippability/removal. The coating may also include a “smart layer” for tamper detection, imaging prevention, and tamper prevention or underlying device de-activation/alteration upon tamper detection. The coating may also include one or more ground planes around the smart layer and one or more frangible layers designed to interrupt or alter smart layer function in the event of a tamper attempt.

Abstract: In a method of manufacturing a multilayer printed circuit board, a first insulating resin base material is formed. A resin surface of a second insulating resin base material formed by attaching copper foil on a surface of a resin-insulating layer is unified with the first insulating resin base material. A conductor circuit is formed on the second insulating resin base material and a via hole electrically connecting to the conductor circuit. A concave portion is formed from a resin-insulating layer surface in a conductor circuit non-formation area of the first insulating resin base material. A semiconductor element is housed within the concave portion and adhered with an adhesive. A resin-insulating layer is formed by coating the semiconductor element and a via hole.

Abstract: High-frequency circuit components are disclosed in which parasitic capacitance between a high-frequency circuit element and a substrate is reduced and mechanical strength is improved. An exemplary component has a conductive substrate, a coil as the high-frequency circuit-element, a mounting board including a thin dielectric film on which the coil is mounted, and a support board that couples the mounting board to the substrate. The mounting board is coupled so that it floats relative to the substrate as a result of deliberate warping of the support board.

Abstract: A printed circuit board includes a high-speed differential signal control chip, first to fourth coupling capacitor pads, first and second connector pads, first and second inductor pads, a number of transmission lines, a power pin, two sharing pads, and two selection pads. Two coupling capacitors can selectively connect the first and second coupling capacitor pads and the two sharing pads or between the third and fourth coupling capacitor pads and the two sharing pads, respectively. Two inductors can connect the first and second inductor pads and the two selection pads respectively, and the first and second inductor pads and the two selection pads can be void.

Abstract: A multilayer capacitor includes a laminate of ceramic layers, and a capacitor unit provided in the laminate. In the multilayer capacitor, the relationships P?Ra and P?W are established, wherein P represents the average projection height of first and second via conductors from the upper surface, Ra represents the surface roughness of the upper surface, and W represents an amount of curvature of the laminate. Further, the projecting portions of the first and second via conductors projecting from the upper surface are buried in first and second external electrodes, respectively.

Abstract: A chip capacitor is provided in a core substrate of a printed circuit board. This makes it possible to shorten a distance between an IC chip and the chip capacitor and to reduce loop inductance. Since the core substrate is constituted by provided a first resin substrate, a second resin substrate and a third resin substrate in a multilayer manner, the core substrate can obtain sufficient strength.

Abstract: The invention discloses integrated circuits (ICs), molded IC packages, and to leadframe arrays, package arrays and methods for their manufacture. Leadframe arrays and package arrays used for the manufacture of IC packages by transfer molding processes include a locking feature adapted for encapsulation. The locking feature is situated in a strap of the leadframe array overlying a gate between mold cavities. The strap lock formed by curing encapsulant in the locking feature of the strap strengthens the resulting package array and provides improved mold extraction and handling characteristics.

Abstract: A chip capacitor 20 is provided in a core substrate 30 of a printed circuit board 10. This makes it possible to shorten a distance between an IC chip 90 and the chip capacitor 20 and to reduce loop inductance. Since the core substrate 30 id constituted by provided a first resin substrate 30a, a second resin substrate 30b and a third resin substrate 30c in a multilayer manner, the core substrate 30 can obtain sufficient strength.

Abstract: A chip capacitor 20 is provided in a core substrate 30 of a printed circuit board 10. This makes it possible to shorten a distance between an IC chip 90 and the chip capacitor 20 and to reduce loop inductance. Since the core substrate 30 is constituted by provided a first resin substrate 30a, a second resin substrate 30b and a third resin substrate 30c in a multilayer manner, the core substrate 30 can obtain sufficient strength.

Abstract: Chip capacitors 20 are provided in a printed circuit board 10. In this manner, the distance between an IC chip 90 and each chip capacitor 20 is shortened, and the loop inductance is reduced. In addition, the chip capacitors 20 are accommodated in a core substrate 30 having a large thickness. Therefore, the thickness of the printed circuit board does not become large.

Abstract: Disclosed herein is a printed circuit board having an RF module power stage circuit embedded therein. Specifically, this invention relates to a printed circuit board having an RF module power stage circuit embedded therein, in which a terminal pad for a resistor, a bead, or an inductor is defined or formed on a power supply plane of a multilayered wired board to connect the resistor, the bead, or the inductor to the power supply plane, and the resistor, the bead, or the inductor is connected in parallel with a decoupling capacitor by using a via hole or by embedding the resistor, the bead or the inductor perpendicular to the power supply plane, thus decreasing the size of the RF module and improving the performance thereof.

Abstract: A multilayer printed circuit board has an IC chip (20) included in a core substrate (30) in advance and a transition layer (38) provided on a pad (24) of the IC chip (20). Due to this, it is possible to electronically connect the IC chip to the multilayer printed circuit board without using lead members and a sealing resin. Also, by providing the transition layer (38) made of copper on the die pad (24), it is possible to prevent resin residues on the pad (24) and to improve connection characteristics between the pad (24) and a via hole (60) and reliability.

Abstract: Micromodules and methods of making them are disclosed. An exemplary micromodule includes a substrate having a thin film inductor, and a bumped die mounted on the substrate and over the thin film inductor.

Abstract: An interconnect module and a method of manufacturing the same. The method of making an interconnect module on a substrate comprises forming an interconnect section on the substrate. The interconnect section comprises at least two metal interconnect layers separated by a dielectric layer. The method further comprises forming a passive device on the substrate at a location laterally adjacent to the interconnect section. The passive device comprises at least one moveable element comprising a metal layer. The method further comprises forming the metal layer and one of the at least two metal interconnect layers from substantially the same material.

Abstract: In a semiconductor device such as a high-frequency power amplifier module, a plurality of amplifying means are formed on a semiconductor chip which is mounted on a main surface of a wiring substrate, and electrodes of the semiconductor chip are electrically connected by wires to electrodes of the wiring substrate. In order to make the high-frequency power amplifier module small in size, a substrate-side bonding electrode electrically connected to a wire set at a fixed reference electric potential is place at a location farther from a side of the semiconductor chip than a substrate-side output electrode electrically connected to an output wire. A substrate-side input electrode electrically connected to an input wire is located at a distance from the side of the semiconductor chip about equal to the distance from the side of the semiconductor chip to the substrate-side output electrode, or at a location farther from the side of the semiconductor chip than the substrate-side bonding electrode is.

Abstract: This invention relates to a capacitive/resistive device, which may be embedded within a layer of a printed wiring board. Embedding the device conserves board surface real estate, and reduces the number of solder connections, thereby increasing reliability. More specifically, the device, comprises a first metallic foil; a second metallic foil; a first electrode formed from the first metallic foil; a dielectric disposed over the first electrode; a resistor element formed on and adjacent to the dielectric; a conductive trace; and a second electrode formed from the second metallic foil and disposed over the dielectric and in electrical contact with the resistor element, wherein the dielectric is disposed between the first electrode and the second electrode and wherein said dielectric comprises an unfilled polymer of dielectric constant less than 4.0.

Abstract: A wiring board having an excellent electrical property and reliability or the like. The wiring board includes a core board, a capacitor and a resin filler. The core board includes an accommodation hole therein and a core board main surface side conductor disposed on the core main surface thereof. A capacitor main surface side electrode is disposed on a capacitor main surface of the capacitor. A gap between the capacitor accommodated in the accommodation hole and the core board is filled with the resin filler so that the capacitor is fixed to the core board. Further, the resin filler has a main surface side wiring forming portion on which a main surface side connecting conductor, which is connected to an end portion of a via conductor, is disposed so as to connect the core board main surface side conductor to the capacitor main surface side electrode.

Abstract: A circuit board includes power reference layers and a capacitor provided between the power reference layers such that a shorter dimension of the capacitor defines a space between the power reference layers. The capacitor has plural conductive plates and plural dielectric layers.

Abstract: The semiconductor device concerning the present invention has a wiring substrate, a semiconductor chip, under-filling resin, a reinforcement ring, a heat spreader, a power supply pattern and a wiring layer under surface via land which are formed on the wiring substrate and spaced out by a clearance region, an insulating film, a wiring layer via land, a via, and a wiring which is formed on the insulating film, passes over the clearance region, and connects the wiring layer via land to the semiconductor chip. The wiring layer via land is formed between the semiconductor chip and the reinforcement ring, and within a region of a 1 mm width from the extension line of the diagonal line of the semiconductor chip. The angle of the lead-out direction of the wiring from a wiring layer via land to the extension line of the diagonal line of the semiconductor chip is 20° or more.

Abstract: A flexible substrate includes: (i) a film; (ii) an insulating resin layer formed on each of a front face of the film and a rear face of the film, which rear face is opposite to the front face; (iii) a front-sided wiring pattern embedded in the insulating resin layer formed on the front face of the film, and a rear-sided wiring pattern embedded in the insulating resin layer formed on the rear face of the film; and (iv) a via which is located between the front-sided wiring pattern and the rear-sided wiring pattern and serves to electrically interconnect the front-sided wiring pattern and the rear-sided wiring pattern, wherein the insulating resin layer formed on each of the front face and the rear face of the film is thicker than the film.

Abstract: A capacitor built-in interposer of the present invention, includes a base resin layer, a capacitor first electrode provided to pass through the base resin layer and having projection portions projected from both surface sides of the base resin layer respectively whereby the projection portion on one surface side of the base resin layer serves as a connection portion, a capacitor dielectric layer for covering the projection portion of the first electrode on other surface side of the base resin layer, and a capacitor second electrode for covering the dielectric layer, wherein a plurality of capacitors each constructed by the first electrode, the dielectric layer, and the second electrode are arranged and aligned in a lateral direction in a state that the capacitors are passed through the base resin layer.

Abstract: An electronic substrate is disclosed that includes: a substrate having a first face on which an active region is formed, and a second face on an opposite side to the first face and on which a passive element is formed. The substrate may further include: a penetrative conductive portion penetrating through the substrate; and an electrode formed on the first face, wherein the passive element is electrically connected to the electrode via a penetrative conductive portion.

Abstract: The invention discloses integrated circuits (ICs), molded IC packages, and to leadframe arrays, package arrays and methods for their manufacture. Leadframe arrays and package arrays used for the manufacture of IC packages by transfer molding processes include a locking feature adapted for encapsulation. The locking feature is situated in a strap of the leadframe array overlying a gate between mold cavities. The strap lock formed by curing encapsulant in the locking feature of the strap strengthens the resulting package array and provides improved mold extraction and handling characteristics.

Abstract: An interconnection line device includes an insulating layer for electrical insulation; an external connection terminal which is formed on one surface of the insulating layer: an interconnection line which is formed on another surface of the insulating layer and whose one end portion area is connected to a predetermined signal line; and a connection portion which is arranged so as to penetrate through the insulating layer and connects another end portion area of the interconnection line to the external connection terminal.

Abstract: In a module with embedded electronic components, connection electrodes are formed on the component mounting surface of a substrate. The electrode portions of each of the electronic components are placed on the individual connection electrodes and connected in fixed relation thereto by using a solder. The electronic components are encapsulated in an encapsulating resin.

Abstract: A method including forming a layer of a first ceramic material on a substrate; and after forming the layer, forming a second ceramic material on the layer of the first ceramic material, the formed second ceramic material including an average grain size less than a grain size of the first ceramic material. An apparatus including a first electrode; a second electrode; and a sintered ceramic material, wherein the ceramic material comprises first ceramic grains defining grain boundaries therebetween and second ceramic grains having an average grain size smaller than a grain size of the first ceramic grains. A system including a device including a microprocessor, the microprocessor coupled to a circuit board through a substrate, the substrate including a capacitor structure formed on a surface, the capacitor structure including a first electrode, a second electrode, and a sintered ceramic material disposed between the first electrode and the second electrode.

Abstract: A semiconductor package includes: a build-up wiring layer including a metal wiring layer and an insulation resin layer; and a low thermal expansion material layer having a coefficient of thermal expansion closer to that of a semiconductor chip mounted on the build-up wiring layer as compared with the insulation resin layer of the build-up wiring layer, the low thermal expansion material layer being bonded to an entire region of a rear surface of the build-up wiring layer corresponding to a region of a front surface of the build-up wiring layer on which the semiconductor chip is mounted.

Abstract: A printed circuit board is fabricated so contacts for tight-pitch components are at an angle with respect to the bundles of glass fibers in the epoxy-glass printed circuit board such that adjacent component contacts do not contact the same bundle of glass fibers. This angle may be accomplished by manufacturing a printed circuit board panel with the glass fibers at an angle with respect to its edges. This angle may also be accomplished by placing parts on a printed circuit board panel that has a traditional X-Y orthogonal weave of glass fiber bundles at an angle with respect to the edges of the panel. This angle may also be accomplished by starting with a traditional panel that has an X-Y orthogonal weave, laying out parts on the panel along the X-Y weave, then placing components on the parts at an angle with respect to the edges of the parts.

Abstract: In a module with embedded electronic components, connection electrodes are formed on the component mounting surface of a substrate. The electrode portions of each of the electronic components are placed on the individual connection electrodes and connected in fixed relation thereto by using a solder. The electronic components are encapsulated in an encapsulating resin.

Abstract: A high-frequency module having a communication function is provided which includes a base substrate block (2) formed from organic substrates (11, 12), the organic substrate (11) having wiring layers (14, 15) formed on main sides, respectively, thereof while the organic substrate (12) has wiring layers (16, 17) formed on main sides, respectively, thereof, the base substrate block (2) having a buildup surface formed by flattening an uppermost layer, and an elements block (3) formed from organic insulative layers (26, 28) formed on the buildup surface of the base substrate block (2) and in which a plurality of conductive parts (19, 20, 32) forming passive elements and distributed parameter elements, which transmit a high-frequency signal, are formed along with wiring layers (27, 29). The conductive parts (19, 20, 32) in the elements block (3) are formed correspondingly to portions of the organic substrate (11) in the base substrate block (2) where no woven glass fabric is laid.

Abstract: Provided are active balancing modules that control voltage imbalances between capacitors stacked in a series arrangement and methods for their manufacture. These modules are simple and inexpensive to manufacture, and versatile. They may be used alone or they may be combined together to form a multi-module active balancing circuitry for a plurality of capacitors stacked in a series arrangement. The modules may further be aligned in either a side-by-side topology or an overlapping topology.

Abstract: Circuit modules, systems and devices for controlling voltages across capacitors.

Abstract: The circuit device includes a first transmitting inductor, a first insulating layer, a first receiving inductor, and a second receiving inductor. The first transmitting inductor is constituted of a helical conductive pattern and receives a transmitted signal. The first receiving inductor is located in a region overlapping the first transmitting inductor through the first insulating layer. The first receiving inductor is constituted of a helical conductive pattern, and generates a received signal corresponding to the transmitted signal input to the first transmitting inductor. The second receiving inductor is connected in series to the first receiving inductor, and constituted of a helical conductive pattern. The second receiving inductor generates a voltage in an opposite direction to that generated by the first receiving inductor, in response to a magnetic field of the same direction.

Abstract: This invention effectively prevents potential fluctuation in the power supply terminal of a semiconductor device, that is, noise from flowing out to a main power supply wiring. A multilayer print circuit board includes a first power supply via hole which connects to the power supply terminal of a semiconductor integrated circuit on a first surface layer and extends from the first surface layer to a second surface layer, a ground via hole which connects to a ground conductive layer, extends from the ground conductive layer to the second surface layer, and connects to the first power supply via hole on the second surface layer through a bypass capacitor, a first clearance hole which is formed in a power supply conductive layer, and a second clearance hole which is formed in the ground conductive layer. The first clearance hole is larger than the second clearance hole.

Abstract: An apparatus, and a method for forming, a split thin film capacitor for providing multiple power and reference supply voltage levels to electrical devices such as integrated circuits, may be useful in space restricted applications, and in applications that require very close electrical connections between the power consumer and the power supply. An example of both a space restricted application and a close coupling application may be an integrated circuit (IC) such as a microprocessor. The capacitor supplying and moderating power to the microprocessor needs to be closely coupled in order to respond to instantaneous power demands that may be found in high clock rate microprocessors, and the space inside a microprocessor package is very restricted.

Abstract: The printed wiring board includes: a conductive wiring which is formed on a surface of a board and has a plurality of solder lands, to which components to be mounted are electrically connected by solder; and first and second electrically insulating layers formed on the conductive wiring, wherein the first insulating layer is formed on the conductive wiring in such a manner that the first insulating layer covers a portion of a peripheral part of one solder land and a central part of the one solder land is exposed, the portion of the peripheral part being situated on the side of another solder land, wherein the second insulating layer is piled up on the first insulating layer which covers the portion of the peripheral part of the one solder land.

Abstract: Through an improvement of module size increase due to mounting a single passive element on a substrate and an increase in the mounting cost, to provide a highly reliable, high performance and small sized electronic circuit component which permits to integrate a variety of electronic parts such as capacitors, inductors and resistors in a high density with low cost. The electronic circuit component comprises an insulator substrate, a plurality of electrodes having different areas provided on the insulator substrate, one or more elements selected from a capacitor element of dielectric material sandwiched between the electrodes, an inductor element and resistor element, a metal wiring connecting the elements, a metal terminal part of a part of the metal wiring and an organic insulator material covering the elements and the circumference of the metal wiring portion excluding the metal terminal portion.

Abstract: Disclosed is a PCB including an embedded passive component and a method of fabricating the same. The PCB includes at least two circuit layers in which circuit patterns are formed. At least one insulating layer is interposed between the circuit layers. A pair of terminals is vertically formed through the insulating layers, plated with a first conductive material, and separated from each other by a predetermined distance. The embedded passive component is interposed between the terminals and has electrodes formed on both sides thereof. The electrodes are separated from the terminals by a predetermined distance and electrically connected to the terminals through a second conductive material.

Abstract: A power shunt for use within a semiconductor device of a type having a motherboard and an integrated circuit package electrically coupled to the motherboard and of a type having a spaced portion located between the motherboard and the package. The power shunt comprises a capacitor within the spaced portion between the motherboard and the package of the semiconductor device. The capacitor includes a conductive layer of a first type, a conductive layer of a second type, and a dielectric layer that electrically isolates the first type conductive layer from the second type conductive layer, wherein said first type conductive layer and second type conductive layer form a conductive bridge between the motherboard and the package. The arrangement of the capacitor fulfills the dual function of providing decoupling capacitance with the capability of supplying an additional path of current between the motherboard and package to the die load.

Abstract: A printed board is mounted with a chip-type solid electrolytic capacitor of a four-terminal structure where a pair of positive electrode terminals are disposed at opposite positions and a pair of negative electrode terminals are disposed at opposite positions on a mounting surface. The printed board has a pair of positive electrode patterns and a pair of negative electrode patterns to which the positive electrode terminals and negative electrode terminals of the chip-type solid electrolytic capacitor are connected, respectively. The printed board further has an inductor section that is insulated from the negative electrode patterns, and electrically connects the positive electrode patterns.

Abstract: A chip embedded packaging structure includes a first metal board, a second metal board having at least a through cavity, in which the second metal board is disposed on the upper surface of the first metal board to form a heat dissipating substrate, at least a semiconductor chip and a capacitor chip embedded in the first metal board and embraced in the through cavity of the second metal board, a passive component layer disposed on part of the upper surface of the second metal board, and at least a build-up circuit layer covering the semiconductor chip, the capacitor chip, and the passive component layer and electrically connecting them through a plurality of conductive vias.

Abstract: The invention achieves stable performance, such as low parasitic capacitance generated at conductive components. Components having a low dielectric constant of 4 or less are disposed on a base member. Functional films partitioned by the low-dielectric-constant components are also provided.

Abstract: A wiring board includes a plurality of via pads disposed on a ceramic sub-core accommodated in a core board. A Cu-plated layer is formed on the surface of a conductor pad and serves as a processed face, i.e., a face to which Cu surface chemical processing is applied in order to improve the adhesion between the surface of the Cu-plated layer and that of an adjacent polymer material. The lowermost dielectric layer of a laminated wiring portion, and a via conductor formed in the dielectric layer, are in electrical contact with the processed face.

Abstract: An adjustable-inductance (AI) filter, a tape distribution substrate including the filter, and a display panel assembly including the tape distribution substrate are provided. The adjustable-inductance (AI) filter includes a filter distribution line including first and second end portions each having a first line width, at least one repair pattern having a second line width and disposed between the first and second end portions, and at least one unit filter bank connected in parallel to the at least one repair pattern, respectively.

Abstract: A semiconductor package is disclosed for an integrated circuit die (52). The integrated circuit die is electrically connected to the package substrate by either die solder balls (53a), or wirebonds (53b). The package substrate (50), a single sided printed wiring board, has a thick metal core (100), consisting of a base metal, a core capacitor, and one or more thin build up layers.

Abstract: A multilayered printed circuit board includes a first surface layer that includes a semiconductor integrated circuit, a second surface layer that includes a bypass capacitor and that is opposite to the first surface layer, a main power supply wiring layer, and a ground layer between the first and second surface layers. In the multilayered printed circuit board, one terminal of the bypass capacitor is connected to a midpoint of a wiring path from the main power supply wiring layer to a power supply terminal of the semiconductor integrated circuit, and an impedance of a first wiring path from the main power supply wiring layer to the terminal of the bypass capacitor is higher than an impedance of a second wiring path from the terminal of the bypass capacitor to the power supply terminal of the semiconductor integrated circuit.

Abstract: Shaped integrated passive devices and corresponding methodologies relate to construction and mounting of shaped passive devices on substrates so as to provide both mechanical and electrical connection. Certain components and component assemblies are associated with the implementation of surface mountable devices. Specially shaped integrated passive device are capable of providing simplified mounting on and simultaneous connection to selected electrical pathways on a printed circuit board or other mounting substrate. Shaped, plated side filter devices have plated sides which provide both mounting and grounding/power coupling functions. Thin film filters may be constructed on silicon wafers, which are then diced from the top surface with an angular dicing saw to produce a shaped groove in the top surface. The groove may be v-shaped or other shape, and is then plated with a conductive material. Individual pieces are separated by grinding the back surface of the wafer down to where the grooves are intercepted.

Abstract: A capacitor device is provided which includes a plurality of electric double-layer capacitors connected in series, and a balance resistor portion where five resistors having an equivalent resistance are connected in parallel. In this capacitor device, the balance resistor portion is connected to each electric double-layer capacitor, so that the electric double-layer capacitors connected in series can be charged uniformly.

Abstract: A process for fabricating a circuit board with embedded passive component is provided. A conductive layer including a first surface and a second surface opposing to the first surface is provided. The conductive layer has first through holes passing through the conductive layer, respectively. At least one passive component material layer is formed on the first surface. A circuit unit including second through holes is provided. Locations of the second through holes are corresponding to the locations of the first through holes, respectively. The conductive layer and the circuit unit are aligned by the first through holes and the second through holes, while the first surface of the conductive layer faces the circuit unit, and the passive component material layer is between the circuit unit and the conductive layer. The conductive layer is laminated to the circuit unit. The conductive layer is patterning to form a circuit layer.

Abstract: A memory module includes a memory chip MC1 disposed at a position opposite to a memory buffer via a module substrate, a memory chip MC3 disposed at a position not opposite to the memory buffer via the module substrate, and a memory chip MC11 disposed at a position opposite to the memory chip MC3 via the module substrate. A branch point at which a wiring part connected to the memory chip MC1 and a wiring part connected to the memory chips MC3 and MC11 are branched is positioned at the memory buffer side from the viewpoint of the intermediate point between the planar mounting position of the memory buffer and the planar mounting position of the memory chips MC3 and MC11. Accordingly, the wiring length of the wiring part can be made sufficiently short.