Abstract: A LED packaging process is to place LED chips at predetermined positions on the printed circuit board substrate, followed by drilling holes to penetrate the substrate, followed by passing the printed circuit board through the solder furnace to completely fill the through-hole position with solder points, followed by using molds to make the soldering points into a groove reflector, followed by placing LED chips in the groove reflector, followed by wire bonding and using encapsulation resin for packaging to form SMD LED with reflectors. In the present invention, the filling with metal conductor in electrode through holes on the printed circuit board to form the groove reflector can enhance the heat dissipation of LED and the brightness of LED, which has the advantageous effects that traditional SMD LED can not have.

Abstract: An interposer adapted to be used between a mounting board and a semiconductor chip which is to be mounted on the mounting board. The interposer comprises: a heat-resistant insulator having first and second surfaces, the insulator being provided with a plurality of through-holes opened at the first and second surfaces; wiring patterns formed on the first and second surfaces of the insulator electrically connected to each other by means of a conductor provided on an inner wall of at least one of the through-holes; and a capacitor. The capacitor comprises: a first electrode formed on the insulator and having a connecting portion formed on an inner wall of at least one of the other through-holes; a dielectric layer formed on the first electrode; and a second electrode formed on the dielectric layer.

Abstract: A compact printed board assembly has a patterned copper-coated substrate (1) with electronic components (5, 12) mounted thereon. Depending on the height of the components, either SBU lacquer (11) or non-flow prepreg (3) and laminate (4) surround the electronic components. This subassembly is then sandwiched between two RC (resin coated) copper foils (8) with the resin (7) facing the components (5, 12) and burying them, thereby providing a new etchable copper surface which can be connected by means of microvias (10) to the embedded components (5, 12).

Abstract: A resistive element, a circuit board, and a circuit package, as well as a method of adding a resistive element to a circuit board are described. The resistive element includes a first contact point connected to a capacitor terminal, a second contact point connected to a circuit board plane, and resistive material connected to the first and second contact points. The invention may also include a circuit board with one or more resistive elements, as well as a circuit package, such as an integrated circuit or a discrete bypass capacitor, including one or more resistive elements, applied to an outside surface. The value of resistance for the resistive element can be selected by design to have a predetermined relationship with the equivalent resistance of an associated circuit board and connecting circuitry.

Abstract: A Method and system of routing noise current from noise generating devices in an electronic or electrical system is disclosed. The method and system includes dielectric structures that route noise current from noise generating devices back to the noise generating device in which the noise originates by way of a return path. The dielectric structures provide for the return paths.

Abstract: Printed circuit board 1 on which LSI2 is mounted comprises first capacitors 4a and 4b for electrically connecting power source terminals 3a and 3b to via holes 8b, first power source wiring 5a, second power source wiring 6a and a second capacitor 7a. In a predetermined frequency range, the characteristic impedances in power source wirings 5a and 6a are set to three times or more higher than the impedances in capacitors 4a, 4b and 7a. In addition, the lengths of power source wirings 5a and 6a are set to equal to or larger than a value obtained by multiplying 20 mm by the wavelength reduction rate of the printed circuit board and equal to or smaller than a value obtained by multiplying one quarter the wavelength at the upper limit frequency in the predetermined frequency range by the wavelength reduction rate.

Abstract: An encapsulation material for use within a microelectronic device includes a polymeric base resin that is filled with a fibrous reinforcement material. The fiber reinforcement of the encapsulation material provides an enhanced level of crack resistance within a microelectronic device to improve the reliability of the device. In one embodiment, a fiber reinforced encapsulation material is used to fix a microelectronic die within a package core to form a die/core assembly upon which one or more metallization layers can be built. By reducing or eliminating the likelihood of cracks within the encapsulation material of the die/core assembly, the possibility of electrical failure within the microelectronic device (e.g., within the build up metallization layers) is also reduced.

Abstract: An apparatus includes a connection sheet having a separator layer and an adhesive film layer formed on the separator layer such that said adhesive film layer can be peeled from the separator layer. The cohesive strength of the adhesive film layer decreases when the adhesive film layer is heated to a predetermined temperature. Electronic parts each have an electrode surface and at least one electrode on the electrode surface.

Abstract: There is provided a composite wiring board that occupies a small space and is low in price and a manufacturing method thereof; the composite wiring board comprises at least two rigid wiring boards on end faces of which connection portions are formed, in which each of the rigid wiring boards is arranged so that each of the connection portions is situated on a plane and each of corresponding connection portions is connected with each other in the plane.

Abstract: In a thermomechanical process for planarizing a resist layer applied to a partly elevated carrier area, a resist structure, in particular an encapsulation for electronic components, is obtained. In this case, a dry resist sheet, formed of a composite of a temperature-resistant protective sheet and a photosensitive layer, is applied by its photosensitive layer to a surface of the carrier and the dry resist sheet is planarized under pressure and with heat. After which the photosensitive layer is exposed, and the protective sheet is removed and the photosensitive layer is developed.

Abstract: An electronic device comprising a semiconductor chip which is fixed to the mounting face of a wiring board through an adhesive and in which external terminals are electrically connected with electrode pads of the wiring board through bump electrodes. Recesses are formed in the electrode pads, and in the recesses the electrode pads and the bump electrodes are connected. The electrode pads are formed over the surface of a soft layer, and the recesses are formed by elastic deformation of the electrode pads and the soft layer.

Abstract: A chip type electronic component and a method of manufacturing the same reduces the steps necessary for applying an electrically conductive paste to define a first external electrode, a second external electrode and a third external electrode on the outer surface of an electronic component main body. External electrodes are provided around the side surfaces of the main body of the electronic component. The first external electrode is positioned on the first end surface of the main body, the second external electrode is positioned on the second end surface, the third external electrode is positioned between the first and second external electrodes. The first and second external electrodes are arranged to extend to edge portions of the first and second end surfaces, but exposing at least the approximate central portions of these end surfaces. In this way, the external electrodes are formed by applying the electrically conductive paste on the side surfaces of the main body.

Abstract: A method and apparatus interconnecting multiple devices on a circuit board. One disclosed circuit board has a first attach region on a first surface for coupling a first set of pins from a first device to a set of signal lines. A second attach region on a second surface is for coupling a second set of pins from a second device to the set of signal lines. The second attach region is predominantly non-overlapping with respect to the first attach region.

Abstract: A card has an electronic device, such as an integrated circuit, a conductive, resistive or capacitive network, or other electronic device, embedded therein. The card, sometimes referred to as a “smart card,” has the electronic device mounted to a substrate, generally by electrical connections formed of solder, electrically-conductive adhesive or flexible electrically-conductive adhesive. The substrate is covered by a layer of melt-flowable adhesive of thickness sufficient to cover the electronic device mounted thereon. The substrate is attached to a card blank to which it is bonded by melt flowing the melt-flowable adhesive. In one embodiment, the card blank has a cavity into which the electronic device and substrate are placed. In another embodiment, the substrate is of the same size and shape as is the card blank and the space therebetween is filled with melt flowable adhesive to bond them together and embed the electronic device therebetween.

Abstract: The invention relates to an electronically detectable resonance label, in particular an RFID label, with a substrate made of plastic foil and with conductive surfaces on the front and rear of the substrate, with some of the conductive surfaces forming a capacitor in a mutual area of overlap, comprising a first capacitor plate on the front of the substrate and a second capacitor plate on the rear of the substrate. The capacitor plates are in the shape of elongated strips of uniform width along their entire length; with said strips overlapping only partially. The area of overlap is arranged at a distance from both ends of at least one capacitor plate. This provides the advantage that during the production process relative displacement of the capacitor plates can take place in two directions.

Abstract: A circuit structure combines an integrated circuit with a passive circuit element formed within a grid-array substrate. Formation of the circuit structure includes forming a passive circuit element within one or more conductive layers of a grid-array substrate such as may be used for packaging of integrated circuits. A pair of terminals of the passive circuit element is coupled to a pair of passive element contact pads within a processed surface of the integrated circuit, thereby connecting the integrated circuit to the grid-array substrate. The same grid-array substrate may be used for formation of the passive circuit element and for packaging of the integrated circuit. In some embodiments the lateral extent of the integrated circuit overlaps the lateral extent of the passive circuit element. Alternatively, the passive circuit element may be laterally displaced from the integrated circuit.

Abstract: A thin electrical circuitry structure is formed which contains conductive circuitry traces, integral capacitors and integral resistors. A first laminate structure comprises a conductive foil having a layer of embeddable dielectric material laminated thereto. A second laminate structure comprises a conductive foil having a layer of resistive material on one side, the thickness of the resistive material layer being less than that of the layer of embeddable dielectric material. The resistive material layer is circuitized to produce resistive patches, and the two structures are laminated together, embedding the resistive patches in the dielectric material layer. One of the foils is circuitized providing circuitry traces, optional inductor coils, and capacitor plates. That foil embedded in dielectric laminate to support the structure for further processing. The other foil is then circuitized providing circuitry traces, optional inductor coils and capacitor plates.

Abstract: A printed circuit board includes a first component mounted on a first side of the printed circuit board. A second component has an identical pin-out as the first component. The second component is mounted on a second side of the printed circuit board. A first signal line connects a first landpad coupled to a first contact on the first component with a second landpad coupled to a corresponding first contact on the second component. A second signal line connects a third landpad coupled to a second contact on the first component with a fourth land pad coupled to a corresponding second contact on the second component. The first signal line has is equal in length to the second signal line.

Abstract: A process is given for permitting the application to a substrate (2) of a microsystem or transducer (1) having a first partial surface (13), whose interaction with the environment is to be possible, and a second partial surface (14), which is to be protected against external influences. The substrate (2) is prepared, a passage point (20) being produced in said substrate (2). The microsystem (1) and substrate (2) are so mutually positioned that the first partial surface (13) faces the substrate (2) and that the passage point (20) in the substrate (2) and the first partial surface (13) come to rest opposite one another. Contacts (50, 51.1, 51.2) are produced by flip-chip technology. A sealing contact (51.1, 51.2) seals the second partial surface (14) against external influences. A gap (3) between the microsystem (1) and substrate (2) is filled with a filling material (30). A selective cover (24) over the passage point (20) keeps undesired external influences away from the first partial surface (13).

Abstract: The present invention is a method of providing a protective covering on an electronic package including a first circuitized substrate, a semiconductor chip positioned on and electrically coupled to the first substrate, and a plurality of conductors also on the substrate for electrically connecting the substrate to an external circuitized substrate. In one version, the method comprises covering substantially all of the external surfaces of the substrate, the semiconductor chip and a portion of the plurality of conductors with a protective covering from immersion in a dielectric solution (e.g., TEFLON AF). The coatings can also be applied by brushing, spraying, or chemical vapor deposition. In an alternative embodiment, all of the external surfaces, including all of the conductors, are coated with the protective covering (e.g., to facilitate package shipment or other handling). The resulting electronic packages are also described herein.

Abstract: A memory module includes a plurality of semiconductor memory devices mounted on a printed wiring board (PWB); longitudinal contact terminals that are for connection to a computer mother board and are arranged along at least one longitudinal edge of the PWB; and transverse contact terminals that are for connection to the computer mother board and are arranged along at least one transverse edge of the PWB. A socket for the module includes at least one longitudinal part into which the longitudinal contact terminals are inserted and at least one transverse part into which the transverse contact terminals are inserted. Each transverse socket part can be mounted on a pivot attached to the longitudinal part and rotated to engage a PWB inserted in the longitudinal part. Alternatively, each transverse part can be a flexible circuit carrier.

Abstract: The invention relates to a power module with a circuit arrangement provided with active semiconductor components and passive components and with a circuit substrate, whereby at least a portion of the active semiconductor components are soldered onto a DCB substrate and at least a portion of the passive components are printed in thick film technology on at least one ceramic substrate. The upper side of the DCB substrate is structured to form track conductors and connecting surfaces for receiving the active semiconductor components and passive components of the circuit arrangement. On the ceramic substrate, for each passive component, a first print layer is printed in thick film technology and at least one contact surface as additional print layer laterally adjoining the first print layer.

Abstract: This invention discloses a wafer level packaging method and configuration. This improved wafer level package includes a processed wafer mounted on a first printed circuit board (PCB) carrier. The processed wafer mounted on the PCB carrier board includes a plurality of separated integrated circuit (IC) chips divided by scribe-line gaps wherein each of these scribe-line gaps is filled with flexible gap-filling insulation material. In another preferred embodiment, the wafer-level package further includes a second PCB carried board composed of same material as the first PCB carrier board mounted on top of the wafer. In another preferred embodiment, the wafer-level package, which having the first and the second PCB carrier boards further includes a plurality of connection via penetrating through the first and the second PCB carried board for forming electric connection to the IC chips separated by the scribe-line gaps.

Abstract: A device that reduces the interfacial stress caused by differential thermal expansion in an IC/PC board assembly can be created by attaching an annular part, that has a higher coefficient of thermal expansion, to the IC at an elevated temperature. When the assembly cools the annular part contracts and compresses the IC, increasing the change in size of the IC and reducing the stress in the IC/PC joint.

Abstract: A wiring substrate with reduced thermal expansion. A wiring substrate, such as a laminated PWB, thin film circuit, lead frame, or chip carrier accepts an integrated circuit, such as a die, a flip chip, or a BGA package. The wiring substrate has a thermal expansion reduction insert in a thermal expansion stress region where the integrated circuit is mounted. The thermal expansion reduction insert may extend a selected distance from the edge or edges of the integrated circuit attachment area, or stop a selected distance from the edge or edges of the integrated circuit attachment area, or be essentially equal to the integrated circuit attachment area. The thermal expansion reduction insert reduces the thermal expansion of the wiring substrate in the region that is joined to the integrated circuit, thus reducing thermal stress between components of the wiring substrate-integrated circuit assembly.

Abstract: The invention relates to a resonant tag including an insulating thin film and coiled circuits made of a metal foil respectively formed on both sides of the insulating thin film. The coiled circuits are formed in an electrically connected relation to each other with a space at the center of the insulating thin film. Said both coils are almost superimposed on each other to form a capacitor, thereby constituting an LC circuit. The area of a portion of each side of the thin film, said portion being surrounded by the innermost peripheries of both coils and having no metal foil on both sides, is controlled to at least 16% based on the whole area of said one side of the tag, whereby a resonant tag having an area of at most 700 mm2 can be obtained.

Abstract: In the present invention, a thin film capacitor, having a dielectric layer of a metal oxide having perovskite crystal structure, is formed on a first substrate before the capacitor is transferred onto a second substrate on which an electronic circuit has been formed. Thereafter, patterning of the capacitor and electrical connection are to be carried out.

Abstract: An improved robber or solder thieving pad, parallelogram shaped, significantly reduces solder bridging in wave soldered multi leaded through hole or surface mounted components in a printed circuit board for different wave settings. The component leads are either parallel or perpendicular to the solder wave during the soldering process. In one embodiment, the parallelogram shaped solder thieving pad is disposed contiguous or adjacent to the through hole. In another embodiment, the parallelogram shaped solder thieving pad is spaced from a thin annular ring surrounding the through-hole. In still another embodiment, the pad may be linked to the ring by a thin connecting bridge. Dimensions of the solder thieving pad vary according to the component lead size, spacing, and number of rows.

Abstract: The invention describes a module provided with a thin-film circuit. To realize the module with thin-film circuit, capacitors, or capacitors and resistors, or capacitors, resistors and inductors are provided next to the conductor tracks directly on a substrate (1) of an insulating material. The partial or full integration of passive elements leads to the creation of a module which requires little space.

Abstract: A semiconductor package is present along with an associated method. The package comprises a substrate with a top surface and a bottom surface, the substrate having a plurality of electrically conductive vias extending from the top surface of the substrate to the bottom surface of the substrate. A semiconductor device having an active surface, the active surface having a plurality of bonding pads, is attached to the substrate by an adhesive that bas holes that align with the vias. The vias are also aligned with the bonding pads. Solder serves to electrically and mechanically couple each of the bonding pads with a corresponding via. Each of the vias, in turn, is coupled to a solder ball formed on the bottom of the substrate.

Abstract: A flexible substrate strip comprises a plurality of substrate units adapted for mounting semiconductor chips. The surface of the flexible substrate strip is provided with a plurality of degating regions at locations such that the edges of mold runners and gates of a mold used to encapsulate the semiconductor chips in encapsulant material fit entirely within the degating regions when the substrate strip is placed in the mold during encapsulation of the semiconductor chips. The present invention is characterized in that each degating region has a buffer region at a location corresponding to the gate of the mold during encapsulation. The degating regions have a degating region material formed thereon with the buffer regions not coated with the degating region material. The adhesive force between the encapsulant material and the degating region material is less than the adhesive force between the encapsulant material and the substrate.

Abstract: A device for solving the electrical, physical, architectural and thermal challenges associated with designing a computer system is disclosed. A memory controller chipset having two or more chips mounted on opposite sides of a system planar helps balance the thermal profile of the system and achieve the strict spacing requirements of advanced computer processors relative to the memory controller chipset. Although the chips are staggered on opposite sides of the system planar, the adjacent edges of the chips substantially align with one another to minimize their separation.

Abstract: In the production radio frequency (RF) sensable objects, it is possible to produce a package, envelope, or like container which has enhanced read distance, producable by a simple method. Large areas are printed on the envelope or package in conductive ink which are separated by a non-conductive portion of the package or envelope and function as an RF antenna. Then by placing an otherwise conventional label with an RFID chip associated with it so that it bridges the conductive ink portions of the RF antenna, a much easier to sense or read product is produced. The conductive ink can be applied in a pattern, logo, and letters or character indicia. The label may have conductive pressure sensitive adhesive on one face, which actually connects the antenna sections to the RFID chip to form the operable structure that can be sensed by an RF receiver at a distance of three meters or more.

Abstract: A chip-sized semiconductor device includes a semiconductor element having a plurality of electrodes and a plurality of connecting pads electrically connected to the respective electrodes. A connecting board includes a base substrate having a first surface and a second surface, a plurality of connecting holes extending from the first surface to the second surface, a plurality of lands formed on the first surface to close the respective connecting holes, the lands being arranged in conformity with positions of the connecting pads of the semiconductor element, each of the connecting pads having a surface area smaller than that of the land. The semiconductor element is mounted on the connecting board in such a manner that the connecting pads of the semiconductor element are electrically connected to the respective lands of the connecting board by means of a plurality of bumps, respectively.

Abstract: The invention relates to a module provided with a thin-film circuit which comprises an integrated trimmable capacitor. At least one electrically conducting layer (2, 4) of the capacitor has a structured surface with recesses. This finger-type design has the result that the actual capacitor is composed of several capacitors connected in parallel. After the total capacitance value has been determined, this total capacitance value can be fine tuned through a selective cutting-off of fingers, i.e. of capacitors, from the main surface of the electrically conducting layer (2, 4).

Abstract: A method and apparatus interconnecting multiple devices on a circuit board. One disclosed circuit board has a first attach region on a first surface for coupling a first set of pins from a first device to a set of signal lines. A second attach region on a second surface is for coupling a second set of pins from a second device to the set of signal lines. The second attach region is predominantly non-overlapping with respect to the first attach region.

Abstract: Disclosed are a printed circuit board and a method for wiring signal lines on the same. Connecting lines for electrically connecting chip select pins of a semiconductor chip, no connect pins and address designate pins, are formed on a PCB. In case of an unstack type, a pad is connected to chip select pin and no connect functioning pin of other semiconductor chip via a first signal line. In case of a stack type, another pad used with a pad is connected to a no connect functioning pin and a chip select pin of the corresponding semiconductor chip having no connection with the first signal line via a second signal line. According to the type of semiconductor chip, e.g. unstack or stack type, a second connecting pad selectively connecting by a first jumper having almost zero resistance value, is disposed between the first and the second signal lines. A first connecting pad is also disposed at the second signal line, the first pad is selectively connected by a second jumper having zero resistance value.

Abstract: A process for forming a thick-film resistor whose dimensions can be accurately obtained, thereby yielding a precise resistance value. The method includes providing on a substrate a photoimageable layer that preferably forms a permanent dielectric layer of a multilayer structure. An opening is photodefined in the surface of the photoimageable layer, and then overfilled with an electrically-resistive material to form a resistive mass having an excess portion that lies on the surface of the photoimageable layer surrounding the opening. Following curing which causes the surface of the resistive material to become recessed below the surface of the photoimageable layer, the excess portion of the resistive mass is removed, preferably by abrading or a similar operation, such that the lateral dimensions of the resistive mass are determined by the lateral dimensions of the opening in the photoimageable layer.

Abstract: A substrate 15 has an electrically adjustable trim pad 50 on the bottom side. A circuit pattern 18 resides on the top side, covered by an RF shield 20. The trim pad is located on the bottom side directly below the RF shield, and is electrically connected 52 to the circuit pattern. A number of surface mount connections 30, typically C5 solder bumps, are located on the bottom side, and surround the trim pad. The trim pad is trimmed after the RF shield is attached, thus providing more accurate tuning of the circuit on the top side.

Abstract: An electronic control unit having a housing, a substrate, particularly a hybrid, arranged in the housing and having an electronic control circuit. The electronic control unit also includes at least one device plug secured to the housing having contact elements that are electrically conductively connected to the control circuit of the substrate. A second substrate is arranged in the housing, spatially separated from the first substrate. At least one power component disposed in the housing and, electrically connected to the control circuit on the first substrate. One connecting printed circuit trace disposed in housing and conductively connected to the power component. The connecting printed circuit trace are conductively connected to a contact element, conducting power currents, of the device plug. Using the arrangement, in the event of a large number of contact elements in a device plug, the electrical connecting of the contact elements to the substrate can be simplified.

Abstract: The present invention relates generally to a new method and apparatus to enable high yielding double sided and/or multipass screening in the manufacture of multilayer ceramic packages. Also, the present invention enables the screened features to be buried partially or fully with flat surface being available for high yielding post-sinter operations.

Abstract: In a printed circuit board, electronic components such as a component having a pair of leading portions, a chip component having a pair of electrodes, and the like, are connected to circuit patterns; and a resist layer covering a copper foil portion formed as a ground pattern is removed in vicinity of the high-impedance side leading portion of the current leading component and the high-impedance side electrode of the chip component to thereby form removed portions so that discharge paths are formed between the copper foil portion exposed through the removed portions and the leading portion and the electrode.

Abstract: In a multilayer printed circuit board having at least two conductive layers, including a power-supply layer with a plurality of power-supply planes having different supply voltages and a ground layer, a circuit pattern for transmitting a signal serving as a radiation noise source is formed on a conductive layer facing the ground layer in order to suppress generation of radiation noise.

Abstract: A multi-element module is constituted by a substrate having thereon a plurality of first electrodes, a plurality of electrical elements each having at least one second electrode and disposed so that its second electrode is aligned with a first electrode in an opposed relationship, and an adhesive member disposed between the substrate and the plurality of electrical elements to ensure electrical connection between the first electrodes and the second electrodes. The adhesive member comprises an adhesive layer contacting and bonding the electrical elements to the substrate, and an anisotropic conductive layer comprising a resin and electroconductive particles dispersed in the resin. The anisotropic conductive film is disposed between the adhesive layer and the substrate so as to insulate adjacent electrodes from each other while electrically connects the first and second electrodes, even when the electrical elements having second electrodes different in thickness.

Abstract: A method and apparatus is provided for electrically and mechanically interconnecting electronic circuit assemblies or electronic modules. An integrated circuit (300) includes a plurality of leads (302) extending from a surface (305), each of the leads (302) having a seating portion (403) and a stem portion (402). A printed circuit board (400) includes a plurality of plated through holes (401) therein corresponding to the plurality of leads (302) extending from the integrated circuit (300). The steps of the method include positioning the printed circuit board (400) so that a lower surface (404) of the printed circuit board (400) rests on the seating portion (403) of the leads (302) of the integrated circuit (300), and so that the stem portion (302) of each of the leads are positioned within the corresponding plated through holes (401) in the printed circuit board (400).

Abstract: In an integrated circuit, the conducting paths electrically coupling the electronic components can be fabricated to conform to conflicting physical property requirements. After formation of the conducting paths, conducting material can be added to or removed from selected conducting paths. In this manner, the resistance or the capacitance of selected conducting paths can be enhanced relative to the non-selected conducting paths.

Abstract: A chip-on-flex package which includes at least one moisture barrier layer to prevent metal corrosion and delamination of flex component layers. An exemplary microelectronic package includes a microelectronic die having an active surface and at least one side, wherein the microelectronic die active surface includes at least one contact. A flex component is attached by a first surface to the microelectronic die active surface. At least one conductive trace is disposed on a second surface of the flex component and extends through the flex component to contact at least one of the contacts. An encapsulation material is adjacent the microelectronic die side and a bottom surface of the flex component. A moisture barrier is disposed on the flex component and the conductive trace(s). A second moisture barrier may be disposed on the encapsulation material. A heat dissipation device may also be incorporated into the chip-on-flex package.

Abstract: A circuit body 10 includes a main circuit body 12 having an inner circuit; a plurality of connector blocks 13, 14 integrally supported by the main circuit body 12 and directly connected to electric parts; and flexible legs 21a, 21b, 21c, 21d for supporting the plurality of connector blocks 13, 14 independently from the main circuit body 12 so that they can be freely moved in the direction perpendicular to the connecting direction of the electric parts.

Abstract: An electronic assembly (10) comprises one or more electronic components (18) having solder terminations (20), and a printed circuit substrate (12) having printed circuit traces (14, 16), wherein at least one of the solder terminations of the one or more electronic components (18) and the printed circuit traces (14, 16) of the printed circuit substrate (12) has a secondary finish produced by application of an electrolessly deposited nickel film (26) containing phosphorus which is further plated with gold (28). An indium-tin-lead solder paste (22) is utilized in a soldering process to attached the one or more electronics components (18) to the printed circuit traces (14,16) on the printed circuit board (12), such that the indium-tin-lead solder (22) provides improved solder joint integrity with the secondary finish. The electronic components (18) include semiconductor devices such as ball grid arrays (1000) and flip-chip integrated circuits (1010).

Abstract: A method of and apparatus for identifying an item to or with which a radio frequency identification tag is attached or associated is provided. The tag is made of a nonconductive material to have a flat surface on which a plurality of circuits are pressed, stamped, etched or otherwise positioned. Each circuit has a capacitance and an inductance. The capacitance is formed from the capacitive value of a single capacitor. The inductance is formed from the inductive value of a single inductor coil having two conductive ends each connected to the capacitor. Each tag is associated with a binary number established from a pattern of binary ones and zeros which depend on the resonance or nonresonance of each circuit, respectively and the circuits position with respect to the binary table. The binary number may be converted to a decimal number using the binary table for conversion.