Abstract: The invention provides a wiring board with built-in capacitors, that has a multilayer wiring structure and capable of mounting an IC chip thereon. The wiring board with built-in capacitors includes: a first capacitor that is built into the multilayer wiring structure and formed so that an overlapping area between a first lower electrode and a first upper electrode provided on respective surfaces of a first dielectric layer is a predetermined area; and a second capacitor that is built into the multilayer wiring structure along the same plane as the first dielectric layer and formed so that an overlapping area between a second lower electrode and a second upper electrode provided on respective surfaces of a second dielectric layer with the same thickness as the first dielectric layer is different from the predetermined area.

Abstract: This invention relates to a capacitive/resistive device, which may be embedded within a layer of a printed wiring board. Embedding the device conserves board surface real estate, and reduces the number of solder connections, thereby increasing reliability. More specifically, the device, comprises a first metallic foil; a second metallic foil; a first electrode formed from the first metallic foil; a dielectric disposed over the first electrode, a resistor element formed on and adjacent to the dielectric; a conductive trace; and a second electrode formed from the second metallic foil and disposed over the dielectric and in electrical contact with the resistor element, wherein the dielectric is disposed between the first electrode and the second electrode and wherein said dielectric comprises an unfilled polymer of dielectric constant less than 4.0. This invention also relates to a method of making the device.

Abstract: The present invention provides a circuit board structure, the circuit board structure consisting of a carrier board having a first surface and an opposed second surface, the carrier board being formed with at least one through hole penetrating the first and second surfaces; a conductive pillar formed in the through hole by electroplating; and a first circuit layer and a second circuit layer respectively formed on the first and second surfaces of the carrier board, the first and second circuit layers being electrically connected to the two end portions of the conductive pillar, thereby reducing spacing between adjacent conductive pillars of the carrier board and achieving high density circuit layout.

Abstract: An R-C network formed on a substrate. The capacitor includes a metal member with anodized and unanodized layers. The unanodized layer functions as one of the capacitor's electrodes. The anodized layer functions as the capacitor's dielectric layer. The resistor is formed from material on the same side of the substrate as the capacitor. In some versions of the invention, the resistor is formed on top of a substrate dielectric layer. In these versions of the invention, a conductor both functions as one of the capacitor's electrodes and connects the resistor to the capacitor. In alternative versions of the invention, the resistor is formed from a film that disposed on the undersurface a metal foil. The foil functions as the resistor to capacitor conductor. Sections of the foil that are removed expose and define the resistor. Solder balls or other connectors on the substrate surface connect the network to another component.

Abstract: Provided are active balancing modules that control voltage imbalances between capacitors stacked in a series arrangement and methods for their manufacture. These modules are simple and inexpensive to manufacture, and versatile. They may be used alone or they may be combined together to form a multi-module active balancing circuitry for a plurality of capacitors stacked in a series arrangement. The modules may further be aligned in either a side-by-side topology or an overlapping topology.

Abstract: A chip capacitor 20 is provided in a core substrate 30 of a printed circuit board 10. This makes it possible to shorten a distance between an IC chip 90 and the chip capacitor 20 and to reduce loop inductance. Since the core substrate 30 is constituted by providing a first resin substrate 30a, a second resin substrate 30b and a third resin substrate 30c in a multilayer manner, the core substrate 30 can obtain sufficient strength.

Abstract: To reduce switching noise, the power supply terminals of an integrated circuit die are coupled to the respective terminals of at least one capacitor embedded in an interposer that lies between the die and a substrate. In an embodiment, the interposer is a multilayer ceramic structure that couples power and signal conductors on the die to corresponding conductors on the substrate. The capacitor is formed of at least one high permittivity layer and in an embodiment comprises several high permittivity layers interleaved with conductive layers. Alternatively, the capacitor can comprise at least one embedded discrete capacitor. Also described are an electronic system, a data processing system, and various methods of manufacture.

Abstract: The invention provides a wiring board with built-in capacitors, that has a multilayer wiring structure and capable of mounting an IC chip thereon. The wiring board with built-in capacitors includes: a first capacitor that is built into the multilayer wiring structure and formed so that an overlapping area between a first lower electrode and a first upper electrode provided on respective surfaces of a first dielectric layer is a predetermined area; and a second capacitor that is built into the multilayer wiring structure along the same plane as the first dielectric layer and formed so that an overlapping area between a second lower electrode and a second upper electrode provided on respective surfaces of a second dielectric layer with the same thickness as the first dielectric layer is different from the predetermined area.

Abstract: A system and method for the fabrication of high reliability capacitors (1011), inductors (1012), and multi-layer interconnects (1013) (including resistors (1014)) on various thin film hybrid substrate surfaces (0501) is disclosed. The disclosed method first employs a thin metal layer (0502) deposited and patterned on the substrate (0501). This thin patterned layer (0502) is used to provide both lower electrodes for capacitor structures (0603) and interconnects (0604) between upper electrode components. Next, a dielectric layer (0705) is deposited over the thin patterned layer (0502) and the dielectric layer (0705) is patterned to open contact holes (0806) to the thin patterned layer. The upper electrode layers (0907, 0908, 1009, 1010) are then deposited and patterned on top of the dielectric (0705).

Abstract: A power shunt for use within a semiconductor device of a type having a motherboard and an integrated circuit package electrically coupled to the motherboard and of a type having a spaced portion located between the motherboard and the package. The power shunt comprises a capacitor within the spaced portion between the motherboard and the package of the semiconductor device. The capacitor includes a conductive layer of a first type, a conductive layer of a second type, and a dielectric layer that electrically isolates the first type conductive layer from the second type conductive layer, wherein said first type conductive layer and second type conductive layer form a conductive bridge between the motherboard and the package. The arrangement of the capacitor fulfills the dual function of providing decoupling capacitance with the capability of supplying an additional path of current between the motherboard and package to the die load 16.

Abstract: More compact, thinner, shorter and lighter surface-mounted electronic component modules and their manufacturing methods at low costs, thus making them industrially highly valuable are available. Such the component includes a wiring substrate having wiring patterns formed on one side and external connection terminals formed on the other side, the wiring patterns and the external connection terminals being connected with each other by via holes or through holes; a plurality of electronic component devices mounted on the one side of the wiring substrate; and an exterior resin layer formed on the wiring substrate which covers the plurality of electronic component devices, wherein at least one of the plurality of electronic component devices is fastened face up to the one side of the wiring substrate, the connection terminal of the electronic component device fastened face up and the wiring pattern or the connection terminal of another electronic component device being connected with each other by wire.

Abstract: Chip capacitors 20 are provided in a printed circuit board 10. In this manner, the distance between an IC chip 90 and each chip capacitor 20 is shortened, and the loop inductance is reduced. In addition, the chip capacitors 20 are accommodated in a core substrate 30 having a large thickness. Therefore, the thickness of the printed circuit board does not become large.

Abstract: A semiconductor wafer includes a redistribution layer which is electrically connected with a pad which is an end portion of an interconnect, a first resin layer which is formed over the redistribution layer, a second resin layer which is formed over the first resin layer and covers the side surface of the first resin layer, and an external terminal which is formed to be electrically connected with the redistribution layer in a manner to avoid the pad.

Abstract: A multilayer substrate assembly (80) includes at least one embedded component (52) within a plurality of stacked pre-processed substrates. Each pre-processed substrate can have a core dielectric (14), patterned conductive surfaces (12 and 16) on opposing sides of the core dielectric, and at least one hole (18) in each of at least two adjacently stacked pre-processed substrates such that at least two holes are substantially aligned on top of each other forming a single hole (19). The assembly further includes a processed adhesive layer (48) between top and bottom surfaces of respective pre-processed substrates. The embedded component is placed in the single hole and forms a gap (67 & 66) between the embedded component and a peripheral wall of the single hole. When the assembly is biased, the processed adhesive layer fills the gap to form the assembly having the embedded component cross-secting the plurality of pre-processed substrates.

Abstract: A multilayer printed circuit board with a built-in capacitor includes a plurality of resin films, each of which is made of thermoplastic resin and has a plurality of via-holes at predetermined positions, a plurality of conductive patterns, which are located on the resin films, and a plurality of conductive pattern interconnecting members, which are located in the via-holes to electrically interconnect the conductive patterns that are electrically separated by the resin films. Two of the conductive patterns are respectively located on two surfaces, which are opposite to each other, of one of the resin films while overlapping. The two of the conductive patterns and the one of the resin films make up a capacitor.

Abstract: A de-coupling capacitor module using dummy conductive elements in an integrated circuit is disclosed. The de-coupling module comprises at least one circuit module having one or more active nodes, and at least one dummy conductive element unconnected to any active node, and separated from a high voltage conductor or a low voltage conductor by an insulation region to provide a de-coupling capacitance.

Abstract: A resistive element, a circuit board, and a circuit package, as well as a method of adding a resistive element to a circuit board are described. The resistive element includes a first contact point connected to a capacitor terminal, a second contact point connected to a circuit board plane, and resistive material connected to the first and second contact points. The invention may also include a circuit board with one or more resistive elements, as well as a circuit package, such as an integrated circuit or a discrete bypass capacitor, including one or more resistive elements, applied to an outside surface. The value of resistance for the resistive element can be selected by design to have a predetermined relationship with the equivalent resistance of an associated circuit board and connecting circuitry.

Abstract: A multilayer ceramic substrate with a cavity includes a multilayer composite member including a plurality of ceramic layers disposed one on another. A cavity is formed in the multilayer composite member such that an opening of the cavity is located in one principal surface of the multilayer composite member. A bottom-surface conductive film is disposed on the bottom surface of the cavity. A capacitor conductive film is disposed in the multilayer composite member such that the capacitor conductive film faces the bottom-surface conductive film via one of the ceramic layers, thereby forming a capacitor.

Abstract: A thin film circuit module constructed for serial coupling to circuit conductors at printed and transmission line circuits. In one form of equalizer construction, thin film circuit elements are deposited on a supporting substrate and wherein a capacitor plate is defined a circuit resistor. Two connector applications serially couple the equalizer modules to trace conductors of a motherboard connector block and to cylindrical core conductors of a coaxial connector. Other hybrid equalizer constructions provide modules constructed of thin film resistors and pick-and-placed capacitors mounted piggyback to an equalizer module substrate.

Abstract: An integrated library core for embedded passive components and a method for forming an electronic device on the library core are provided. An insulating core layer is formed with a plurality of openings penetrating therethrough and with electrically conductive layers on upper and lower surfaces thereof. The openings of the core layer are filled with materials for forming passive components such as resistors and capacitors. This thereby provides an integrated library core on which the electrically conductive layers of the core layer can be desirably patterned to electrically interconnect the passive components, and this library core can be electrically connected to an electronic device such as substrate or printed circuit board to enhance performances of electrical characteristics for the electronic device.

Abstract: A semiconductor wafer includes a redistribution layer which is electrically connected with a pad which is an end portion of an interconnect, a first resin layer which is formed over the redistribution layer, a second resin layer which is formed over the first resin layer and covers the side surface of the first resin layer, and an external terminal which is formed to be electrically connected with the redistribution layer in a manner to avoid the pad.

Abstract: A method of making a resonant frequency tag which resonates at a predetermined frequency. The method involves providing a first conductive pattern having an inductive element and a first land and a second conductive pattern having a second land and a third land which are joined together by a link. The second conductive pattern is overlaid the first conductive pattern such that the second land is positioned over the first land. The third land is in electrical communication with the inductive element of the first conductive pattern. The formed resonant frequency tag is energized to determine if the tag resonates at the predetermined frequency. If the tag resonates properly, the third land is electrically coupled to the inductive element. If it does not, the second conductive pattern is adjusted so that overlapping portions of the first and second lands are changed, altering the capacitance to adjust the resonant tag frequency.

Abstract: An electronic circuit device, includes: internal terminals; a board on which wirings to the internal terminals are formed; an electronic component that is mounted on the board and is connected with the internal terminals; and an encapsulation resin with which the electronic component and the internal terminals are encapsulated. A part of the wiring forms a ring-shaped portion, and the ring-shaped portion has a plurality of gaps by which the ring-shaped portion is divided into a plurality of discontinuous ring-constituting sections. The plurality of ring-constituting sections are connected to the respective internal terminals, and a coating region of the encapsulation resin is surrounded with the ring-shaped portion. The applied area of the encapsulation resin can be controlled to be constant without using a special element for controlling the flow of the encapsulation resin.

Abstract: A method of making a resonant frequency tag having a predetermined frequency comprises forming a first conductive pattern comprising an inductive element and a first land having a first end connected to an inductive element end, and a second end spaced a predetermined distance from the first end; separately forming a second conductive pattern comprising a second land having a predetermined width and a link element; placing the second conductive pattern proximate the first conductive pattern at a first location wherein the second land overlies a portion of the first land with a dielectric therebetween establishing capacitive element plates having a first capacitance along with the inductive element forming a resonant circuit; measuring the resonant circuit frequency and comparing the measured and predetermined frequencies moving the second land along of the first land length to match the resonant frequency; and securing the second conductive pattern to the first conductive pattern.

Abstract: A process is revealed whereby resistors can be manufactured integral with a printed circuit board by plating the resistors onto the insulative substrate. Uniformization of the insulative substrate through etching and oxidation of the plated resistor are discussed as techniques for improving the uniformity and consistency of the plated resistors. Trimming and baking are also disclosed as methods for adjusting and stabilizing the resistance of the plated resistors.

Abstract: A method of making an electronic package. The method includes forming a semiconductor chip and an multi-layered interconnect structure. The semiconductor chip includes a plurality of contact members on one of its surfaces that are connected to the multi-layered interconnect structure by a plurality of solder connections. The formed multi-layered interconnect structure is adapted for electrically interconnecting the semiconductor chip to a circuitized substrate (eg., circuit board) with another plurality of solder connections and includes a thermally conductive layer being comprised of a material having a selected thickness and coefficient of thermal expansion to substantially prevent failure of the solder connections between said first plurality of electrically conductive members and the semiconductor chip. The method forms the electronic package to further include a dielectric material having an effective modulus to assure sufficient compliancy of the multi-layered interconnect structure during operation.

Abstract: A sheet capacitor of the invention has a contact portion formed in a through-hole requiring electrical connection with an IC connection pin among the through-holes in which the IC connection pins are inserted, and a capacitor element connected to the contact portion. Another sheet capacitor of the invention includes an insulating board and a capacitor element mounted on the insulating board. The insulating board has a connection land with an IC at the upper side, and a connection land with a printed wiring board at the lower side. The capacitor element and connection lands at the upper and lower side of the insulating board are connected with each other electrically. In any one of these configurations, a capacitor element of large capacity and low ESL is connected closely to the IC, and the mounting area of the peripheral circuits of the IC can be increased.

Abstract: The invention relates to an electronic assembly, in particular for low power consumption electric switching devices such as low power contactors, time relays or the like. In order to provide protection against input current pulses, an ohmic resistor (6) is provided in the form of a resistive layer that is applied by pressing.

Abstract: Exemplary techniques for providing an embedded preemphasis circuit and/or a deemphasis circuit in a printed circuit board (PCB) or other circuit device are disclosed. In particular, a technique for preemphasizing and/or deemphasizing transmitted signals in a PCB-based circuit is provided. The technique may be realized as a preemphasis circuit for preemphasizing a signal being transmitted from a signal source to a signal destination. The preemphasis circuit comprises a printed circuit board (PCB), a resistor embedded in the PCB and having a first terminal electrically connected to the signal source and a second terminal electrically connected to the signal destination, and a capacitor embedded in the PCB and having a first terminal electrically connected to the signal source and a second terminal electrically connected to the signal destination.

Abstract: To reduce switching noise, the power supply terminals of an integrated circuit die are coupled to the respective terminals of at least one capacitor embedded in an interposer that lies between the die and a substrate. In an embodiment, the interposer is a multilayer ceramic structure that couples power and signal conductors on the die to corresponding conductors on the substrate. The capacitor is formed of at least one high permittivity layer and in an embodiment comprises several high permittivity layers interleaved with conductive layers. Alternatively, the capacitor can comprise at least one embedded discrete capacitor. Also described are an electronic system, a data processing system, and various methods of manufacture.

Abstract: A method of making a resonant frequency tag which resonates at a predetermined frequency. The method involves providing a first conductive pattern having an inductive element and a first land and a second conductive pattern having a second land and a third land which are joined together by a link. The second conductive pattern is overlaid the first conductive pattern such that the second land is positioned over the first land. The third land is in electrical communication with the inductive element of the first conductive pattern. The formed resonant frequency tag is energized to determine if the tag resonates at the predetermined frequency. If the tag resonates properly, the third land is electrically coupled to the inductive element. If it does not, the second conductive pattern is adjusted so that overlapping portions of the first and second lands are changed, altering the capacitance to adjust the resonant tag frequency.

Abstract: A hybrid capacitor associated with an integrated circuit package provides multiple levels of excess, off-chip capacitance to die loads. The hybrid capacitor includes a low inductance, parallel plate capacitor embedded within the package, and electrically connected to a second source of off-chip capacitance. The parallel plate capacitor is disposed underneath a die, and includes a top conductive layer, a bottom conductive layer, and a thin dielectric layer that electrically isolates the top and bottom layers. The second source of off-chip capacitance is a set of self-aligned via capacitors, and/or one or more discrete capacitors, and/or an additional parallel plate capacitor. Each of the self-aligned via capacitors is embedded within the package, and has an inner conductor and an outer conductor. The inner conductor is electrically connected to either the top or bottom conductive layer, and the outer conductor is electrically connected to the other conductive layer.

Abstract: A system and method for the fabrication of high reliability capacitors (1011), inductors (1012), and multi-layer interconnects (1013) (including resistors (1014)) on various thin film hybrid substrate surfaces (0501) is disclosed. The disclosed method first employs a thin metal layer (0502) deposited and patterned on the substrate (0501). This thin patterned layer (0502) is used to provide both lower electrodes for capacitor structures (0603) and interconnects (0604) between upper electrode components. Next, a dielectric layer (0705) is deposited over the thin patterned layer (0502) and the dielectric layer (0705) is patterned to open contact holes (0806) to the thin patterned layer. The upper electrode layers (0907, 0908, 1009, 1010) are then deposited and patterned on top of the dielectric (0705).

Abstract: A thin type printed circuit board with an enclosed capacitor of a large capacitance. The printed circuit board includes metal sheet 11 having roughed surface presenting micro-irregularities, a dielectric film for capacitor 12 covering the surface of the metal sheet, and a first electrically conductive layer of electrically conductive resin 13 covering the surface of the dielectric film. A second electrically conductive layer 14 is provided on the surface of the first electrically conductive layer in a region of via for cathode side connection 18. The metal sheet and the first and second electrically conductive layers are encapsulated by resin 15. The via for cathode side connection 18, obtained on boring through the resin 15 until reaching the second electrically conductive layer 14, is coated with an electrode 20. A via for anode side connection 19 obtained on boring through the resin 15 is coated with an electrode 21 that is insulated from the second electrically conductive layer 13 by the resin 15.

Abstract: Chip capacitors 20 are provided in a printed circuit board 10. In this manner, the distance between an IC chip 90 and each chip capacitor 20 is shortened, and the loop inductance is reduced. In addition, the chip capacitors 20 are accommodated in a core substrate 30 having a large thickness. Therefore, the thickness of the printed circuit board does not become large.

Abstract: A power semiconductor module contains a power component and a sensor component. The power component is disposed on a first substrate. The sensor component is electrically and/or mechanically insulated from the power component by being disposed on an individual, separate second substrate. In this manner, disturbances of the sensor system section caused by the power section and its operation can be avoided particularly reliably.

Abstract: The present invention mainly relates to a method for reducing shrinkage during sintering low-temperature-cofired ceramics, the ceramics comprising a dielectric portion and a heterogeneous material portion, the method comprising the steps of: (a) providing a monolithic structure, the monolithic structure comprising a dielectric body and a constraining layer; the dielectric body comprising at least one dielectric layer that comprises at least one active area; wherein said active area is disposed with at least one heterogeneous material pattern; the constraining layer positioned on the top of the dielectric body comprising at least one window wherein the edge of the active area of the dielectric layer each falls within the edge of the window in the vertical direction; (b) firing the monolithic structure; and (c) singulating the monolithic structure along a cutting line to provide the low-temperature-cofired ceramics, wherein the cutting line is disposed in the area formed between the edge of the window and the e

Abstract: A process for forming a circuit pattern on a substrate includes steps of forming a number of electrical circuits on a substrate, which circuits include an electrically conductive bus that interconnects the circuits, covering the electrical circuits with a soldermask, leaving electrical contact portions exposed, electroplating the exposed electrical contacts with a conductive surface finish by using the bus to electrolytically apply the surface finish, and then severing the bus at locations between circuits so that the circuits are electrically isolated from each other. The process may be used to make circuit boards and especially integrated circuit packages.

Abstract: A multiple network electronic component includes an insulator having a first element-forming surface and a second element-forming surface spaced thicknesswise from the first element-forming surface, a plurality of first intermediate film conductors 20A formed on the first element-forming surface and spaced from each other, a plurality of second intermediate film conductors 20B formed on the second element-forming surface and spaced from each other in corresponding relation to the first intermediate film conductors, and a plurality of through-conductive paths penetrating the insulator for electrically connecting each of the first intermediate film conductors to a corresponding one of the second film conductors. The first element-forming surface is formed with a plurality of first elements and a plurality of second elements, and each of the first and second elements has one end connected to a respective one of the first intermediate film conductors.

Abstract: A system and method for the fabrication of high reliability capacitors (1011), inductors (1012), and multi-layer interconnects (1013) (including resistors (1014)) on various thin film hybrid substrate surfaces (0501) is disclosed. The disclosed method first employs a thin metal layer (0502) deposited and patterned on the substrate (0501). This thin patterned layer (0502) is used to provide both lower electrodes for capacitor structures (0603) and interconnects (0604) between upper electrode components. Next, a dielectric layer (0705) is deposited over the thin patterned layer (0502) and the dielectric layer (0705) is patterned to open contact holes (0806) to the thin patterned layer. The upper electrode layers (0907, 0908, 1009, 1010) are then deposited and patterned on top of the dielectric (0705).

Abstract: A technique for fabricating a resistor on a flexible substrate. Specifically, at least a portion of a polyimide substrate is activated by exposure to a ion sputter etch techniques. A metal layer is disposed over the activated portion of the substrate, thereby resulting in the formation of a highly resistive metal-carbide region. Interconnect layers are disposed over the metal-carbide region and patterned to form terminals at opposite ends of the metal carbide region. The metal-carbide region is patterned to form a resistor between the terminals. Alternatively, only a selected area of the polyimide substrate is activated. The selected area forms the area in which the metal-carbide region is formed. Interconnect layers are disposed over the metal-carbide region and patterned to form terminals at opposite ends of the metal-carbide region.

Abstract: The invention provides a surface mounting type electronic circuit unit that is suitable for miniaturization and is suitable for simple output adjustment. Circuit elements including capacitors, resistors, and inductance elements and a conducting pattern connected to the circuit elements are formed on an alumina substrate by means of thin film forming technique, and a diode D1 and a semiconductor chip of a transistor are fixed to a connection land of the conducting pattern by means of wire bonding, wherein only the emitter resistor out of the base bias voltage dividing resistors and the emitter resistor of the transistor is trimmed for output adjustment.

Abstract: A low-EMI circuit which realizes a high mounting density by converting the potential fluctuation of a power supply layer with respect to a ground layer which occurs on switching an IC device etc., into Joule's heat in the substrate without using any parts as a countermeasure against the EMI. Its structure, a circuit board using it, and a method of manufacturing the circuit board are also disclosed. Parallel plate lines in which the Q-value of the stray capacitance between solid layers viewed from the power supply layer and ground layer is equivalently reduced and which are matchedly terminated by forming a structure in which a resistor (resistor layer) and another ground layer are provided in addition to the power supply layer and the ground layer on a multilayered circuit board. A closed shield structure is also disclosed.

Abstract: Three or more, or two or more types of electronic components are formed on one substrate, and these electronic components form an aggregated planar surface on a surface of the substrate.

Abstract: A manufacturing method of a printed circuit board is composed of a first process of forming a pattern of lower electrode 4a at a specific portion on a substrate 2 in which a capacitor element 16 is formed, a second process of forming a capacitor insulative layer 6 that is constituted by a paste material having high permittivity selectively at a position that corresponds to the lower electrode 4a, a third process of forming an interlayer insulative film 8 having low permittivity all over the entire surface of the substrate 2 including the capacitor insulative layer 6, a fourth process of exposing the capacitor insulative layer 6 by grinding the surface of the interlayer insulative film 8 so as to be flat, and a fifth process of forming a capacitor element 16 by forming a pattern of upper electrode on the surface of the capacitor insulative layer 6. Accordingly, the printed circuit board is excellent in mechanical strength, low in manufacturing cost and high in reliability and capacitance accuracy.

Abstract: An electronic part comprising: a printed circuit board including a first major surface and a second major surface; a circuit element disposed on the first major surface of the printed circuit board; a terminal electrode disposed on the second major surface of the printed circuit board and including a major surface opposed to the second major surface of the printed circuit board; a soldering-resistant film disposed on the second major surface of the printed circuit board and including a major surface opposed to the second major surface of the printed circuit board; wherein the distance between the major surface of the terminal electrode and the second major surface of the printed circuit board is substantially equal to or larger than the distance between the major surface of the soldering-resistant film in the vicinity of the terminal electrode and the second major surface of the printed circuit board.

Abstract: A method for producing printed circuits utilizing direct printing methods to apply a pattern mask to a substrate. The direct printing methods include correcting positional errors in a printing apparatus by ascertaining the errors in the printer through comparison of a printed pattern and a known standard pattern. Printer inputs are manipulated to compensate for the ascertained errors of the printer. The pattern mask applied by the corrected printer may be an etch resist mask for forming conductive pathways by an etching process, or the pattern mask may be a plating mask with conductive pathways being formed by a plating operation. The process of the present invention is applicable to forming both single-sided and double-sided printed circuit boards.

Abstract: Via holes are formed in an electrically conductive power plane. Photo-imageable dielectric (PID) material is applied to one side of the power plane filling the via holes. The power plane side with no PID material is exposed to light energy to cure the PID material in the via holes. A developer is used to remove any uncured PID material. Signal plane assemblies comprising a conductive signal plane and a dielectric layer are laminated onto the filled power plane forming a two signal and one power plane (2S1P) structure. In another embodiment, the power plane has PID material applied from both sides. A photo-mask is applied to the power plane and the PID material in the via holes is cured with light energy. A developer is used to remove uncured PID material. Signal plane assemblies, as described above, are laminated onto the filled power plane forming a 2S1P structure.

Abstract: The invention provides an electronic circuit unit that is suitable for miniaturization and excellent in high frequency characteristic. Capacitors and a wiring pattern are formed on an alumina substrate by means of thin film forming technique, and a part of the wiring pattern is served as the connection land for mounting a bare chip of a transistor. Among the capacitors, the top electrode of the capacitor is served also as a part of the connection land, and the bottom side collector electrode of the bare chip is connected to the connection land by use of conductive adhesive. Top electrodes of the residual capacitors are served as the bonding pad, and the base electrode and the emitter electrode on the top side of the bare chip are connected to the top electrodes of the respective capacitors by a wire.

Abstract: An electronic component having a substrate on which one or more grooves are formed on its opposing side faces; electrodes formed on the groove and top and bottom faces of the substrate at a portion adjacent to the groove; and a circuit element formed between the electrodes. An electrode is also formed on the opposing side faces of said substrate at a portion other than the grooves. This structure enables to improve the reliability of a soldered portion even for small electronic components with about 10 &mgr;m thick electrodes such as chip resistors, chip capacitors, and chip inductors.