Having Leadless Component Patents (Class 361/768)
  • Patent number: 10468194
    Abstract: A multilayer ceramic capacitor includes a ceramic body having a plurality of dielectric layers stacked therein, and first and second internal electrodes alternately disposed with at least one among the plurality of dielectric layers interposed therebetween. The first internal electrodes include first and second lead portions exposed to a mounting surface of the ceramic body, and disposed to be spaced apart from each other in a length direction of the ceramic body. The second internal electrodes include a third lead portion exposed to the mounting surface of the ceramic body, and disposed between the first and second lead portions in the length direction of the ceramic body.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: November 5, 2019
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Kyo Kwang Lee, Jin Kim, Young Ghyu Ahn, Chang Su Kim
  • Patent number: 10192686
    Abstract: There are provided a multilayer electronic component and a board having the same. The multilayer electronic component includes: a capacitor body; external electrodes including band portions and connected portions; connection terminals formed of insulators and disposed on the band portions; and insulating portions disposed on at least some circumferential surfaces of the connection terminals. The connection terminals include conductive patterns formed on surfaces thereof facing the band portions and surfaces thereof opposing the surfaces, cut portions are formed in some the circumferential surfaces connecting between the conductive patterns facing each other, connection patterns are formed on the cut portions to electrically connect between the conductive patterns facing each other, and the insulating portions are disposed so as not to cover the cut portions.
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: January 29, 2019
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Heung Kil Park, Gu Won Ji, Se Hun Park
  • Patent number: 10050002
    Abstract: Various implementations enable management of parasitic capacitance and voltage handling of stacked integrated electronic devices. Some implementations include a radio frequency switch arrangement having a ground plane, a stack and a first solder bump. The stack is arranged in relation to the ground plane, and includes switching elements coupled in series with one another, and a first end of the stack includes a respective terminal of a first one of the plurality of switching elements. The first solder bump is coupled to the respective terminal of the first one of the plurality of switching elements such that at least a portion of the first solder bump overlaps with one or more of the plurality of switching elements, an overlap dimension set in relation to a first threshold value in order to set a respective contribution to a parasitic capacitance of the radio frequency switch arrangement.
    Type: Grant
    Filed: November 17, 2014
    Date of Patent: August 14, 2018
    Assignee: Skyworks Solutions, Inc.
    Inventors: Ambarish Roy, Yu Zhu, Christophe Masse
  • Patent number: 9478482
    Abstract: One embodiment of the present invention sets forth an integrated circuit package including a substrate, an integrated circuit die, and a plurality of solder bump structures. The substrate includes a first plurality of interconnects disposed on a first surface of the substrate. The integrated circuit die includes a second plurality of interconnects disposed on a first surface of the integrated circuit die. The plurality of solder bump structures couple the first plurality of interconnects to the second plurality of interconnects. The first plurality of interconnects are configured to be substantially aligned with the second plurality of interconnects when the integrated circuit package is at a first temperature within a range of about 0° C. to about ?100° C. The first plurality of interconnects are configured to be offset from the second plurality of interconnects when the integrated circuit package is at a temperature above the first temperature.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: October 25, 2016
    Assignee: NVIDIA CORPORATION
    Inventors: Leilei Zhang, Zuhair Bokharey
  • Patent number: 9198280
    Abstract: A printed circuit board includes first and second signal pads located on a top surface of the printed circuit board and arranged to transmit a first differential signal, first and second signal vias extending through the printed circuit board and arranged to transmit the first differential signal, a first signal trace located on the top surface of the printed circuit board and connecting the first signal pad and the first signal via, and a second signal trace located on the top surface of the printed circuit board and connecting the second signal pad and the second signal via. The first and second signal vias are located on opposite sides of a line connecting the first and second signal pads.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: November 24, 2015
    Assignee: Samtec, Inc.
    Inventors: Gary Ellsworth Biddle, James Nadolny
  • Patent number: 9087820
    Abstract: An electronic substrate includes: an electronic element provided on a first face of a semiconductor substrate having a through hole; a passive element provided on a second face of the semiconductor substrate; a first part of an interconnection pattern provided on the second face of the semiconductor substrate; an insulating layer provided on the second face of the semiconductor substrate; and a second part of the interconnection pattern provided on the insulating layer.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: July 21, 2015
    Assignee: Seiko Epson Corporation
    Inventor: Nobuaki Hashimoto
  • Patent number: 9070616
    Abstract: A packaging substrate includes a first dielectric layer; a plurality of first conductive pads embedded in and exposed from a first surface of the first dielectric layer; a first circuit layer embedded in and exposed from a second surface of the first dielectric layer; a plurality of first metal bumps disposed in the first dielectric layer, each of the first metal bumps having a first end embedded in the first circuit layer and a second end opposing the first end and disposed on one of the first conductive pads, a conductive seedlayer being disposed between the first circuit layer and the first dielectric layer and between the first circuit layer and the first metal bump; a built-up structure disposed on the first circuit layer and the first dielectric layer; and a plurality of second conductive pads disposed on the built-up structure. The packaging substrate has an over-warpage problem improved.
    Type: Grant
    Filed: December 5, 2013
    Date of Patent: June 30, 2015
    Assignee: Unimicron Technology Corporation
    Inventors: Tzyy-Jang Tseng, Chung-W. Ho
  • Patent number: 9042114
    Abstract: An electronic component includes an interposer, and a multilayer ceramic capacitor. The interposer includes a substrate including front and back surfaces that are parallel or substantially parallel to each other. Two first mounting electrodes and two second mounting electrodes are located on the front surface of the substrate, on opposite end portions in the longitudinal direction. Recesses are located in the longitudinal side surface of the insulating substrate. Connecting conductors are each provided in the side wall surface of each of the recesses. The connecting conductors connect a first external connection electrode and a second external connection electrode that are located on the back surface of the substrate, and first mounting electrodes and second mounting electrodes.
    Type: Grant
    Filed: January 6, 2014
    Date of Patent: May 26, 2015
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Kazuo Hattori, Isamu Fujimoto
  • Patent number: 9035194
    Abstract: Embodiments of the present disclosure are directed towards a circuit board having integrated passive devices such as inductors, capacitors, resistors and associated techniques and configurations. In one embodiment, an apparatus includes a circuit board having a first surface and a second surface opposite to the first surface and a passive device integral to the circuit board, the passive device having an input terminal configured to couple with electrical power of a die, an output terminal electrically coupled with the input terminal, and electrical routing features disposed between the first surface and the second surface of the circuit board and coupled with the input terminal and the output terminal to route the electrical power between the input terminal and the output terminal, wherein the input terminal includes a surface configured to receive a solder ball connection of a package assembly including the die. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: October 30, 2012
    Date of Patent: May 19, 2015
    Assignee: Intel Corporation
    Inventors: M D Altaf Hossain, Jin Zhao, John T. Vu
  • Patent number: 9030836
    Abstract: An apparatus capable of selectively applying different types of connectors to a substrate is disclosed. The memory apparatus includes a substrate having a controller. First and second connector pads may be arranged on edges of top and bottom surfaces of the substrate. A via hole may be arranged between the controller and the first and second connector pads. A first passive device pad may be arranged between the via hole and the first connector pads. A second passive device pad may be arranged between the via hole and the second connector pads. A passive device may be coupled to only one of the first passive device pad or the second passive device pad.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: May 12, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kwang-soo Park, Kyung-suk Kim
  • Patent number: 8969730
    Abstract: Printed circuits may be electrically and mechanically connected to each other using connections such as solder connections. A first printed circuit such as a rigid printed circuit board may have solder pads and other metal traces. A second printed circuit such as a flexible printed circuit may have openings. Solder connections may be formed in the openings to attach metal traces in the flexible printed circuit to the solder pads on the rigid printed circuit board. A ring of adhesive may surround the solder connections. The flexible printed circuit may be attached to the rigid printed circuit board using the ring of adhesive. An insulating tape may cover the solder connections. A conductive shielding layer with a conductive layer and a layer of conductive adhesive may overlap the solder joints. The conductive adhesive may connect the shielding layer to the metal traces on the rigid printed circuit board.
    Type: Grant
    Filed: August 16, 2012
    Date of Patent: March 3, 2015
    Assignee: Apple Inc.
    Inventors: Anthony S. Montevirgen, Emery A. Sanford, Stephen Brian Lynch
  • Patent number: 8923003
    Abstract: An electronic device may contain components such as flexible printed circuits and rigid printed circuits. Electrical contact pads on a flexible printed circuit may be coupled electrical contact pads on a rigid printed circuit using a coupling member. The coupling member may be configured to electrically couple contact pads on a top surface of the flexible circuit to contact pads on a top surface of the rigid circuit. The coupling member may be configured to bear against a top surface of the flexible circuit so that pads on a bottom surface of the flexible circuit rest against pads on a top surface of the rigid circuit. The coupling member may bear against the top surface of the flexible circuit. The coupling member may include protrusions that extend into openings in the rigid printed circuit. The protrusions may be engaged with engagement members in the openings.
    Type: Grant
    Filed: February 6, 2012
    Date of Patent: December 30, 2014
    Assignee: Apple Inc.
    Inventors: Alexander D. Schlaupitz, Joshua G. Wurzel
  • Publication number: 20140355226
    Abstract: An anisotropic conductive film laminate is provided. The anisotropic conductive film laminate includes a first non-conductive film, an anisotropic conductive film disposed on the first non-conductive film, and a second non-conductive film disposed on the anisotropic conductive film, wherein the first non-conductive film has a higher viscosity than the second non-conductive film, and a lower viscosity than the anisotropic conductive film.
    Type: Application
    Filed: January 21, 2014
    Publication date: December 4, 2014
    Applicant: Samsung Display Co., Ltd.
    Inventors: Joon-Sam KIM, Jong-Hwan KIM, Sang-Won YEO
  • Patent number: 8897027
    Abstract: A bonding pad structure is disclosed, which is composed of two bonding pad units that are symmetrically disposed with respect to an axial line. Each bonding pad units is further composed of at least two bonding pads, i.e. each bonding pad unit is composed of at least one first bonding pad and at least one second bonding pad. In an embodiment, the first bonding pad is arranged next to the axial line and the second bonding pad is arranged at a side of the corresponding first bonding pad away from the axial line while enabling the first bonding pad and the corresponding second bonding pad to be interconnected to each other by a first neck portion. Thereby, a plurality of solder areas of different sizes can be formed by the interconnecting of the at least two bonding pad units that can be used for soldering electronic components of different sizes.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: November 25, 2014
    Assignee: Wintek Corporation
    Inventors: Han-Chung Chen, Chun-Yi Wu, Shih-Cheng Wang, Chin-Mei Huang, Tsui-Chuan Wang, Pei-Fang Tsai
  • Patent number: 8867224
    Abstract: A mounting structure includes: an electronic component including: a functional element having a predetermined function; a first resin protrusion section having a surface covered by a covering film including a conductive section electrically connected to the functional element; and a second resin protrusion section that is disposed inside an area surrounded by the first resin protrusion section, and has adhesiveness at least on a surface of the second resin protrusion section, and a base member having a connection electrode and adapted to mount the electronic component. In the structure, the second resin protrusion section mounts the electronic component on the base member in a condition in which the conductive section of the covering film has conductive contact with the connection electrode due to elastic deformation of the first resin protrusion section.
    Type: Grant
    Filed: January 9, 2012
    Date of Patent: October 21, 2014
    Assignee: Seiko Epson Corporation
    Inventor: Yukihiro Hashi
  • Patent number: 8837159
    Abstract: Devices and methods for constructing low-profile, minimal-thickness electronic devices using existing production techniques are disclosed in this application. An electronic component and interposer form a sub-assembly. The sub-assembly is placed in an aperture in a circuit board with the interposer providing interconnections between the electronic component and the circuit board. Such placement conceals the thickness of the integrated circuit within the thickness of the circuit board, reducing overall thickness.
    Type: Grant
    Filed: October 28, 2009
    Date of Patent: September 16, 2014
    Assignee: Amazon Technologies, Inc.
    Inventor: David C Buuck
  • Patent number: 8817485
    Abstract: A single-layer component package comprising: a single conductive-pattern layer having a first surface; an insulating-material layer on the first surface of the single conductive-pattern layer; in an installation cavity inside the insulating-material layer, a semiconductor component having flat contact zones; and solid contact pillars containing copper and solderlessly, metallurgically and electrically connecting the flat contact zones to the single conductive-pattern layer.
    Type: Grant
    Filed: October 21, 2009
    Date of Patent: August 26, 2014
    Assignee: GE Embedded Electronics Oy
    Inventors: Risto Tuominen, Petteri Palm
  • Patent number: 8804364
    Abstract: A footprint of a printed circuit board (PCB) for a leadframe-based package includes a plurality of pads arranged within a central region on a main surface of the PCB; and an array of signal pads disposed within a peripheral region surrounding the central region.
    Type: Grant
    Filed: June 26, 2011
    Date of Patent: August 12, 2014
    Assignee: Mediatek Inc.
    Inventor: Hao-Jung Li
  • Patent number: 8796563
    Abstract: In ultrasonic bonding of a metal terminal to a substrate pad, a thin buffer metal layer which is formed of a soft metal or a highly slidable metal is interposed between a terminal edge and a pad so as to prevent direct contact between an end of the terminal and the pad upon bonding. This makes it possible to prevent abrasion and a crack in the pad at the end of the terminal caused by pressure and an ultrasonic wave upon the ultrasonic bonding. This makes it possible to realize a compact bonded structure with high reliability.
    Type: Grant
    Filed: January 29, 2010
    Date of Patent: August 5, 2014
    Assignee: Hitachi Automotive Systems, Ltd.
    Inventors: Ukyo Ikeda, Masato Nakamura, Shiro Yamashita
  • Publication number: 20140204551
    Abstract: A circuit board assembly with a printed circuit board, which has an SMD mounting location for attaching a first integrated circuit having an electrical circuit. A replacement circuit board having the electrical circuit is soldered at the SMD mounting location using SMD technology.
    Type: Application
    Filed: January 22, 2014
    Publication date: July 24, 2014
    Applicant: Baumueller Nuernberg GmbH
    Inventors: Rainer GRUNERT, Uwe HENSEL
  • Patent number: 8759884
    Abstract: An electronic device comprises a functional stack (10) and a cover (50) coupled thereto by an insulating adhesive layer (30). The functional stack (10) comprises a first transparent and electrically conductive layer (22), a second electrically conductive layer (24) and a functional structure (26), comprising at least one layer, sandwiched between said first and second conductive layer. The cover (50) includes a substrate (52) and at least a first conductive structure (66, 68) that is arranged in a first plane between the adhesive layer (28) and the substrate (52). First and second transverse electrical conductors (32, 34) transverse to the first plane (61) electrically interconnect the first and the second electrically conductive layer (22, 24) with the first and the second conductive structure (66, 68) in the first plane (61).
    Type: Grant
    Filed: July 7, 2009
    Date of Patent: June 24, 2014
    Assignees: Nederlandse Organisatie voor toegepast—natuurwetenschappelijk onderzoek TNO, Koninklijke Philips Electronics N.V.
    Inventors: Jeroen van den Brand, Andreas Heinrich Dietzel, Edward Willem Albert Young, Herbert Lifka, Erik Dekempeneer
  • Patent number: 8754336
    Abstract: A wiring board includes: wiring layers; insulating layers disposed between the wiring layers; and external connection pads respectively including surface plated layers, for connecting to an external circuit. In each of the external connection pads in one face of the wiring board, an outer peripheral edge of the external connection pad is retracted from an outer peripheral edge of the surface plated layer toward a center of the external connection pad.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: June 17, 2014
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventor: Kentaro Kaneko
  • Patent number: 8749989
    Abstract: An LTCC carrier composed of thermosetting polymer, woven glass fiber and ceramic has gold over nickel contact pads on top and bottom surfaces and conductive vias therethrough between aligned pairs of top and bottom pads. The vias prevent undesirable inductive paths from limiting high frequency operation of the circuitry. Solder deposits on the top pads attach the LTCC component, which is further secured to the carrier by epoxy, thus improving resistance to thermal stress and mechanical shock. A slot through the carrier body between top and bottom surfaces further reduces thermal stress and mechanical shock. Metallized castellations on opposite carrier sides provide additional surface area for reflow solder joints with the PCB, and a means for visually inspecting the solder joint quality. A gap in the metallization on the top layer of the carrier prevents solder spreading during multiple soldering cycles, which may result in poor solder joints.
    Type: Grant
    Filed: December 28, 2009
    Date of Patent: June 10, 2014
    Assignee: Scientific Components Corporation
    Inventors: Harvey L. Kaylie, Aron Raklyar
  • Patent number: 8737087
    Abstract: This invention provides a multilayer printed wiring board in which electric connectivity and functionality are obtained by improving reliability and particularly, reliability to the drop test can be improved. No corrosion resistant layer is formed on a solder pad 60B on which a component is to be mounted so as to obtain flexibility. Thus, if an impact is received from outside when a related product is dropped, the impact can be buffered so as to protect any mounted component from being removed. On the other hand, land 60A in which the corrosion resistant layer is formed is unlikely to occur contact failure even if a carbon pillar constituting an operation key makes repeated contacts.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: May 27, 2014
    Assignee: Ibiden Co., Ltd.
    Inventors: Yasuhiro Watanabe, Michimasa Takahashi, Masakazu Aoyama, Takenobu Nakamura, Hiroyuki Yanagisawa
  • Publication number: 20140085848
    Abstract: An assembled circuit is disclosed, wherein the assembled circuit comprises an inductor having a top surface, a bottom surface and side surfaces, wherein each of a plurality of conductors extends from the top surface to the bottom surface via one of the side surfaces of the inductor, wherein a circuit board is disposed over the top surface of the first electronic component and electrically connected to the plurality of conductors and a plurality of pins disposed on the bottom surface of the inductor for connecting to another circuit board.
    Type: Application
    Filed: December 3, 2013
    Publication date: March 27, 2014
    Applicant: DELTA ELECTRONICS, INC.
    Inventors: Jian-Hong Zeng, Wei Yang, Shou-Yu Hong, Jian-Ping Ying
  • Patent number: 8664541
    Abstract: A modified 0402 footprint for a PCB, including: at least two padstacks each having a minimum area consistent with the 0402 standard; and each padstack modified on at least two corners such that the padstack's footprint can be placed beneath a ball grid array (‘BGA’), the BGA having approximately a 1 millimeter pitch, and such that the padstack may be placed at least at a minimum distance away from a closest via in the PCB, wherein each padstack has a trace to a via not directly under a padstack in the PCB and each padstack has no via within the padstack.
    Type: Grant
    Filed: July 25, 2011
    Date of Patent: March 4, 2014
    Assignee: International Business Machines Corporation
    Inventors: Mark E. Andresen, William T. Byrne, Leslie M. Garrett, Paul D. Kangas, Larry G. Pymento, Wilson Velez
  • Patent number: 8630097
    Abstract: Disclosed herein are a power module using sintering die attach and a manufacturing method of the same. The power module includes: a substrate having an insulating layer formed on a surface of a metal plate; a circuit layer formed on the substrate and including a wiring pattern and an electrode pattern; a device mounted on the wiring pattern; a sintering die attach layer applying a metal paste between the wiring pattern and the device and sintering the metal paste to bond the wiring pattern to the device; and a lead frame electrically connecting the device to the electrode pattern, whereby making it possible to simplify and facilitate the process, increase electrical efficiency and improve radiation characteristics, and manufacture firm and reliable power module.
    Type: Grant
    Filed: January 14, 2011
    Date of Patent: January 14, 2014
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Tae Hyun Kim, Yong Hui Joo, Seog Moon Choi
  • Patent number: 8610266
    Abstract: A semiconductor device (5) for radio frequency applications has a semiconductor chip (1) with an integrated circuit accommodated in a radio frequency package. Inside bumps (2) comprise inside contacts between the semiconductor chip (1) and a redistribution substrate (3). The inside bumps (2) have a metallic or plastic core (6) and a coating layer (7) of a noble metal.
    Type: Grant
    Filed: September 5, 2006
    Date of Patent: December 17, 2013
    Assignee: Infineon Technologies AG
    Inventors: Kai Chong Chan, Gerald Ofner
  • Patent number: 8564968
    Abstract: Embodiments include but are not limited to apparatuses and systems including a die package including a substrate, a die coupled with a top surface of the substrate, a package wall disposed on the top surface of the substrate and bounding the die, and a package lid coupled with the package wall, and including at least one protrusion facilitating a coupling of the package lid with the package wall. At least one edge of the top surface of the die pad may include an etched portion such that a width of the top surface is narrower than a width of the bottom surface. At least one edge of a top surface of at least one of the leads may include an etched portion such that a width of the top surface is narrower than a width of the bottom surface. Other embodiments may be described and claimed.
    Type: Grant
    Filed: May 10, 2011
    Date of Patent: October 22, 2013
    Assignee: TriQuint Semiconductor, Inc.
    Inventors: Youngwook Heo, John M. Beall
  • Patent number: 8547701
    Abstract: This publication discloses an electronics module and a method for manufacturing it. The electronic module includes at least one first embedded component (6), the contact terminals (7) of which face essentially towards the first surface of the insulating-material layer (1) and which is connected electrically by its contact terminals (7) to the conductor structures contained in the electronic module. According to the invention, a second embedded component (6?), the contact terminals (7?) of which face essentially towards the second surface of the insulating-material layer and which is connected electrically by its contact terminals (7?) to the conductor structures contained in the electronic module, is attached by means of glue or two-sided tape to the first component (6), and the contact terminals (7, 7?) are connected to the conductor structures with the aid of a conductive material, which is arranged in the insulating-material layer in holes (17) at the locations of the contact terminals (7, 7?).
    Type: Grant
    Filed: November 24, 2005
    Date of Patent: October 1, 2013
    Assignee: Imbera Electronics Oy
    Inventors: Risto Tuominen, Antti Iihola
  • Publication number: 20130170165
    Abstract: An electronic-component mounted body of the present invention includes an electronic component mounted on a circuit board. The electronic component includes multiple component-side electrode terminals, and the circuit board includes multiple circuit-board side electrode terminals for the component-side electrode terminals. The electronic-component mounted body further includes: multiple protruded electrodes formed respectively on the component-side electrode terminals of the electronic component to electrically connect the electronic component and the circuit board; and a dummy electrode formed on the electronic component and electrically connected to the component-side electrode terminal in a predetermined position out of the component-side electrode terminals. The protruded electrode on the component-side electrode terminal in the predetermined position is higher than the protruded electrode on the component-side electrode terminal in a different position from the predetermined position.
    Type: Application
    Filed: September 22, 2011
    Publication date: July 4, 2013
    Applicant: PANASONIC CORPORATION
    Inventors: Daisuke Sakurai, Kazuya Usirokawa
  • Patent number: 8477511
    Abstract: A package structure and an electronic apparatus of the package structure are disclosed. The package structure includes a substrate and a plurality of pins. The plurality of pins is disposed on the substrate. The plurality of pins is interlaced to each other, so that a line along a specific direction will only pass one of the plurality of pins at most.
    Type: Grant
    Filed: September 2, 2010
    Date of Patent: July 2, 2013
    Assignee: Amazing Microelectronic Corp.
    Inventors: Ho-Shyan Lin, Tsu-Yang Wong
  • Patent number: 8451619
    Abstract: Disclosed is a printed wiring board having signal layers each interposed between a power supply layer and a ground layer, wherein the signal layer includes at least one of a wiring region for a ground potential and a wiring region for a power supply potential.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: May 28, 2013
    Assignee: NEC Corporation
    Inventor: Kazuhiro Kashiwakura
  • Publication number: 20130107484
    Abstract: A semiconductor device (20) has a plurality of device-side lands (23) which are disposed asymmetrically in relation to an intersection point (B). The plurality of device-side lands (23) include 45 device-side connection lands and four device-side isolation lands. Each of the device-side connection lands is mechanically connected to a printed board (10) via a connection component (30). Each of the device-side isolation lands is mechanically isolated from the printed board (10).
    Type: Application
    Filed: December 20, 2010
    Publication date: May 2, 2013
    Applicant: PANASONIC CORPORATION
    Inventors: Haruya Sakuma, Masataka Saitoh
  • Patent number: 8426983
    Abstract: A semiconductor device may include: first and second wiring boards separated from each other via a gap; a semiconductor chip; first and second groups of electrode pads; and first and second groups of connection pads. The semiconductor chip is fixed to upper surfaces of the first and second wiring boards, and has a first portion adjacent to the gap. The first and second groups of electrode pads are disposed on the first portion. The first and second groups of electrode pads are aligned adjacent to side surfaces of the first and second wiring boards, respectively. The side surfaces of the first and second wiring boards face each other. The first and second groups of connection pads are disposed on lower surfaces of the first and second wiring boards, respectively. The first and second groups of connection pads are aligned adjacent to the side surfaces of the first and second wiring boards, respectively.
    Type: Grant
    Filed: January 26, 2011
    Date of Patent: April 23, 2013
    Assignee: Elpida Memory, Inc.
    Inventors: Hiromasa Takeda, Satoshi Isa, Mitsuaki Katagiri
  • Patent number: 8411455
    Abstract: A mounting structure 1 in which an electronic component 5 is surface-mounted with solder 4 to a wiring substrate 2 is disclosed. The solder is Sn—Ag—Bi—In-based solder containing 0.1% by weight or more and 5% by weight or less of Bi, and more than 3% by weight and less than 9% by weight of In, with the balance being made up of Sn, Ag and unavoidable impurities. The wiring substrate has a coefficient of linear expansion of 13 ppm/K or less in all directions. Thus, it is possible to realize a mounting structure using lead-free solder and for which the occurrence of cracks in a solder joint portion due to a 1000-cycle thermal shock test from ?40 to 150° C. has been suppressed.
    Type: Grant
    Filed: February 22, 2010
    Date of Patent: April 2, 2013
    Assignee: Panasonic Corporation
    Inventors: Kenji Kondo, Masahito Hidaka, Koji Kuyama, Yutaka Kamogi
  • Patent number: 8395904
    Abstract: A multichip module includes a package substrate, a first semiconductor device, a second semiconductor device and a conductive bump. The first semiconductor device is flip-chip bonded to the package substrate. The first semiconductor device includes a first chip pad on a surface thereof. The second semiconductor device is mounted on the first semiconductor device. The second semiconductor device includes a second chip pad facing the first chip pad. The conductive bump connects the first chip pad to the second chip pad. The conductive bump includes a first metallic body that has a first diffusion rate and a second metallic body that has a second diffusion rate lower than the first diffusion rate.
    Type: Grant
    Filed: June 23, 2010
    Date of Patent: March 12, 2013
    Assignee: Fujitsu Limited
    Inventors: Takayoshi Matsumura, Kenji Kobae, Shuichi Takeuchi, Tetsuya Takahashi
  • Publication number: 20130039026
    Abstract: Provided is a semiconductor device in which misalignment between a semiconductor die and a substrate (e.g., a circuit board) can be prevented or substantially reduced when the semiconductor die is attached to the circuit board. In a non-limiting example, the semiconductor device includes: a semiconductor die comprising at least one bump; and a circuit board comprising at least one circuit pattern to which the bump is electrically connected. In a non-limiting example, the circuit board comprises: an insulation layer comprising a center region and peripheral regions around the center region; a plurality of center circuit patterns formed in the center region of the insulation layer; and a plurality of peripheral circuit patterns formed in the peripheral regions of the insulation layer. The center circuit patterns may be formed wider than the peripheral circuit patterns, formed in a zigzag pattern, and/or may be formed in a crossed shape.
    Type: Application
    Filed: August 3, 2012
    Publication date: February 14, 2013
    Inventors: Min Jae Lee, You Shin Chung, Hoon Jung
  • Publication number: 20130033836
    Abstract: A chip-component structure includes an interposer and a multilayer capacitor mounted thereon. The interposer includes a substrate, a component connecting electrode, an external connection electrode, and a side electrode. The component connecting electrode and the external connection electrode are electrically connected by the side electrode. The component connecting electrode is joined to an external electrode of the multilayer capacitor. The substrate includes a communication hole that communicates between opposite spaces opening in both principal surfaces of the substrate.
    Type: Application
    Filed: August 3, 2012
    Publication date: February 7, 2013
    Applicant: MURATA MANUFACTURING CO., LTD.
    Inventors: Kazuo HATTORI, Isamu FUJIMOTO
  • Patent number: 8351214
    Abstract: This publication discloses an electronics module comprising an insulating-material layer having two opposite surfaces, and at least one microcircuit embedded to the insulating-material layer. The microcircuit has a first contact surface comprising first contact terminals, from which the microcircuit is electrically connected to first conductor structures in the form of a patterned first conductor layer contained on first surface of the insulating-material layer, and a second contact surface opposite to the first contact surface, in which there is at least one second contact terminal, from which the microcircuit is electrically connected to second conductor structures contained in the form of a patterned second conductor layer on second surface of the insulating-material layer. According to the invention there is provided a local adhesive layer between the component and the first contact surface and first conductor layer, the adhesive layer filling the space between the component and the first conductor layer.
    Type: Grant
    Filed: May 4, 2010
    Date of Patent: January 8, 2013
    Assignee: Imbera Electronics Oy
    Inventors: Risto Tuominen, Antti Iihola
  • Patent number: 8300420
    Abstract: A circuit substrate includes an electrically conductive layer having electrically conductive patterns formed therein, an insulating layer having a through hole, and a composite layer positioned between the electrically conductive layer and the insulating layer. The through hole is configured for having an electronic component mounted thereon. The composite layer includes a polymer matrix and at least one carbon nanotube bundle embedded in the polymer matrix. One end of the at least one carbon nanotube bundle contacts the electrically conductive patterns, and the other is exposed in the through hole of the insulation layer.
    Type: Grant
    Filed: May 24, 2009
    Date of Patent: October 30, 2012
    Assignee: Zhen Ding Technology Co., Ltd.
    Inventors: Chung-Jen Tsai, Hung-Yi Chang, Chia-Cheng Chen, Meng-Chieh Hsu, Cheng-Hsien Lin
  • Patent number: 8279618
    Abstract: A circuit substrate includes protruding terminals and has a structure that ensures an excellent connection with an electronic component, such as an IC. The circuit substrate on which an IC is to be mounted includes terminals that are to be electrically connected to solder bumps located on the IC. The terminals protrude from the mounting surface of a substrate body on which the IC is to be mounted. The sectional area of the top surface of each of the terminals is about 1.2 times the sectional area of each of the terminals on the mounting surface.
    Type: Grant
    Filed: March 4, 2010
    Date of Patent: October 2, 2012
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Yutaka Fukuda
  • Patent number: 8208271
    Abstract: A printed board having an input/output terminal that connects with a component in an image formation apparatus through a cable, and a control circuit that controls the component, the printed board which includes a conductive pattern on which a capacitor that suppresses an emission of an electromagnetic wave from the cable is mounted between a grounding surface and a signal line from the input/output terminal, the conductive pattern being formed in the vicinity of the input/output terminal.
    Type: Grant
    Filed: March 25, 2009
    Date of Patent: June 26, 2012
    Assignee: Fuji Xerox Co., Ltd
    Inventors: Atsushi Aketo, Hisanori Yukawa, Shogo Sata, Masaru Yonemochi, Hiromasa Kanno
  • Patent number: 8188379
    Abstract: A package substrate structure includes: a substrate having a first surface and an opposing second surface and characterized by a plurality of wire-bonding pads provided on the first surface of the substrate, a plurality of ball-implanting pads provided on the second surface of the substrate, and at least a cavity formed to penetrate the first and second surfaces of the substrate; a metal board mounted on the second surface of the substrate and covering the cavity, wherein the metal board has a thickness greater than that of the ball-implanting pads and has an area greater than that of the cavity; and solder masks disposed on the first and second surfaces of the substrate respectively and having at least a solder-mask cavity corresponding in position to the cavity of the substrate, the solder masks further having a plurality of openings for exposing the wire-bonding pads, the ball-implanting pads and the metal board.
    Type: Grant
    Filed: June 30, 2009
    Date of Patent: May 29, 2012
    Assignee: Unimicron Technology Corp.
    Inventor: Shin-Ping Hsu
  • Patent number: 8184453
    Abstract: Disclosed is a lead frame and a semiconductor device including the same. The lead frame is provided with a die pad, and first, second and third lands sequentially arranged on an outer circumferential edge. The lead frame can separate the first and second lands or the die pad and the first land using a plating layer formed on the lead frame as a mask, instead of using a separate mask by etching after the application of the encapsulant. As a result thereof, a plurality of lands can be formed at low cost, in comparison with a conventional method. Additionally, the first, second and third lands are exposed to the outside through a lower portion of an encapsulant, and can be surface mounted on an external device through the first, second and third lands.
    Type: Grant
    Filed: July 31, 2008
    Date of Patent: May 22, 2012
    Assignee: Amkor Technology, Inc.
    Inventors: Jae Yoon Kim, Gi Jeong Kim, Myung Soo Moon
  • Patent number: 8184444
    Abstract: Provided is an electrode pad for mounting an electronic component on a surface of a circuit board. The electrode pad includes first and second electrode parts facing each other, and third and fourth electrode parts facing each other. The third and fourth electrode parts are disposed adjacent to the first and second electrode parts for forming corners of the electrode pad together with the first and second electrode parts. At least one of the first to fourth electrode parts includes a chamfered surface formed by cutting a corner of the at least one of the first to fourth electrode parts forming the corner of the electrode pad. Therefore, when the electrode pad is used for mounting an electronic component, the width of an outer electrode of the electronic component can be sufficiently increased, and thus the shape or size of the outer electrode can be easily adjusted.
    Type: Grant
    Filed: April 16, 2009
    Date of Patent: May 22, 2012
    Assignee: Samsung Electro-Mechanics Co., Ltd
    Inventors: Byoung Hwa Lee, Sung Kwon Wi, Hong Yeon Cho, Dong Seok Park, Sang Soo Park, Min Cheol Park
  • Patent number: 8179690
    Abstract: A cut-edge positioning type soldering structure and a method for preventing a pin deviation can prevent a plurality of pins of an electronic component from being deviated when the pins are soldered onto a printed circuit board by a solder, and each of at least two solder pads includes at least two cut edges, and the solder pads are installed in an alignment direction on the printed circuit board, such that the cut-edge positioning type soldering structure and the method for preventing a pin deviation can improve the efficiency of manufacturing processes and reduce the manufacturing cost.
    Type: Grant
    Filed: July 22, 2010
    Date of Patent: May 15, 2012
    Assignee: Askey Computer Corp.
    Inventors: Hsiang-Chih Ni, Ching-Feng Hsieh
  • Patent number: 8164003
    Abstract: A circuit board surface structure and a fabrication method thereof are proposed. The circuit board surface structure includes: a circuit board having a plurality of electrically connecting pads formed on at least one surface thereof; a first and a second insulating protective layers formed on the surface of the circuit board in sequence; first and a second openings respectively formed in the first and second insulating protective layers to expose the electrically connecting pads on the surface of the circuit board, wherein the first and second openings have narrow top and wide bottom and the diameter of the first openings is bigger than that of the second openings; and conductive elements formed in the first and second openings on surfaces of the electrically connecting pads. The present structure facilitates to strengthen the bonding between the conductive elements and the corresponding electrically connecting pads.
    Type: Grant
    Filed: March 6, 2008
    Date of Patent: April 24, 2012
    Assignee: Unimicron Technology Corp.
    Inventors: Sao-Hsia Tang, Ying-Tung Wang
  • Patent number: 8159825
    Abstract: A method for electrically interconnecting two substrates, each having a corresponding set of preformed electrical contacts, the substrates comprising an electronic circuit, and the resulting module, is provided. A liquid curable adhesive is provided over the set of contacts of a first substrate, and the set of electrical contacts of the second substrate is aligned with the set of electrical contacts of the first substrate. The sets of electrical contacts of the first and second substrate are compressed to displace the liquid curable adhesive from the inter-contact region, and provide electrical communication between the respective sets of electrical contacts. The liquid curable adhesive is then cured to form a solid matrix which maintains a relative compression between the respective sets of electrical contacts. One embodiment of the module comprises a high-speed superconducting circuit which operates at cryogenic temperatures.
    Type: Grant
    Filed: August 18, 2007
    Date of Patent: April 17, 2012
    Assignee: Hypres Inc.
    Inventor: Vladimir V. Dotsenko
  • Patent number: 8139370
    Abstract: A method and system for a FET cell is presented. The FET cell includes multiple individual transistors and interconnect bumps that are configured to flip-chip connect to a substrate. The substrate may have the majority of a matching structure for the FET cell. Furthermore, the FET cell may include a stability circuit in communication with the terminals of the individual transistors and further in communication with the interconnect bumps. Additionally, different materials can be used in combination in the FET cell and the separate substrate having the majority of the matching structure. Various materials may be more efficiency used in a FET cell, while other materials are suitable for the separate substrate.
    Type: Grant
    Filed: March 24, 2009
    Date of Patent: March 20, 2012
    Assignee: ViaSat, Inc.
    Inventor: Kenneth V. Buer