With Mounting Pad Patents (Class 361/767)
  • Patent number: 10993321
    Abstract: A wiring substrate has a substrate body formed by a single or a plurality of insulating layers and having front and back surfaces located at opposite sides of the substrate body; a plurality of pads formed on at least one of the front surface, the back surface and an inner layer surface that is located between the front and back surfaces, and having a staggered arrangement in plan view; and a plurality of via conductors formed at each of the pads, extending in a thickness direction of the substrate body with the plurality of via conductors being parallel to each other and connecting the pads located on different surfaces. Arrangement, in plan view, of the plurality of via conductors connecting to the pad and arrangement, in plan view, of the plurality of via conductors connecting to an adjacent pad located on the same surface are different from each other.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: April 27, 2021
    Assignee: NGK SPARK PLUG CO., LTD.
    Inventor: Takahiro Hayashi
  • Patent number: 10993325
    Abstract: Interposer printed circuit boards for power modules and associated methods are disclosed. In at least one illustrative embodiment, a printed circuit board assembly may comprise a printed circuit board having a surface, an electrical component mounted on the surface, a pin mounted on the surface, and an interposer printed circuit board mounted on the surface. The electrical component may have a first height orthogonal to the surface. The pin may have a second height orthogonal to the surface, where the second height is greater than the first height. The interposer printed circuit board may comprise a pad and an outer solder bump positioned on the pad. The outer solder bump may have a third height orthogonal to the surface, where the third height is greater than the first height.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: April 27, 2021
    Assignee: ABB Power Electronics Inc.
    Inventors: John Andrew Trelford, Richard John Yeager, Alok Kumar Lohia, Thang Danh Truong
  • Patent number: 10984965
    Abstract: The present description relates to a fully biodegradable supercapacitor and a method for manufacturing the same. When the fully biodegradable supercapacitor and the method for manufacturing the same according to the present description are used, supercapacitor having high capacitance, high energy, and high output is provided by forming a metal oxide on a metal electrode and a surface of a solid electrolyte. In addition, the present description is environment-friendly, biodegradable, and biocompatible to be implanted into a body, and may be a bio-implantable energy storage device in the future.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: April 20, 2021
    Assignee: Korea University Research and Business Foundation
    Inventors: Jeong Sook Ha, Geumbee Lee, Yu Ra Jeong
  • Patent number: 10986730
    Abstract: Substrates configured to route electrical signals may include a first dielectric material and an electrically conductive material located on a first side of the first dielectric material. A second dielectric material may be located on a second, opposite side of the first dielectric material. A series of voids may be defined by the second dielectric material extending from the first dielectric material at least partially through the second dielectric material. Footprints of at least some of the voids of the series of voids may at least partially laterally overlap with the electrically conductive material.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: April 20, 2021
    Assignee: Microsemi Semiconductor ULC
    Inventors: Nasser Ghassemi, Mehran Aliahmad
  • Patent number: 10980132
    Abstract: LEDs for an illumination system may be mounted on a PCB. The PCB may be provided with alignment features such as oversized holes for connection to a support surface. Using optical sensing of the position of the mounted LEDs, the space made available by the alignment features may be reduced and aligned to create modified alignment features. The modified alignment features may be created by adding a modifying component and aligned based on the sensed positions of the mounted LEDs. The positioning of the modifying component may offset misalignment of the LEDs with the PCB. An opening in the modified alignment feature may receive a bolt or alignment pin for connection to the support surface. The support surface may be aligned with the secondary optics, resulting in the LEDs being aligned with the secondary optics irrespective of misalignment of the LEDs with respect to the PCB.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: April 13, 2021
    Assignee: Lumileds LLC
    Inventor: Axel Mehnert
  • Patent number: 10931009
    Abstract: Aspects of this disclosure relate to methods of selectively shielded radio frequency modules. A radio frequency module can be provided with a radio frequency component and an antenna. A shielding layer can be formed over a portion of the radio frequency module such that the radio frequency component is shielded by the shielding layer and the antenna is unshielded by the shielding layer.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: February 23, 2021
    Assignee: Skyworks Solutions, Inc.
    Inventors: Hoang Mong Nguyen, Anthony James LoBianco, Gregory Edward Babcock, Darren Roger Frenette, George Khoury
  • Patent number: 10925151
    Abstract: Systems and methods for providing a PWB. The methods comprise: forming a Core Substrate (“CS”) a First Via (“FV”) formed therethrough; disposing a First Trace (“FT”) on an exposed surface of CS that is in electrical contact with FV; laminating a first HDI substrate to CS such that FT electrically connects FV via with a Second Via (“SV”) formed through the first HDI substrate; disposing a Second Trace (“ST”) on an exposed surface of the first HDI substrate that is in electrical contact with SV; and laminating a second HDI substrate to the first HDI substrate such that ST electrically connects SV to a Third Via (“TV”) formed through the second HDI substrate. SV comprises a buried via with a central axis spatially offset from central axis of FV and SV. FV and SV have diameters which are smaller than TV's diameter.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: February 16, 2021
    Assignee: EAGLE TECHNOLOGY, LLC
    Inventors: Michael T. DeRoy, Marvin D. Miller, Andres M. Gonzalez, David Cure, Tena M. Hochard
  • Patent number: 10896884
    Abstract: A semiconductor package includes a frame having a first through-hole, a semiconductor chip having an active surface on which a connection pad is disposed; a first encapsulant encapsulating at least a portion of the semiconductor chip; a second encapsulant disposed on at least a portion of the external side surface of the frame, and a connection member disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pad of the semiconductor chip. The frame includes an insulating layer, a wiring layer disposed on upper and lower surfaces of the insulating layer, a first metal layer on the external side wall of the insulating layer, a second metal layer on the internal side wall of the first through hole, and a via penetrating the upper and lower surfaces of the insulating layer.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: January 19, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yong Koon Lee, Jin Su Kim
  • Patent number: 10861785
    Abstract: An electronic module includes an electronic part including a bottom surface and lands, the bottom surface including a first region and a third region surrounding the first region, the first lands being disposed in the third region, a printed wiring board including a main surface and second lands, the main surface including a second region and a fourth region surrounding the second region, the main surface facing the bottom surface of the electronic part, the second lands being disposed in the fourth region, solder bonding portions respectively bonding the first lands to the second lands, and a resin portion containing a cured product of a thermosetting resin and being in contact with the solder boding portions. A recess portion is provided in the second region. The resin portion is not provided in the recess portion.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: December 8, 2020
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Shingo Ishiguri, Mitsutoshi Hasegawa, Kunihiko Minegishi, Takashi Sakaki
  • Patent number: 10832830
    Abstract: The present invention provides an anisotropic electrically conductive film with a structure, in which electrically conductive particles are disposed at lattice points of a planar lattice pattern in an electrically insulating adhesive base layer. A proportion of the lattice points, at which no electrically conductive particle is disposed, with respect to all the lattice points of the planar lattice pattern assumed as a reference region, is less than 20%. A proportion of the lattice points, at which plural electrically conductive particles are disposed in an aggregated state, with respect to all the lattice points of the planar lattice pattern, is not greater than 15%. A sum of omission of the electrically conductive particle and an aggregation of the electrically conductive particles is less than 25%.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: November 10, 2020
    Assignee: DEXERIALS CORPORATION
    Inventors: Tomoyuki Ishimatsu, Reiji Tsukao
  • Patent number: 10818578
    Abstract: A method of manufacturing semiconductor devices such as integrated circuits comprises: providing one or more semiconductor chips having first and second opposed surfaces, coupling the semiconductor chip or chips with a support substrate with the second surface towards the support substrate, embedding the semiconductor chip or chips coupled with the support substrate in electrically-insulating packaging material by providing in the packaging material electrically-conductive passageways. The electrically-conductive passageways comprise: electrically-conductive chip passageways towards the first surface of the at least one semiconductor chip, and/or electrically-conductive substrate passageways towards the support substrate.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: October 27, 2020
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Michele Derai, Federico Giovanni Ziglioli
  • Patent number: 10782319
    Abstract: A probe card for testing of electronic devices comprises a testing head with plural contact probes inserted into guide holes of an upper guide and a lower guide, and a space transformer, each of the contact probes having a first terminal portion projecting from the lower guide with a first length and ending with a contact tip adapted to abut onto a respective contact pad of a device to be tested, and a second terminal portion projecting from the upper guide with a second length and ending with a contact head adapted to abut onto a contact pad of the space transformer. The probe card comprises a spacer element interposed between the space transformer and the upper guide and removable to adjust the first length of the first terminal portion by changing the second length of the second terminal portion and approaching the upper guide and the space transformer.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: September 22, 2020
    Assignee: TECHNOPROBE S.P.A.
    Inventors: Roberto Crippa, Stefano Felici
  • Patent number: 10770387
    Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for dual surface finish package substrate assemblies. In one embodiment a method includes depositing a first lamination layer on a first side of a package substrate and a first surface finish on one or more electrical contacts disposed on a second side of the package substrate; removing the first lamination layer from the first side of the package substrate; depositing a second lamination layer on the second side of the package substrate and a second surface finish on the one or more electrical contacts disposed on the first side of the package substrate; and removing the second lamination layer from the second side of the package substrate. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: September 8, 2020
    Assignee: INTEL CORPORATION
    Inventors: Qinglei Zhang, Stefanie M. Lotz
  • Patent number: 10687746
    Abstract: This application features a method of forming a nanoporous layer. The method includes steps of reducing metal ions in a reverse micelle phase composition to form nanoparticles, removing surfactant from the composition to form clusters of the nanoparticles, dispensing the composition including the nanoparticle clusters dispersed in a liquid on a substrate, and drying to form the nanoporous layer. The nanoporous layer includes nanoparticles deposited to form a three dimensional network of irregularly shaped bodies. The nanoporous layer also includes a three dimensional network of intercluster spaces that are not occupied by the three dimensional network of irregularly shaped bodies.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: June 23, 2020
    Assignee: UXN CO., LTD.
    Inventors: Hankil Boo, Rae Kyu Chang
  • Patent number: 10660206
    Abstract: An information handling system (IHS) has a circuit board assembly with a dual-sided interposer substrate that is inserted between a baseboard and a processor integrated circuit having a second pattern of electrical contacts. The dual interposer substrate formed of a stack of printed circuit boards (PCBs) provides communication channels between a first coupling pad on the baseboard that has a first pattern of electrical contacts and a second coupling pad on top of the dual interposer substrate that provides the second pattern of electrical contacts. The second pattern receives another type of processor integrated circuit than a type supported by the first pattern. Stacked vias formed through the stack of PCBs electrically connect respective electrical contacts of the first and second coupling pads to form a corresponding communication channel. One or more grounded vias mitigate signal integrity (SI) anomalies on the communication channels.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: May 19, 2020
    Assignee: Dell Products, L.P.
    Inventors: Kevin W. Mundt, Sandor Farkas, Bhyrav M. Mutnury, Yeshaswy Rajupalepu
  • Patent number: 10629094
    Abstract: A module assembly includes a device. The device comprises a base structure and a flat planar top surface located at an upper portion of the base structure. The module assembly further includes an electrical source coupled to the base structure of the module to provide power to the device. A plurality of components is coupled to the device at the top surface. Each component of the plurality of components is coupled to the electrical source and the plurality of components combine to purpose a particular technical function. A module system comprises at least two module assemblies coupled together. The module system may purpose a combined technical function.
    Type: Grant
    Filed: July 1, 2014
    Date of Patent: April 21, 2020
    Assignee: Northeast Wisconsin Technical College
    Inventors: Joseph John Barker, Edward Francis Kralovec, Troy A. Giese, Jacob D. Morois
  • Patent number: 10615109
    Abstract: A substrate includes a first dielectric layer having a first surface and a second dielectric layer having a first surface disposed adjacent to the first surface of the first dielectric layer. The substrate further includes a first conductive via disposed in the first dielectric layer and having a first end adjacent to the first surface of the first dielectric layer and a second end opposite the first end. The substrate further includes a second conductive via disposed in the second dielectric layer and having a first end adjacent to the first surface of the second dielectric layer. A width of the first end of the first conductive via is smaller than a width of the second end of the first conductive via, and a width of the first end of the second conductive via is smaller than the width of the first end of the first conductive via.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: April 7, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Cheng-Lin Ho, Chih-Cheng Lee
  • Patent number: 10582864
    Abstract: A measurement sensor package and a measurement sensor improve reliability in strength and other aspects. A measurement sensor package includes a substrate, a lid, a ground conductor layer, a metallic thin layer, and a bond. The ground conductor layer and the metallic thin layer are arranged inside the bond that extends continuously as viewed through from above. The bond directly bonds a first main surface of a substrate body and a facing surface of the lid together along the entire periphery. This improves the reliability in strength.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: March 10, 2020
    Assignee: KYOCERA CORPORATION
    Inventors: Yasushi Oode, Hiroki Ito, Yoshimasa Sugimoto, Noritaka Niino, Shogo Matsunaga, Takuya Hayashi
  • Patent number: 10566108
    Abstract: The present invention provides an anisotropic electrically conductive film with a structure, in which electrically conductive particles are disposed at lattice points of a planar lattice pattern in an electrically insulating adhesive base layer. A proportion of the lattice points, at which no electrically conductive particle is disposed, with respect to all the lattice points of the planar lattice pattern assumed as a reference region, is less than 20%. A proportion of the lattice points, at which plural electrically conductive particles are disposed in an aggregated state, with respect to all the lattice points of the planar lattice pattern, is not greater than 15%. A sum of omission of the electrically conductive particle and an aggregation of the electrically conductive particles is less than 25%.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: February 18, 2020
    Assignee: DEXERIALS CORPORATION
    Inventors: Tomoyuki Ishimatsu, Reiji Tsukao
  • Patent number: 10559538
    Abstract: A power module of the invention includes a power semiconductor element mounted on a circuit board, and an adapter connected to a front-surface main electrode of the element, wherein the adapter includes a main-electrode wiring member which is connected to the front-surface main electrode of the element; and wherein the main-electrode wiring member includes: an element connection portion connected to the front-surface main electrode of the element; a board connection portion which is placed outside the element connection portion and connected to the circuit board; and a connector connection portion which is placed outside the element connection portion and connected to an external electrode through a connector.
    Type: Grant
    Filed: February 9, 2016
    Date of Patent: February 11, 2020
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Junji Fujino, Shohei Ogawa, Soichi Sakamoto
  • Patent number: 10537016
    Abstract: The present disclosure relates to systems and methods using thermal vias to increase the current-carrying capacity of conductive traces on a multilayered printed circuit board (PCB). In various embodiments, parameters associated with vias may be selected to control various electrical and thermal properties of the conductive trace. Such parameters include the via diameter, a plating thickness, a number of vias, a placement of the vias, an amount of conductive material to be added or removed from the conductive trace, a change in the resistance of the conductive trace, a change in a fusing measurement of the conductive trace, and the like.
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: January 14, 2020
    Assignee: Schweitzer Engineering Laboratories, Inc.
    Inventors: Travis C. Mallett, Ben M. Armstrong, Forrest A. Rahrer
  • Patent number: 10499163
    Abstract: A microphone assembly including a main board and a microphone. The microphone includes a capacitor or a MEMS chip, a case accommodating the capacitor or the MEMS chip, and a microphone board electrically connected to the capacitor or the MEMS chip. The microphone board has a larger outer dimension than the case and includes a fixing portion and a connecting portion. The case is fixed onto the fixing portion. The connecting portion is a portion of the microphone board, the portion being located outside the case and electrically and mechanically connected to the main board.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: December 3, 2019
    Assignee: HOSIDEN CORPORATION
    Inventors: Naosuke Fukada, Mayumi Kaneko, Ryuji Awamura, Hidenori Motonaga, Kensuke Nakanishi
  • Patent number: 10468374
    Abstract: Examples relate to a die interconnect substrate comprising a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate further comprises a substrate structure comprising a substrate interconnect electrically insulated from the bridge die, wherein the bridge die is embedded in the substrate structure. The die interconnect substrate further comprises a first interface structure for attaching a semiconductor die to the substrate structure, wherein the first interface structure is connected to the first bridge die pad. The die interconnect substrate further comprises a second interface structure for attaching a semiconductor die to the substrate structure, wherein the second interface structure is connected to the substrate interconnect. A surface of the first interface structure and a surface of the second interface structure are at the same height.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: November 5, 2019
    Assignee: Intel Corporation
    Inventors: Rahul Jain, Ji Yong Park, Kyu Oh Lee
  • Patent number: 10412829
    Abstract: To prevent degradation of electrical characteristics caused by a resin filled between electrodes in an ultraviolet light-emitting operation, the present invention provides a base 10 that comprises an insulating base material 11 and two or more metal films 12 and 13 that are formed on one side of the insulating base material 11 and electrically separated from each other. The two or more metal films are formed to include an upper surface and a side wall surface that are covered by gold or a platinum group metal, to be capable of mounting thereon one or more nitride semiconductor light-emitting elements and the like, and to have, as a whole, a predetermined planar view shape including two or more electrode pads.
    Type: Grant
    Filed: August 2, 2016
    Date of Patent: September 10, 2019
    Assignees: SOKO KAGAKU CO., LTD., AGC INC.
    Inventors: Akira Hirano, Ko Aosaki
  • Patent number: 10375826
    Abstract: A printed circuit board assembly (PCBA) for downhole applications has a printed circuit board (PCB) and a plurality of electronic components installed on the PCB. The PCB comprises a polyimide substrate, a lead-free surface finish, a plurality of traces, a plurality of surface mount pads, and a plurality of VIAs. The ratio between the width of one of the plurality of surface mount pads to the width of the trace connected thereto is 2 or less.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: August 6, 2019
    Assignee: CHINA PETROLEUM & CHEMICAL CORPORATION
    Inventors: Sheng Zhan, Jinhai Zhao, Fengtao Hu, Herong Zheng
  • Patent number: 10354957
    Abstract: An electrical interconnect for an electronic package. The electrical interconnect includes a first dielectric layer; a second dielectric layer; a signal conductor positioned between the first dielectric layer and the second dielectric layer; and a conductive reference layer mounted on the first dielectric layer, and wherein the conductive reference layer does not cover the signal conductor. The conductive reference layer may be a first conductive reference layer and the electrical interconnect further comprises a second conductive reference layer mounted on the second dielectric layer. The second conductive reference layer does not cover the signal conductor. In addition, the signal conductor may be a first signal conductor and the electrical interconnect may further include a second signal conductor between the first dielectric layer and the second dielectric layer. The first and second signal conductors may form a differential pair of conductors.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: July 16, 2019
    Assignee: Intel Corporation
    Inventors: Bok Eng Cheah, Jackson Chung Peng Kong, Stephen Harvey Hall, Khang Choong Yong, Kooi Chi Ooi, Eric C Gantner
  • Patent number: 10308786
    Abstract: Provided are a power inductor including a body, a base disposed in the body, a coil disposed on the base, a first external electrode connected to the coil, the first external electrode being disposed on a side surface of the body, and a second external electrode connected to the first external electrode, the second external electrode being disposed on a bottom surface of the body and a method for manufacturing the same.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: June 4, 2019
    Assignee: MODA-INNOCHIPS CO., LTD.
    Inventors: In Kil Park, Gyeong Tae Kim, Seung Hun Cho, Jun Ho Jung, Ki Joung Nam, Jung Gyu Lee
  • Patent number: 10304587
    Abstract: The present invention provides an anisotropic electrically conductive film with a structure, in which electrically conductive particles are disposed at lattice points of a planar lattice pattern in an electrically insulating adhesive base layer. A proportion of the lattice points, at which no electrically conductive particle is disposed, with respect to all the lattice points of the planar lattice pattern assumed as a reference region, is less than 20%. A proportion of the lattice points, at which plural electrically conductive particles are disposed in an aggregated state, with respect to all the lattice points of the planar lattice pattern, is not greater than 15%. A sum of omission of the electrically conductive particle and an aggregation of the electrically conductive particles is less than 25%.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: May 28, 2019
    Assignee: DEXERIALS CORPORATION
    Inventors: Tomoyuki Ishimatsu, Reiji Tsukao
  • Patent number: 10292281
    Abstract: Provided is an electronic control device that is easily assembled and with which it is possible to reduce the effects of vibration and external force applied from a connector. Electronic components are installed on a substrate. A base covers a surface of the substrate. A cover covers a surface of the substrate. A first connector, which is installed on the surface, connects to a connector fixed to an on-board transmission. A second connector, which is installed on the surface, connects to a connector of a harness. First vibration-suppressing parts, which are provided to the inside surface of the base facing the end surface of the first connector on the surface side, suppress the vibration of the first connector.
    Type: Grant
    Filed: January 8, 2016
    Date of Patent: May 14, 2019
    Assignee: Hitachi Automotive Systems, Ltd.
    Inventors: Masato Saito, Yoshio Kawai, Shoho Ishikawa
  • Patent number: 10269584
    Abstract: Embodiments of the present disclosure include a semiconductor device and methods of forming a semiconductor device. An embodiment is a semiconductor device comprising an interconnecting structure consisting of a plurality of thin film layers and a plurality of metal layers disposed therein, each of the plurality of metal layers having substantially a same top surface area, and a die comprising an active surface and a backside surface opposite the active surface, the active surface being directly coupled to a first side of the interconnecting structure. The semiconductor device further comprises a first connector directly coupled to a second side of the interconnecting structure, the second side being opposite the first side.
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Wei Chiu, Cheng-Hsien Hsieh, Hsien-Pin Hu, Kuo-Ching Hsu, Shang-Yun Hou, Shin-Puu Jeng
  • Patent number: 10256204
    Abstract: Embodiments of the present disclosure relate to separating an integrated circuit (IC) structure from an adjacent chip. An IC structure according to embodiments of the disclosure may include: a semiconductor region including an interconnect pad positioned thereon, the interconnect pad electrically connected to a solder bump; and an ohmic heating wire positioned within the semiconductor region and in thermal communication with the interconnect pad, wherein the ohmic heating wire is configured to be heated above a melting temperature of the solder bump.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: April 9, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Glen E Richard, Stephen P Ayotte, Hanyi Ding
  • Patent number: 10181437
    Abstract: A package substrate includes a substrate, a first connection terminal mounted over the substrate, the first connection terminal including a first land and a second land on the substrate, a first solder resist surrounding the first land and the second land, and a first solder ball formed straddling the first land and the second land; and a second connection terminal which is mounted over the substrate and disposed adjacent to the first connection terminal, the second connection terminal including a third land and a fourth land on the substrate, a second solder resist surrounding the third land and the fourth land, and a second solder ball formed straddling the third land and the fourth land.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: January 15, 2019
    Assignee: Fujitsu Limited
    Inventors: Manabu Watanabe, Kenji Fukuzono, Yuki Hoshino, Masateru Koide
  • Patent number: 10166869
    Abstract: An electronic component unit of a wire harness includes a substrate on which an electronic component is mounted, a connector electrically connected to the substrate, and a connector fixing structure. The connector fixing structure includes a pair of notches that are provided facing each other on ends of the substrate in a long-side direction and that penetrate through the substrate in a plate thickness direction, a pair of press fitting plates that are provided on the connector and that are press-fitted into the respective notches, and a deformation acceptable space that is provided adjacent to each of both sides of the press fitting plates press-fitted into the respective notches in the long-side direction.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: January 1, 2019
    Assignees: YAZAKI CORPORATION, Mitsubishi Electric Corporation
    Inventors: Kouichi Ohyama, Mitsunori Nishida, Osamu Nishizawa
  • Patent number: 10157834
    Abstract: An electronic apparatus is provided. The electronic apparatus includes an integrated fan-out package, a dielectric housing, and a plurality of conductive patterns. The dielectric housing is covering the integrated fan-out package, wherein a gap or a first dielectric layer is in between the dielectric housing and the integrated fan-out package. The plurality of conductive patterns is located on a surface of the dielectric housing, wherein the plurality of conductive patterns is located in between the dielectric housing and the integrated fan-out package.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tzu-Chun Tang, Chung-Hao Tsai, Chen-Hua Yu, Chuei-Tang Wang, Che-Wei Hsu
  • Patent number: 10141677
    Abstract: An electrical connector includes an insulating body, which has at least two body units. Each two body unit accommodates and is fixed with multiple terminals, and the at least two body units are spliced to each other. Each body unit has at least two edge portions, and the insulating body is provided with at least four fixing portions such that each of the edge portions is provided with at least one fixing portions. At least four metal members are correspondingly and fixedly provided on the at least four fixing portions respectively. At least two metal sheets are provided outside the at least two body units. Each metal sheet is soldered and fixed to at least one metal member provided on each body unit. By soldering and fixing the metal members and the metal sheets together, the overall structure of the electrical connector is firmer, and flatness is higher.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: November 27, 2018
    Assignee: LOTES CO., LTD
    Inventor: Ted Ju
  • Patent number: 10089568
    Abstract: An integrated circuit (IC) chip card includes a card body and an integrated IC chip module located in a recess provided by the card body on one side thereof. The IC chip module includes a substrate having outward-facing and inward-facing surfaces, and a first plurality of contact pads supportably interconnected to the outward-facing surface of the substrate for contact engagement with at least one appendage of a user. The IC chip module further includes a first IC chip supportably interconnected to the inward-facing surface of the substrate and electrically interconnected to the first plurality of contact pads for processing a biometric signal received therefrom.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: October 2, 2018
    Assignee: CPI CARD GROUP—COLORADO, INC.
    Inventor: Barry Mosteller
  • Patent number: 10043769
    Abstract: A semiconductor device includes an interposer having a first side and a second side opposite to the first side, at least one active chip mounted on the first side within a chip mounting area through a plurality of first bumps, at least one dummy chip mounted on the first side within a peripheral area being adjacent to the chip mounting area, a molding compound disposed on the first side. The molding compound covers the at least one active chip and the at least one dummy chip. A plurality of solder bumps is mounted on the second side.
    Type: Grant
    Filed: June 3, 2015
    Date of Patent: August 7, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Shing-Yih Shih, Neng-Tai Shih
  • Patent number: 9999132
    Abstract: An electronic package is provided, which includes: a substrate, an electronic element disposed on the substrate, and an antenna structure disposed on the substrate. The antenna structure has a base portion and at least a support portion, the base portion including a plurality of openings and a frame separating the openings from one another, and the support portion supporting the base portion over the substrate. Therefore, no additional area is required to be defined on a surface of the substrate, and the miniaturization requirement of the electronic package is thus met.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: June 12, 2018
    Assignee: Silicon Precision Industries Co., Ltd.
    Inventors: Chih-Hsien Chiu, Chia-Yang Chen, Ying-Wei Lu, Jyun-Yuan Jhang, Ming-Fan Tsai
  • Patent number: 9967511
    Abstract: Devices and methods for routing cables through a printed circuit board (PCB) include an enclosure having at least one cable guide and a cable duct. A PCB is mounted in the enclosure, such that the cable duct penetrates the PCB through a hole in the PCB. At least one additional component is mounted in the enclosure and connected to at least one cable that is attached to the at least one cable guide and the cable duct. The at least one cable enters the duct on a first side of the PCB and exits the duct on a second side of the PCB.
    Type: Grant
    Filed: September 18, 2014
    Date of Patent: May 8, 2018
    Assignee: THOMSON Licensing
    Inventors: Darin Bradley Ritter, Mickey Jay Hunt
  • Patent number: 9865530
    Abstract: An assembly comprises: at least one element that is capable of transmitting heat; at least one electrically insulating substrate comprising at least one film of a polymer that is a good thermal conductor and electrical insulator; at least one sintered metal joint that is in contact with the polymer film; a main radiator; the radiator being in direct contact, or in contact via a sintered joint, with the substrate.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: January 9, 2018
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventor: Rabih Khazaka
  • Patent number: 9847271
    Abstract: A semiconductor device includes: a processor having a heat sink mounted thereon; and an optical module having a heat transfer interposer, wherein the heat sink and the optical module are coupled to each other via the heat transfer interposer. And a semiconductor device includes: a semiconductor chip mounted on a substrate; a lead that covers the semiconductor chip; a heat sink installed on the lead; and an optical module coupled to the heat sink via a heat transfer interposer.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: December 19, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Yohei Miura, Yasushi Masuda, Satoshi Ohsawa, Yoshihiro Morita
  • Patent number: 9733676
    Abstract: A touch panel having a cover plate, a sensor electrode layer, an insulating layer and a jumper layer is provided. The sensor electrode layer has first axis electrodes, second axis electrodes, bonding pads and first periphery traces. Each first axis electrode has first electrode blocks that are electrically connected to each other. Each second axis electrode has second electrode blocks that are electrically isolated from each other. The bonding pads are disposed on the periphery region of the cover plate. The first periphery traces are electrically connected to the bonding pads and the first axis electrodes or the second axis electrodes respectively. The insulating layer has first via holes and second via holes. The jumper layer has jumper traces and second periphery traces, wherein the second periphery traces are electrically connected to the first axis electrodes or the second axis electrodes through the first via holes.
    Type: Grant
    Filed: February 16, 2014
    Date of Patent: August 15, 2017
    Assignee: TPK Touch Solutions Inc.
    Inventors: Jun-Yao Huang, Po-Pin Hung, Hsiang-Yu Teng, Chun-Chi Lin
  • Patent number: 9692187
    Abstract: An assembly of a cable connection apparatus and an electrical connector, includes a mating plug having an insulating body and multiple terminals, a circuit board having a notch depressed from an edge at a side of the circuit board toward a center direction of the circuit board and a metal conductor disposed in the notch or at an edge of the notch, and a cable having at least one conducting wire. The terminals are conducted to the circuit board. The conducting wire is inserted into the corresponding notch along a depression direction of the notch, and conducted to the metal conductor, thereby reducing the height of a soldering end of the conducting wire protruding from a surface of the circuit board. Thus, a metal casing outside the circuit board may wrap the circuit board without having a protruding portion for reserving the soldering end.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: June 27, 2017
    Assignee: LOTES CO., LTD
    Inventor: Jian Cheng Qian
  • Patent number: 9625956
    Abstract: A touch panel having a cover plate, a sensor electrode layer, an insulating layer and a jumper layer is provided. The sensor electrode layer has first axis electrodes, second axis electrodes, bonding pads and first periphery traces. Each first axis electrode has first electrode blocks that are electrically connected to each other. Each second axis electrode has second electrode blocks that are electrically isolated from each other. The bonding pads are disposed on the periphery region of the cover plate. The first periphery traces are electrically connected to the bonding pads and the first axis electrodes or the second axis electrodes respectively. The insulating layer has first via holes and second via holes. The jumper layer has jumper traces and second periphery traces, wherein the second periphery traces are electrically connected to the first axis electrodes or the second axis electrodes through the first via holes.
    Type: Grant
    Filed: February 16, 2014
    Date of Patent: April 18, 2017
    Assignee: TPK Touch Solutions Inc.
    Inventors: Jun-Yao Huang, Po-Pin Hung, Hsiang-Yu Teng, Chun-Chi Lin
  • Patent number: 9585252
    Abstract: An electronic device connection unit includes a substrate and a plurality of signal pads on the substrate configured to send signals from an electronic device to a driving printed circuit board (PCB). One or more active ground pads on the substrate are configured to connect at least the driving PCB to a reference voltage of the electronic device. One or more dummy ground pads on the substrate are configured to connect to the reference voltage of the electronic device without extending onto the driving PCB. One or more connectors are connected to the one or more dummy ground pads, where each of the one or more connectors is configured to electrically couple at least a subset of the one or more dummy ground pads to the one or more active ground pads.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: February 28, 2017
    Assignee: LG Display Co., Ltd.
    Inventors: InHo Yeo, KyongShik Jeon
  • Patent number: 9570238
    Abstract: An ultra-wideband assembly is provided. The assembly includes a non-conductive tapered core having a conductive wire wound on an outer surface of the non-conductive tapered core, a low-frequency inductor coupled to the non-conductive tapered core via the distal end of the conductive wire and configured to allow mounting of the non-conductive tapered core at an angle with respect to the circuit board. The low frequency inductor is being disposed on a dielectric board configured to be coupled to the circuit board. The assembly includes an ultra-wideband capacitor coupled to the non-conductive tapered core via the proximate end of the conductive wire, the ultra-wideband capacitor being also coupled to the transmission line on the dielectric board.
    Type: Grant
    Filed: July 28, 2014
    Date of Patent: February 14, 2017
    Assignee: American Technical Ceramics Corp.
    Inventor: John Mruz
  • Patent number: 9553059
    Abstract: An embodiment package on package (PoP) device includes a molding compound having a metal via embedded therein, a passivation layer disposed over the molding compound, the passivation layer including a passivation layer recess vertically aligned with the metal via, and a redistribution layer bond pad capping the metal via, a portion of the redistribution layer bond pad within the passivation layer recess projecting above a top surface of the molding compound.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: January 24, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Hao Tsai, Jing-Cheng Lin
  • Patent number: 9536818
    Abstract: A method of a semiconductor package includes providing a substrate having a conductive trace coated with an organic solderability preservative (OSP) layer, removing the OSP layer from the conductive trace, and then coupling a chip to the substrate to form a semiconductor package.
    Type: Grant
    Filed: October 13, 2011
    Date of Patent: January 3, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Hung Lin, Ming-Da Cheng, Chung-Shi Liu, Mirng-Ji Lii, Chen-Hua Yu
  • Patent number: 9508636
    Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for dual surface finish package substrate assemblies. In one embodiment a method includes depositing a first lamination layer on a first side of a package substrate and a first surface finish on one or more electrical contacts disposed on a second side of the package substrate; removing the first lamination layer from the first side of the package substrate; depositing a second lamination layer on the second side of the package substrate and a second surface finish on the one or more electrical contacts disposed on the first side of the package substrate; and removing the second lamination layer from the second side of the package substrate. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: October 16, 2013
    Date of Patent: November 29, 2016
    Assignee: INTEL CORPORATION
    Inventors: Qinglei Zhang, Stefanie M. Lotz
  • Patent number: 9502469
    Abstract: An integrated interposer may include a substrate and a resistive-type non-volatile memory (NVM) array(s). The integrated interposer may also include a contact layer on a first surface of the substrate. The contact layer may include interconnections configured to couple the resistive-type NVM array(s) to a die(s). The resistive-type NVM array(s) may be partially embedded within the contact layer of the integrated interposer.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: November 22, 2016
    Assignee: QUALCOMM INCORPORATED
    Inventors: Yu Lu, Vidhya Ramachandran, Seung Hyuk Kang