With Mounting Pad Patents (Class 361/767)
  • Patent number: 11372175
    Abstract: An optical module includes a wiring board having a first electrode, an optical waveguide provided on the wiring board, an optical element having a second electrode and provided on the optical waveguide, a conductive bonding material bonding the first and second electrodes, and a fixing member that fixes the optical element to the optical waveguide. The optical waveguide includes a core layer, a first cladding layer provided on a first side of the core layer, a second cladding layer provided on a second side of the core layer opposite to the first side, and an optical path conversion mirror provided on the core layer or the second cladding layer. The optical element is optically coupled to one end of the core layer via the optical path conversion mirror, and a softening point of the fixing member is higher than a melting point of the conductive bonding material.
    Type: Grant
    Filed: November 18, 2020
    Date of Patent: June 28, 2022
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Kenji Yanagisawa, Koichi Toya
  • Patent number: 11373951
    Abstract: Embodiments include a package structure with one or more layers of dielectric material, where an interconnect bridge substrate is embedded within the dielectric material. One or more via structures are on a first surface of the embedded substrate, where individual ones of the via structures comprise a conductive material and have a tapered profile. The conductive material is also on a sidewall of the embedded substrate.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: June 28, 2022
    Assignee: Intel Corporation
    Inventors: Jeremy D. Ecton, Hiroki Tanaka, Oscar Ojeda, Arnab Roy, Vahidreza Parichehreh, Leonel R. Arana, Chung Kwang Tan, Robert A. May
  • Patent number: 11350525
    Abstract: A method is provided for mounting a semiconductor IC to a substrate without a socket or solder. The method includes disposing a guide structure on the substrate. The substrate has multiple contact pads disposed thereon. The substrate also has multiple nuts formed therein for connecting to one or more bolts. The method also includes placing the semiconductor IC inside the guide structure such that the semiconductor IC makes contact with the contact pads. A top plate is disposed on the semiconductor IC. Further, the top plate and the semiconductor IC are fastened to the substrate.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: May 31, 2022
    Assignee: NUVOTON TECHNOLOGY CORPORATION
    Inventor: Simon Wilson
  • Patent number: 11330743
    Abstract: An electronic device is provided. The electronic device includes a display panel, a metal layer disposed on a surface of the display panel, a display driver integrated circuit (DDI) disposed on a surface of the metal layer, a bending part connecting the display panel to the DDI, and a cover member connected to the metal layer while covering the DDI. The cover member includes at least one conductive layer. The metal layer and the cover member form a space in which the DDI is disposed, and the bending part is connected to the DDI via a connection part in the space.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: May 10, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyunjun Park, Seonghoon Kim, Hongkook Lee, Donghwy Kim, Jongkon Bae, Dongkyoon Han
  • Patent number: 11310913
    Abstract: The invention relates to a semiconductor component (2), comprising a semiconductor chip (3), a housing (5) and a connection point arrangement (10) having at least two rows (14, 16) of planar connection points (12), which are arranged on a bottom side of the housing (5) and can be electrically connected by means of connections to corresponding contacts of a contact arrangement having at least two rows, which contact arrangement is arranged on a printed circuit board, wherein the geometry of the contact arrangement corresponds to the geometry of the connection point arrangement (10), a first distance is specified between two adjacent first connection points (14A) of a first row (14) of the connection point arrangement (10) and a second distance is specified between two adjacent second connection points (16A) of a second row (16) of the connection point arrangement (10), and the second connection points (16A) of the second row (16) are offset to the first connection points (14A) of the first row (14).
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: April 19, 2022
    Assignee: Robert Bosch GmbH
    Inventors: Guenter Gera, Klaus Kosbi, Lars Vollmer, Matthias Lausmann
  • Patent number: 11302656
    Abstract: An integrated circuit (IC) package is described. The IC package includes a package substrate, composed of a substrate core, a first power rail on a first surface of the substrate core, and a second power rail on a second surface of the substrate core. The IC package includes a logic die supported by the second power rail on the second surface of the substrate core. The IC package includes passive devices within the substrate core. Each of the passive devices has a first terminal and a second terminal opposite the first terminal. The first terminal of each of the passive devices is directly coupled to the first power rail, and the second terminal of each of the plurality of the passive devices is directly coupled to the second power rail. The IC package includes package bumps on the second power rail on the second surface of the substrate core.
    Type: Grant
    Filed: July 24, 2020
    Date of Patent: April 12, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Hong Bok We, Aniket Patil, Joan Rey Villarba Buot, Zhijie Wang
  • Patent number: 11296051
    Abstract: Semiconductor packages and methods of forming the same are provided. One of the semiconductor packages includes a first semiconductor die, an adhesive layer, a second semiconductor die and an underfill. The first semiconductor die includes a first surface, and the first surface includes a central region and a peripheral region surrounding the central region. The adhesive layer is adhered to the peripheral region and exposes the central region. The second semiconductor die is stacked over the first surface of the first semiconductor die. The underfill is disposed between the first semiconductor die and the second semiconductor die.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: April 5, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Fu Kao, Chih-Yuan Chien, Li-Hui Cheng, Szu-Wei Lu
  • Patent number: 11278224
    Abstract: This application features a method of forming a nanoporous layer. The method includes steps of reducing metal ions in a reverse micelle phase composition to form nanoparticles, removing surfactant from the composition to form clusters of the nanoparticles, dispensing the composition including the nanoparticle clusters dispersed in a liquid on a substrate, and drying to form the nanoporous layer. The nanoporous layer includes nanoparticles deposited to form a three dimensional network of irregularly shaped bodies. The nanoporous layer also includes a three dimensional network of intercluster spaces that are not occupied by the three dimensional network of irregularly shaped bodies.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: March 22, 2022
    Assignee: UXN Co., Ltd.
    Inventors: Hankil Boo, Rae Kyu Chang
  • Patent number: 11270976
    Abstract: A package structure and a method of manufacturing the same are provided. The package structure includes a first die, a second die, a first encapsulant, a bridge, an underfill layer and a RDL structure. The first die and the second die are placed side by side. The first encapsulant encapsulates sidewalls of the first die and sidewalls of the second die. The bridge electrically connects the first die and the second die through two conductive bumps. The underfill layer fills the space between the bridge and the first die, between the bridge and the second die, and between the bridge and a portion of the first encapsulant. The RDL structure is located over the bridge and electrically connected to the first die and the second die though a plurality of TIVs. The bottom surfaces of the two conductive bumps are level with a bottom surface of the underfill layer.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: March 8, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu-Hang Liao, Chih-Wei Wu, Jing-Cheng Lin, Szu-Wei Lu, Ying-Ching Shih
  • Patent number: 11249112
    Abstract: A testing apparatus with reduced warping of the probe card and a method of reducing warping of a probe card of a testing apparatus are disclosed. The testing apparatus can include a testing head and a platform opposite the testing head, where the testing head and platform move relative to one another to bring a sample into contact with probing tips of the testing apparatus. The testing head can include a probe card printed circuit board, a stiffener, a discontinuous backer and a plurality of probing tips. The stiffener can be coupled to and reinforcing the probe card. The discontinuous backer can extend from the probe card to the stiffener, and can include at least one unfilled void extending from the stiffener to the probe card. The plurality of probing tips can extend from a distal end of the testing head.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: February 15, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Mill-Jer Wang, Ching-Nen Peng, Hung-Chih Lin, Wei-Hsun Lin, Sen-Kuei Hsu, De-Jian Liu
  • Patent number: 11233017
    Abstract: An integrated circuit package includes a first conductive element that is fabricated as part of the integrated circuit package and a micro-wire having a first end coupled to the first conductive element. The micro-wire has been fabricated ex-situ and is of a metal having a diameter of 10 microns or less.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: January 25, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Michael Lee Dawson, Edward J. Pryor, III, Jeffrey L. Large, Mary Coles
  • Patent number: 11199515
    Abstract: A gas sensor device includes a package including a cap in which a through hole for taking gas is formed and a base in which a recessed portion is formed. The cap is attached to the base so that a space is defined around the recessed portion. The device includes metal electrodes fixed to portions surrounding the recessed portion and embedded in the base. The device includes a gas detecting element, which includes a gas detector having a coil-shaped heater that is heated when detecting a predetermined gas, and a plurality of metal lead wires extending from the gas detector to the electrodes. The gas detecting element is held in a suspended state in the recessed portion and/or a space above the recessed portion with the plurality of lead wires, so that the gas detecting element, which includes the heater, does not make contact with walls of the recessed portion.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: December 14, 2021
    Assignee: NISSHA CO., LTD.
    Inventors: Yuki Ura, Muneharu Shimabukuro, Shinichi Matsumoto
  • Patent number: 11201119
    Abstract: A component carrier including i) an electronic component embedded in the component carrier, ii) an antenna structure arranged at a region of a first main surface of the component carrier, iii) a shielding structure made of an electrically conductive material and configured for shielding electromagnetic radiation from propagating between the antenna structure and the electronic component. Hereby, the shielding structure is arranged at least partially between the antenna structure and the electronic component. Furthermore, the component carrier includes an electrically conductive structure to electrically connect the electronic component and the antenna structure through the shielding structure. The shielding structure is non-perforated at least in a plane between the antenna structure and the electronic component.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: December 14, 2021
    Assignee: AT&S Austria Technologie & Systemtechnik Aktiengesellschaft
    Inventors: Markus Leitgeb, Martin Schrems, Erich Schlaffer, Steve Anderson
  • Patent number: 11189557
    Abstract: A method of manufacturing a hybrid package including a flat package and a Wafer Level Chip Scale Package (WLCSP) is disclosed. The method includes fabricating a strip including a plurality of flat packages attached to each other via metal pins, turning the strip upside down, applying a layer of a thermal interface material (TIM) on each of the flat packages while the each of the flat packages is turned upside down, mounting the WLCSP on the layer of the TIM such that a top side of the WLCSP is interfaced with the layer of the TIM, curing the layer of the TIM and singulating each of the flat packages by cutting the metal pins and bending the metal pins.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: November 30, 2021
    Assignee: NXP USA, INC.
    Inventors: Akhilesh Kumar Singh, Nishant Lakhera, Chee Seng Foong
  • Patent number: 11177230
    Abstract: An electronic device includes a substrate and first bumps. The first bumps are disposed on the substrate and arranged in a first bump row. Each first bump has a first end and a second end opposite to each other. Centers of the first ends of the first bumps are on a first axial line. A first axial coordinate of a center of the second end of a respective first bump relative to a second axial line perpendicular to the first axial line is XA(1+?AYA), in which XA is a first axial coordinate of the center of the first end of the respective first bump relative to the second axial line, YA is a second axial coordinate of the center of the second end of the respective first bump relative to the first axial line, and ?A is a slope coefficient of the respective first bump.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: November 16, 2021
    Assignee: NOVATEK Microelectronics Corp.
    Inventors: Hsien-Wen Lo, Chang-Sheng Tseng
  • Patent number: 11145587
    Abstract: An electronic component mounting substrate includes: an insulating substrate having a recess that opens in a main surface of the insulating substrate, the recess for mounting an electronic component; a metal layer located on a bottom surface of the recess; an external electrode located on the other main surface of the insulating substrate, the other main surface opposite to the main surface; a connection wiring located between the metal layer and the external electrode in a thickness direction of the insulating substrate; a plurality of first vias that connects the metal layer and the connection wiring and that is located along a side wall of the recess in a perspective plan view; and a plurality of second vias that connects the connection wiring and the external electrode and that is located in a strip shape in the perspective plan view.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: October 12, 2021
    Assignee: KYOCERA CORPORATION
    Inventors: Yuuki Baba, Yousuke Moriyama
  • Patent number: 11128073
    Abstract: A plug connector for establishing an external connection to a printed circuit board, including at least two angled pin-shaped contacts including a first leg, for making contact with a mating plug connector, and a second leg, for making contact with the printed circuit board, an insulating body for accommodating the contacts at least in the region of the first leg, and a contact carrier for accommodating the contacts at the second leg thereof, wherein the contacts, at the end of the second leg, include a stop acting in the axial direction, and the contact carrier includes through-openings including a counter-stop for the second legs and can be moved in the axial direction of the second legs into a housing and be fixed therein. In this way, all the contacts are located on one plane with respect to the printed circuit board and allow the use of SMD or THR processes.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: September 21, 2021
    Assignee: PHOENIX CONTACT GmbH & Co. KG
    Inventors: Alexander Hieber, Michael Delker
  • Patent number: 11115020
    Abstract: A signal transmission device includes a first lead frame supporting a signal transmission chip that includes first and second inductor spiral rings, a first bonding pad electrically coupled between the first and second inductor spiral rings, and a guard ring provided to roundly cover the first and second inductor spiral rings in a plan view. Bonding pads are provided outside of the guard ring. A direction of rotation between the first and second inductor spiral rings are different from each other so that the first and second inductor spiral rings are disposed substantially symmetrically about the first bonding pad. A second lead frame supports a semiconductor chip, with the signal transmission chip and the semiconductor chip facing each other.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: September 7, 2021
    Assignee: Rohm Co., Ltd.
    Inventors: Daiki Yanagishima, Toshiyuki Ishikawa, Hirotaka Takihara
  • Patent number: 11094614
    Abstract: A semiconductor device structure may include a semiconductor device, disposed at least in part in a semiconductor substrate, and a first insulator layer, disposed on a surface of the semiconductor device, and comprising a first contact aperture, disposed within the first insulator layer. The semiconductor device structure may also include a first contact layer, comprising a first electrically conductive material, disposed over the insulator layer, and being in electrical contact with the semiconductor device through the first contact aperture, and a second insulator layer, disposed over the first contact layer, wherein the second insulator layer further includes a second contact aperture, displaced laterally from the first contact aperture, by a first distance.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: August 17, 2021
    Assignee: Littelfuse, Inc.
    Inventor: Stefan Steinhoff
  • Patent number: 11094637
    Abstract: A multi-chip package structure includes a chip interconnect bridge, a fan-out redistribution layer structure, a first integrated circuit chip, and a second integrated circuit chip. The chip interconnect bridge includes contact pads disposed on a top-side of the chip interconnect bridge. The fan-out redistribution layer structure is disposed around sidewalls of the chip interconnect bridge and over the top-side of the chip interconnect bridge. The first and second integrated circuit chips are direct chip attached to an upper surface of the fan-out redistribution layer structure, wherein the fan-out redistribution layer structure includes input/output connections between the contact pads on the top-side of the chip interconnect bridge and the first and second integrated circuit chips.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: August 17, 2021
    Assignee: International Business Machines Corporation
    Inventors: Joshua M. Rubin, Steven Lorenz Wright, Lawrence A. Clevenger
  • Patent number: 11073573
    Abstract: An apparatus comprises a first substrate and two coils supported by the first substrate and arranged next to each other, the coils configured to each generate a magnetic field which produces eddy currents in and a reflected magnetic field from a conductive target, the two coils arranged so their respectively generated magnetic fields substantially cancel each other in an area between the coils. One or more magnetic field sensing elements are positioned in the area between the coils and configured to detect the reflected magnetic field.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: July 27, 2021
    Assignee: Allegro MicroSystems, LLC
    Inventors: Alexander Latham, Michael C. Doogue, Jason Boudreau
  • Patent number: 11069539
    Abstract: Embodiments of the present disclosure include a semiconductor device and methods of forming a semiconductor device. An embodiment is a semiconductor device comprising an interconnecting structure consisting of a plurality of thin film layers and a plurality of metal layers disposed therein, each of the plurality of metal layers having substantially a same top surface area, and a die comprising an active surface and a backside surface opposite the active surface, the active surface being directly coupled to a first side of the interconnecting structure. The semiconductor device further comprises a first connector directly coupled to a second side of the interconnecting structure, the second side being opposite the first side.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: July 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Wei Chiu, Cheng-Hsien Hsieh, Hsien-Pin Hu, Kuo-Ching Hsu, Shang-Yun Hou, Shin-Puu Jeng
  • Patent number: 11031446
    Abstract: An electronic device includes a substrate; and a pad area on the substrate, the pad area including: a first pad part including a first pad terminal; a second pad part on a side of the first pad part in a first direction and including a second pad terminal; and a third pad part on the other side of the first pad part in the first direction and including a third pad terminal, each of the first pad terminal, the second pad terminal and the third pad terminal including a first long side, a second long side facing the first long side, and at least one bridge extending from the first long side to the second long side, the first long side of the first pad terminal extending in a second direction intersecting the first direction.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: June 8, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jung Yun Jo, Ki Kyung Youk
  • Patent number: 11031366
    Abstract: An electronic component package includes a substrate and an electronic component mounted to the substrate, the electronic component including a bond pad. A first antenna terminal is electrically connected to the bond pad, the first antenna terminal being electrically connected to a second antenna terminal of the substrate. A package body encloses the electronic component, the package body having a principal surface. An antenna is formed on the principal surface by applying an electrically conductive coating. An embedded interconnect extends through the package body between the substrate and the principal surface and electrically connects the second antenna terminal to the antenna. Applying an electrically conductive coating to form the antenna is relatively simple thus minimizing the overall package manufacturing cost. Further, the antenna is relatively thin thus minimizing the overall package size.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: June 8, 2021
    Assignee: Amkor Technology Singapore Pte. Ltd.
    Inventors: Jong Ok Chun, Nozad Karim, Richard Chen, Giuseppe Selli, Michael Kelly
  • Patent number: 10993325
    Abstract: Interposer printed circuit boards for power modules and associated methods are disclosed. In at least one illustrative embodiment, a printed circuit board assembly may comprise a printed circuit board having a surface, an electrical component mounted on the surface, a pin mounted on the surface, and an interposer printed circuit board mounted on the surface. The electrical component may have a first height orthogonal to the surface. The pin may have a second height orthogonal to the surface, where the second height is greater than the first height. The interposer printed circuit board may comprise a pad and an outer solder bump positioned on the pad. The outer solder bump may have a third height orthogonal to the surface, where the third height is greater than the first height.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: April 27, 2021
    Assignee: ABB Power Electronics Inc.
    Inventors: John Andrew Trelford, Richard John Yeager, Alok Kumar Lohia, Thang Danh Truong
  • Patent number: 10993321
    Abstract: A wiring substrate has a substrate body formed by a single or a plurality of insulating layers and having front and back surfaces located at opposite sides of the substrate body; a plurality of pads formed on at least one of the front surface, the back surface and an inner layer surface that is located between the front and back surfaces, and having a staggered arrangement in plan view; and a plurality of via conductors formed at each of the pads, extending in a thickness direction of the substrate body with the plurality of via conductors being parallel to each other and connecting the pads located on different surfaces. Arrangement, in plan view, of the plurality of via conductors connecting to the pad and arrangement, in plan view, of the plurality of via conductors connecting to an adjacent pad located on the same surface are different from each other.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: April 27, 2021
    Assignee: NGK SPARK PLUG CO., LTD.
    Inventor: Takahiro Hayashi
  • Patent number: 10986730
    Abstract: Substrates configured to route electrical signals may include a first dielectric material and an electrically conductive material located on a first side of the first dielectric material. A second dielectric material may be located on a second, opposite side of the first dielectric material. A series of voids may be defined by the second dielectric material extending from the first dielectric material at least partially through the second dielectric material. Footprints of at least some of the voids of the series of voids may at least partially laterally overlap with the electrically conductive material.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: April 20, 2021
    Assignee: Microsemi Semiconductor ULC
    Inventors: Nasser Ghassemi, Mehran Aliahmad
  • Patent number: 10984965
    Abstract: The present description relates to a fully biodegradable supercapacitor and a method for manufacturing the same. When the fully biodegradable supercapacitor and the method for manufacturing the same according to the present description are used, supercapacitor having high capacitance, high energy, and high output is provided by forming a metal oxide on a metal electrode and a surface of a solid electrolyte. In addition, the present description is environment-friendly, biodegradable, and biocompatible to be implanted into a body, and may be a bio-implantable energy storage device in the future.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: April 20, 2021
    Assignee: Korea University Research and Business Foundation
    Inventors: Jeong Sook Ha, Geumbee Lee, Yu Ra Jeong
  • Patent number: 10980132
    Abstract: LEDs for an illumination system may be mounted on a PCB. The PCB may be provided with alignment features such as oversized holes for connection to a support surface. Using optical sensing of the position of the mounted LEDs, the space made available by the alignment features may be reduced and aligned to create modified alignment features. The modified alignment features may be created by adding a modifying component and aligned based on the sensed positions of the mounted LEDs. The positioning of the modifying component may offset misalignment of the LEDs with the PCB. An opening in the modified alignment feature may receive a bolt or alignment pin for connection to the support surface. The support surface may be aligned with the secondary optics, resulting in the LEDs being aligned with the secondary optics irrespective of misalignment of the LEDs with respect to the PCB.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: April 13, 2021
    Assignee: Lumileds LLC
    Inventor: Axel Mehnert
  • Patent number: 10931009
    Abstract: Aspects of this disclosure relate to methods of selectively shielded radio frequency modules. A radio frequency module can be provided with a radio frequency component and an antenna. A shielding layer can be formed over a portion of the radio frequency module such that the radio frequency component is shielded by the shielding layer and the antenna is unshielded by the shielding layer.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: February 23, 2021
    Assignee: Skyworks Solutions, Inc.
    Inventors: Hoang Mong Nguyen, Anthony James LoBianco, Gregory Edward Babcock, Darren Roger Frenette, George Khoury
  • Patent number: 10925151
    Abstract: Systems and methods for providing a PWB. The methods comprise: forming a Core Substrate (“CS”) a First Via (“FV”) formed therethrough; disposing a First Trace (“FT”) on an exposed surface of CS that is in electrical contact with FV; laminating a first HDI substrate to CS such that FT electrically connects FV via with a Second Via (“SV”) formed through the first HDI substrate; disposing a Second Trace (“ST”) on an exposed surface of the first HDI substrate that is in electrical contact with SV; and laminating a second HDI substrate to the first HDI substrate such that ST electrically connects SV to a Third Via (“TV”) formed through the second HDI substrate. SV comprises a buried via with a central axis spatially offset from central axis of FV and SV. FV and SV have diameters which are smaller than TV's diameter.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: February 16, 2021
    Assignee: EAGLE TECHNOLOGY, LLC
    Inventors: Michael T. DeRoy, Marvin D. Miller, Andres M. Gonzalez, David Cure, Tena M. Hochard
  • Patent number: 10896884
    Abstract: A semiconductor package includes a frame having a first through-hole, a semiconductor chip having an active surface on which a connection pad is disposed; a first encapsulant encapsulating at least a portion of the semiconductor chip; a second encapsulant disposed on at least a portion of the external side surface of the frame, and a connection member disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pad of the semiconductor chip. The frame includes an insulating layer, a wiring layer disposed on upper and lower surfaces of the insulating layer, a first metal layer on the external side wall of the insulating layer, a second metal layer on the internal side wall of the first through hole, and a via penetrating the upper and lower surfaces of the insulating layer.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: January 19, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yong Koon Lee, Jin Su Kim
  • Patent number: 10861785
    Abstract: An electronic module includes an electronic part including a bottom surface and lands, the bottom surface including a first region and a third region surrounding the first region, the first lands being disposed in the third region, a printed wiring board including a main surface and second lands, the main surface including a second region and a fourth region surrounding the second region, the main surface facing the bottom surface of the electronic part, the second lands being disposed in the fourth region, solder bonding portions respectively bonding the first lands to the second lands, and a resin portion containing a cured product of a thermosetting resin and being in contact with the solder boding portions. A recess portion is provided in the second region. The resin portion is not provided in the recess portion.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: December 8, 2020
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Shingo Ishiguri, Mitsutoshi Hasegawa, Kunihiko Minegishi, Takashi Sakaki
  • Patent number: 10832830
    Abstract: The present invention provides an anisotropic electrically conductive film with a structure, in which electrically conductive particles are disposed at lattice points of a planar lattice pattern in an electrically insulating adhesive base layer. A proportion of the lattice points, at which no electrically conductive particle is disposed, with respect to all the lattice points of the planar lattice pattern assumed as a reference region, is less than 20%. A proportion of the lattice points, at which plural electrically conductive particles are disposed in an aggregated state, with respect to all the lattice points of the planar lattice pattern, is not greater than 15%. A sum of omission of the electrically conductive particle and an aggregation of the electrically conductive particles is less than 25%.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: November 10, 2020
    Assignee: DEXERIALS CORPORATION
    Inventors: Tomoyuki Ishimatsu, Reiji Tsukao
  • Patent number: 10818578
    Abstract: A method of manufacturing semiconductor devices such as integrated circuits comprises: providing one or more semiconductor chips having first and second opposed surfaces, coupling the semiconductor chip or chips with a support substrate with the second surface towards the support substrate, embedding the semiconductor chip or chips coupled with the support substrate in electrically-insulating packaging material by providing in the packaging material electrically-conductive passageways. The electrically-conductive passageways comprise: electrically-conductive chip passageways towards the first surface of the at least one semiconductor chip, and/or electrically-conductive substrate passageways towards the support substrate.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: October 27, 2020
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Michele Derai, Federico Giovanni Ziglioli
  • Patent number: 10782319
    Abstract: A probe card for testing of electronic devices comprises a testing head with plural contact probes inserted into guide holes of an upper guide and a lower guide, and a space transformer, each of the contact probes having a first terminal portion projecting from the lower guide with a first length and ending with a contact tip adapted to abut onto a respective contact pad of a device to be tested, and a second terminal portion projecting from the upper guide with a second length and ending with a contact head adapted to abut onto a contact pad of the space transformer. The probe card comprises a spacer element interposed between the space transformer and the upper guide and removable to adjust the first length of the first terminal portion by changing the second length of the second terminal portion and approaching the upper guide and the space transformer.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: September 22, 2020
    Assignee: TECHNOPROBE S.P.A.
    Inventors: Roberto Crippa, Stefano Felici
  • Patent number: 10770387
    Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for dual surface finish package substrate assemblies. In one embodiment a method includes depositing a first lamination layer on a first side of a package substrate and a first surface finish on one or more electrical contacts disposed on a second side of the package substrate; removing the first lamination layer from the first side of the package substrate; depositing a second lamination layer on the second side of the package substrate and a second surface finish on the one or more electrical contacts disposed on the first side of the package substrate; and removing the second lamination layer from the second side of the package substrate. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: September 8, 2020
    Assignee: INTEL CORPORATION
    Inventors: Qinglei Zhang, Stefanie M. Lotz
  • Patent number: 10687746
    Abstract: This application features a method of forming a nanoporous layer. The method includes steps of reducing metal ions in a reverse micelle phase composition to form nanoparticles, removing surfactant from the composition to form clusters of the nanoparticles, dispensing the composition including the nanoparticle clusters dispersed in a liquid on a substrate, and drying to form the nanoporous layer. The nanoporous layer includes nanoparticles deposited to form a three dimensional network of irregularly shaped bodies. The nanoporous layer also includes a three dimensional network of intercluster spaces that are not occupied by the three dimensional network of irregularly shaped bodies.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: June 23, 2020
    Assignee: UXN CO., LTD.
    Inventors: Hankil Boo, Rae Kyu Chang
  • Patent number: 10660206
    Abstract: An information handling system (IHS) has a circuit board assembly with a dual-sided interposer substrate that is inserted between a baseboard and a processor integrated circuit having a second pattern of electrical contacts. The dual interposer substrate formed of a stack of printed circuit boards (PCBs) provides communication channels between a first coupling pad on the baseboard that has a first pattern of electrical contacts and a second coupling pad on top of the dual interposer substrate that provides the second pattern of electrical contacts. The second pattern receives another type of processor integrated circuit than a type supported by the first pattern. Stacked vias formed through the stack of PCBs electrically connect respective electrical contacts of the first and second coupling pads to form a corresponding communication channel. One or more grounded vias mitigate signal integrity (SI) anomalies on the communication channels.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: May 19, 2020
    Assignee: Dell Products, L.P.
    Inventors: Kevin W. Mundt, Sandor Farkas, Bhyrav M. Mutnury, Yeshaswy Rajupalepu
  • Patent number: 10629094
    Abstract: A module assembly includes a device. The device comprises a base structure and a flat planar top surface located at an upper portion of the base structure. The module assembly further includes an electrical source coupled to the base structure of the module to provide power to the device. A plurality of components is coupled to the device at the top surface. Each component of the plurality of components is coupled to the electrical source and the plurality of components combine to purpose a particular technical function. A module system comprises at least two module assemblies coupled together. The module system may purpose a combined technical function.
    Type: Grant
    Filed: July 1, 2014
    Date of Patent: April 21, 2020
    Assignee: Northeast Wisconsin Technical College
    Inventors: Joseph John Barker, Edward Francis Kralovec, Troy A. Giese, Jacob D. Morois
  • Patent number: 10615109
    Abstract: A substrate includes a first dielectric layer having a first surface and a second dielectric layer having a first surface disposed adjacent to the first surface of the first dielectric layer. The substrate further includes a first conductive via disposed in the first dielectric layer and having a first end adjacent to the first surface of the first dielectric layer and a second end opposite the first end. The substrate further includes a second conductive via disposed in the second dielectric layer and having a first end adjacent to the first surface of the second dielectric layer. A width of the first end of the first conductive via is smaller than a width of the second end of the first conductive via, and a width of the first end of the second conductive via is smaller than the width of the first end of the first conductive via.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: April 7, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Cheng-Lin Ho, Chih-Cheng Lee
  • Patent number: 10582864
    Abstract: A measurement sensor package and a measurement sensor improve reliability in strength and other aspects. A measurement sensor package includes a substrate, a lid, a ground conductor layer, a metallic thin layer, and a bond. The ground conductor layer and the metallic thin layer are arranged inside the bond that extends continuously as viewed through from above. The bond directly bonds a first main surface of a substrate body and a facing surface of the lid together along the entire periphery. This improves the reliability in strength.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: March 10, 2020
    Assignee: KYOCERA CORPORATION
    Inventors: Yasushi Oode, Hiroki Ito, Yoshimasa Sugimoto, Noritaka Niino, Shogo Matsunaga, Takuya Hayashi
  • Patent number: 10566108
    Abstract: The present invention provides an anisotropic electrically conductive film with a structure, in which electrically conductive particles are disposed at lattice points of a planar lattice pattern in an electrically insulating adhesive base layer. A proportion of the lattice points, at which no electrically conductive particle is disposed, with respect to all the lattice points of the planar lattice pattern assumed as a reference region, is less than 20%. A proportion of the lattice points, at which plural electrically conductive particles are disposed in an aggregated state, with respect to all the lattice points of the planar lattice pattern, is not greater than 15%. A sum of omission of the electrically conductive particle and an aggregation of the electrically conductive particles is less than 25%.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: February 18, 2020
    Assignee: DEXERIALS CORPORATION
    Inventors: Tomoyuki Ishimatsu, Reiji Tsukao
  • Patent number: 10559538
    Abstract: A power module of the invention includes a power semiconductor element mounted on a circuit board, and an adapter connected to a front-surface main electrode of the element, wherein the adapter includes a main-electrode wiring member which is connected to the front-surface main electrode of the element; and wherein the main-electrode wiring member includes: an element connection portion connected to the front-surface main electrode of the element; a board connection portion which is placed outside the element connection portion and connected to the circuit board; and a connector connection portion which is placed outside the element connection portion and connected to an external electrode through a connector.
    Type: Grant
    Filed: February 9, 2016
    Date of Patent: February 11, 2020
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Junji Fujino, Shohei Ogawa, Soichi Sakamoto
  • Patent number: 10537016
    Abstract: The present disclosure relates to systems and methods using thermal vias to increase the current-carrying capacity of conductive traces on a multilayered printed circuit board (PCB). In various embodiments, parameters associated with vias may be selected to control various electrical and thermal properties of the conductive trace. Such parameters include the via diameter, a plating thickness, a number of vias, a placement of the vias, an amount of conductive material to be added or removed from the conductive trace, a change in the resistance of the conductive trace, a change in a fusing measurement of the conductive trace, and the like.
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: January 14, 2020
    Assignee: Schweitzer Engineering Laboratories, Inc.
    Inventors: Travis C. Mallett, Ben M. Armstrong, Forrest A. Rahrer
  • Patent number: 10499163
    Abstract: A microphone assembly including a main board and a microphone. The microphone includes a capacitor or a MEMS chip, a case accommodating the capacitor or the MEMS chip, and a microphone board electrically connected to the capacitor or the MEMS chip. The microphone board has a larger outer dimension than the case and includes a fixing portion and a connecting portion. The case is fixed onto the fixing portion. The connecting portion is a portion of the microphone board, the portion being located outside the case and electrically and mechanically connected to the main board.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: December 3, 2019
    Assignee: HOSIDEN CORPORATION
    Inventors: Naosuke Fukada, Mayumi Kaneko, Ryuji Awamura, Hidenori Motonaga, Kensuke Nakanishi
  • Patent number: 10468374
    Abstract: Examples relate to a die interconnect substrate comprising a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate further comprises a substrate structure comprising a substrate interconnect electrically insulated from the bridge die, wherein the bridge die is embedded in the substrate structure. The die interconnect substrate further comprises a first interface structure for attaching a semiconductor die to the substrate structure, wherein the first interface structure is connected to the first bridge die pad. The die interconnect substrate further comprises a second interface structure for attaching a semiconductor die to the substrate structure, wherein the second interface structure is connected to the substrate interconnect. A surface of the first interface structure and a surface of the second interface structure are at the same height.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: November 5, 2019
    Assignee: Intel Corporation
    Inventors: Rahul Jain, Ji Yong Park, Kyu Oh Lee
  • Patent number: 10412829
    Abstract: To prevent degradation of electrical characteristics caused by a resin filled between electrodes in an ultraviolet light-emitting operation, the present invention provides a base 10 that comprises an insulating base material 11 and two or more metal films 12 and 13 that are formed on one side of the insulating base material 11 and electrically separated from each other. The two or more metal films are formed to include an upper surface and a side wall surface that are covered by gold or a platinum group metal, to be capable of mounting thereon one or more nitride semiconductor light-emitting elements and the like, and to have, as a whole, a predetermined planar view shape including two or more electrode pads.
    Type: Grant
    Filed: August 2, 2016
    Date of Patent: September 10, 2019
    Assignees: SOKO KAGAKU CO., LTD., AGC INC.
    Inventors: Akira Hirano, Ko Aosaki
  • Patent number: 10375826
    Abstract: A printed circuit board assembly (PCBA) for downhole applications has a printed circuit board (PCB) and a plurality of electronic components installed on the PCB. The PCB comprises a polyimide substrate, a lead-free surface finish, a plurality of traces, a plurality of surface mount pads, and a plurality of VIAs. The ratio between the width of one of the plurality of surface mount pads to the width of the trace connected thereto is 2 or less.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: August 6, 2019
    Assignee: CHINA PETROLEUM & CHEMICAL CORPORATION
    Inventors: Sheng Zhan, Jinhai Zhao, Fengtao Hu, Herong Zheng
  • Patent number: 10354957
    Abstract: An electrical interconnect for an electronic package. The electrical interconnect includes a first dielectric layer; a second dielectric layer; a signal conductor positioned between the first dielectric layer and the second dielectric layer; and a conductive reference layer mounted on the first dielectric layer, and wherein the conductive reference layer does not cover the signal conductor. The conductive reference layer may be a first conductive reference layer and the electrical interconnect further comprises a second conductive reference layer mounted on the second dielectric layer. The second conductive reference layer does not cover the signal conductor. In addition, the signal conductor may be a first signal conductor and the electrical interconnect may further include a second signal conductor between the first dielectric layer and the second dielectric layer. The first and second signal conductors may form a differential pair of conductors.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: July 16, 2019
    Assignee: Intel Corporation
    Inventors: Bok Eng Cheah, Jackson Chung Peng Kong, Stephen Harvey Hall, Khang Choong Yong, Kooi Chi Ooi, Eric C Gantner