Abstract: Example implementations relate to an integrated circuit (IC) package, an electronic device having the IC package, and a method of assembling the IC package to a printed circuit board (PCB) of the electronic device. The IC package includes a substrate, a chip, and an electromagnetic shield. The chip is coupled to the substrate. The electromagnetic shield is coupled to the substrate such that the chip is enclosed between the substrate and the electromagnetic shield. The electromagnetic shield includes a ferromagnetic material. Further, the electromagnetic shield protrudes beyond the substrate and is electrically grounded to the PCB to prevent an electromagnetic interference (EMI) noise from radiating through the IC package.

Abstract: A circuit structure and a fabrication method thereof are provided. The fabrication method of the circuit structure includes the following steps: providing a substrate; fabricating a test circuit component on the substrate; fabricating a solder pad on the test circuit component; fabricating an insulating layer; and fabricating a conductive pad on the insulating layer. A second surface of the insulating layer covers the test circuit component and the solder pad. The conductive pad is coupled to the solder pad. Through the fabrication method of the circuit structure provided by the disclosure, circuit quality of the circuit structure may be monitored, and that reliability of the circuit structure provided by the disclosure is improved.

Abstract: A semiconductor package structure is provided. The semiconductor package structure includes an electronic component, and an inductance component. The protection layer encapsulates the electronic component and has a top surface and a bottom surface. The top surface and the bottom surface collectively define a space to accommodate the electronic component. The inductance component outflanks the space from the top surface and the bottom surface of the protection layer.

Abstract: An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.

Abstract: According to one embodiment, an isolator includes a first wiring board and a second wiring board. The first wiring board includes a first insulating layer including first and second principal surfaces; a first coil provided on the first principal surface; and a first pad provided on the first principal surface and electrically connected to the first coil. The second wiring board includes a second insulating layer including third and fourth principal surfaces; a second coil provided on the third principal surface; and a second pad provided on the fourth principal surface and electrically connected to the second coil. The first and second coils are arranged in such a manner as to face each other, and an external size of the second wiring board is smaller than an external size of the first wiring board.

Abstract: A packaged electrical device can include an electrical element and a plurality of terminals connected to the electrical element. The packaged electrical device can further include a body configured to support the electrical element and the plurality of terminals. The body can have a rectangular cuboid shape with a length, a width, and a height that is greater than the width. The body can include a base plane configured to allow surface mounting of the device.

Abstract: A board terminal electrode component includes a board, and a pair of land pads spaced apart from each other on a surface of the substrate. The pair of land pads respectively include inner ends which are proximal to each other in an arrangement direction, and outer ends farther from each other in the arrangement direction than the inner ends. The pair of land pads respectively include expanding width portions expanding in a width direction from the inner end toward the outer end. The pair of land pads respectively include insulators on a surface of an end portion of the outer end of the land pads.

Abstract: A leadless semiconductor package includes a conductive base having a plurality of apertures formed around a perimeter of the conductive base and extending from a first surface to an opposing second surface of the conductive base. The semiconductor package further includes an IC die having a third surface facing the first surface of the conductive base and having a plurality of conductive pillars disposed thereon. Each conductive pillar extends from the third surface to the first surface via a corresponding aperture. A dielectric fill material is disposed in the apertures and insulates the conductive pillars from the conductive material of the conductive base. An opening of an aperture at the second surface, the bottom end of the conductive pillar disposed therein, and the dielectric fill material at the opening of the aperture at the second surface together form a surface mount pad for mounting the semiconductor package to a corresponding pad of a circuit board.

Abstract: A semiconductor structure includes a redistribution structure, topmost and bottom conductive terminals. The redistribution structure includes a topmost pad in a topmost dielectric layer, a topmost under-bump metallization (UBM) pattern directly disposed on the topmost pad and the topmost dielectric layer, a bottommost UBM pad embedded in a bottommost dielectric layer, and a bottommost via laterally covered by the bottommost dielectric layer. Bottom surfaces of the topmost pad and the topmost dielectric layer are substantially coplanar, bottom surfaces of the bottommost UBM pad and the bottommost dielectric layer are substantially coplanar, the bottommost via is disposed on a top surface of the bottommost UBM pad, top surfaces of the bottommost via and the bottommost dielectric layer are substantially coplanar. The topmost conductive terminal lands on a recessed top surface of the topmost UBM pattern, and the bottommost conductive terminal lands on the planar bottom surface of the bottommost UBM.

Abstract: Electronic assembly methods and structures are described. In an embodiment, an electronic assembly method includes bringing together an electronic component and a routing substrate, and directing a large area photonic soldering light pulse toward the electronic component to bond the electronic component to the routing substrate.

Abstract: An antenna device includes a radio frequency (RF) die, a first dielectric layer, a feeding line, a ground line, a second dielectric layer, and a radiating element. The first dielectric layer is over the RF die. The feeding line is in the first dielectric layer and is connected to the RF die. The ground line is in the first dielectric layer and is spaced apart from the feeding line. The second dielectric layer covers the first dielectric layer. The radiating element is over the second dielectric layer and is not in physically contact with the feeding line.

Abstract: An electronic component includes a substrate, an element mounted on a center portion of the substrate, a first terminal portion provided on the substrate at an edge of a first end portion of the substrate as seen in the element, and a second terminal portion provided on the substrate at an edge of a second end portion. The first terminal portion includes a first edge and a second edge in a direction perpendicular to a first direction from the element toward the first end portion and a length of the first edge is different from that of the second edge. The second terminal portion includes a third edge and a fourth edge in the direction and a length of the third edge is different from that of the fourth edge.

Abstract: An electrical connection sheet includes a conduction part including a conductive rubbery elastomer, an adhesion member, and a sheet-shaped connection member fitted with the conduction part and the adhesion member. Both surfaces of the electrical connection sheet are adhesible.

Abstract: The disclosure relates to an electronic device including an interposer. The interposer includes a substrate and a plurality of connecting structures disposed on the substrate and electrically connecting a first circuit board and a second circuit board disposed in the electronic device. The plurality of connecting structures includes a plurality of via holes formed in the substrate, a plurality of conductive members disposed in the plurality of via holes, an insulating member disposed between the plurality of conductive members, and a plurality of pads disposed on the outer periphery of the plurality of conductive members. The plurality of conductive members may be separately disposed on the substrate to electrically connect with the first and second circuit boards.

Abstract: An implantable electronic device includes a flexible circuit board, one or more circuit components attached to the flexible circuit board and configured to convert electrical energy into electrical pulses, and one or more electrodes attached to the flexible circuit board without cables connecting the electrodes to each other or to the flexible circuit board, the one or more electrodes configured to apply the electrical pulses to a tissue adjacent the implantable electronic device.

Abstract: The present disclosure provides a circuit board and its manufacturing method. The circuit board includes a first circuit layer, a first conductive post, and a second circuit layer. The first circuit layer includes a first pad and a first seed layer covering a sidewall of the first pad. The first conductive post is on the first pad and directly connected to the first pad. The second circuit layer includes a second pad and a second seed layer covering a sidewall of the second pad. The second pad is on a first connecting end of the first conductive post. The first connecting end is embedded in the second pad, and the second pad is connected to and directly contacts the first connecting end. The first seed layer and the second seed layer do not extend on a sidewall of the first conductive post.

Abstract: A device and method for providing enhanced bridge structures is disclosed. A set of conducting and insulating layers are deposited and lithographically processed. The conducting layers have uFLS routing. A bridge with uFLS contacts and die disposed on the underlying structure such that the die are connected with the uFLS contacts and uFLS routing. For core-based structures, the layers are formed after the bridge is placed on the underlying structure and the die connected to the bridge through intervening conductive layers. For coreless structures, the layers are formed over the bridge and carrier, which is removed prior to bonding the die to the bridge, and the die bonded directly to the bridge.

Abstract: Aspects of this disclosure relate to methods of selectively shielded radio frequency modules. A radio frequency module can be provided with a radio frequency component and an antenna. A shielding layer can be formed over a portion of the radio frequency module such that the radio frequency component is shielded by the shielding layer and the antenna is unshielded by the shielding layer.

Abstract: A semiconductor package includes a base package substrate, a first semiconductor chip, and a second semiconductor chip. The base package substrate includes a redistribution region where a redistribution layer is provided, a plurality of vertical conductive vias connected to the redistribution layer, and a recess region recessed from an upper surface of the redistribution region. The base package substrate further includes an interposer in the recess region, the interposer comprising a substrate, a plurality of upper pads disposed at an upper surface of the substrate, and plurality of through electrodes respectively connected to the plurality of upper pads to pass through the substrate. The first semiconductor chip and second semiconductor chip, each include a plurality of conductive interconnection terminals respectively connected to the plurality of upper pads and the vertical conductive vias exposed at the upper surface of the redistribution region.

Abstract: A single-layer redistribution plate functioning as a space translator between a device under testing (“DUT”) and a testing PCB may comprise a hard ceramic plate. A DUT side of the plate may have pads configured to interface with a device under testing. Both sides of the plate may comprise traces, vias, and pads to fan out the DUT pad pattern so that the plate side opposite the DUT side has spatially translated pads configured to interface with the pads on a testing PCB. Fabricating a redistribution plate may comprise calibrating and aligning, laser milling vias, laser milling trenches and pads, copper plating, grinding and polishing, removing residual copper, and coating the copper surfaces.

Abstract: A power supply apparatus includes a board including a major surface on which a circuit element group is mounted, and a case attached to the board. The case includes a plate-shaped portion that is located at a distance from the board and faces the major surface, and a side wall portion extending from the plate-shaped portion toward one end portion of the board. One end of a specific circuit element among the circuit element group reaches the one end portion of the board, the one end of the specific circuit element being directed to the side wall portion. The side wall portion is provided with a notch portion with a shape corresponding to an outer shape of the one end of the specific circuit element.

Abstract: A wiring substrate includes: a wiring layer; an insulating layer that is laminated on the wiring layer; an opening portion that passes through the insulating layer to the wiring layer; and an electric conductor film that is formed at the opening portion of the insulating layer. A surface of the insulating layer includes a smoothed portion that is not covered by the electric conductor film, and a roughened portion that includes an inner wall surface of the opening portion covered by the electric conductor film and that have surface roughness that is greater than surface roughness of the smoothed portion.

Abstract: The present disclosure relates to a printed circuit board and a method of manufacturing the same. The printed circuit board includes: an insulating layer; a plurality of pads disposed on the insulating layer; and a plurality of insulating walls that are disposed on the insulating layer and cover side surfaces of the plurality of pads, respectively, but are not disposed on upper surfaces of the plurality of pads. The plurality of insulating walls are disposed to be spaced apart from each other on the first insulating layer.

Abstract: An electronic device is provided. The electronic device includes an electronic component and a heat dissipation structure. The electronic component has a passive surface and a plurality of conductive vias exposed from the passive surface. The heat dissipation structure is disposed on the passive surface and configured to transmit a plurality of independent powers to the conductive vias through the passive surface.

Abstract: A power amplifier module includes a module substrate, a power transistor die, and a heat spreader. The module substrate has first, second, and third module pads exposed at a mounting surface. The power transistor die has an input/output surface that faces the mounting surface, an opposed ground surface, an input pad electrically coupled to the first module pad, an output pad electrically coupled to the second module pad, and an integrated power transistor. In an embodiment, the power transistor is a field effect transistor with a gate terminal coupled to the input pad, a drain terminal coupled to the output pad, and a source terminal coupled to the ground surface. The heat spreader has a thermal contact surface that is physically and electrically coupled to the ground surface of the power transistor die. An electrical ground contact structure is connected between the thermal contact surface and the third module pad.

Abstract: A packaged electronic device includes first conductive leads and second conductive leads at least partially exposed to an exterior of a package structure, and a multilevel lamination structure in the package structure. The multilevel lamination structure includes a first patterned conductive feature having multiple turns in a first level to form a first winding coupled to at least one of the first conductive leads in a first circuit, a second patterned conductive feature having multiple turns in a different level to form a second winding coupled to at least one of the second conductive leads in a second circuit isolated from the first circuit, and a conductive shield trace having multiple turns in a second level spaced apart from and between the first patterned conductive feature and the second patterned conductive feature, the conductive shield trace coupled in the first circuit.

Abstract: Implementations of semiconductor packages may include a first substrate having two or more die coupled to a first side, a clip coupled to each of the two or more die on the first substrate and a second substrate having two or more die coupled to a first side of the second substrate. A clip may be coupled to each of the two or more die on the second substrate. The package may include a lead frame between the first substrate and the second substrate and a molding compound. A second side of each of the first substrate and the second substrate may be exposed through the molding compound. A perimeter of the first substrate and a perimeter of the second substrate may not fully overlap when coupled through the lead frame.

Abstract: A printed wiring board includes a first insulating layer, a conductor layer, and a second insulating layer. The conductor layer includes first and second circuits such that space is formed between the circuits, the first circuit has first and second side walls, the second circuit has third and fourth side walls such that the second wall faces the third wall, the first circuit has first, second and third portions, the second circuit has fourth, fifth and sixth portions such that the first and fourth portions, the second and fifth portions and the third and sixth portions face each other, the first circuit is formed such that the second wall of the second portion is recessed from the second wall of the first and third portions, and the first insulating layer has recess between the second and fifth portions such that the second insulating layer is filling the space and recess.

Abstract: A number of different sealed interfaces for power modules are described. In one example, a sealed interface includes a printed circuit board including a contact pad for power conduction to a bus bar of the printed circuit board, a semiconductor module including at least one power transistor, a terminal pin electrically coupled to the power module, and a housing for the power module. The housing includes an open terminal aperture that extends through the housing. The printed circuit board is seated upon the open terminal aperture, to close and seal the open terminal aperture, with the contact pad positioned within the open terminal aperture. The terminal pin contacts the contact pad of the printed circuit board within the open terminal aperture, and the open terminal aperture comprises a transitional feature to abate electric field intensity around an interface between the open terminal aperture and the printed circuit board.

Abstract: Implementations of semiconductor packages may include a first substrate having two or more die coupled to a first side, a clip coupled to each of the two or more die on the first substrate and a second substrate having two or more die coupled to a first side of the second substrate. A clip may be coupled to each of the two or more die on the second substrate. The package may include a lead frame between the first substrate and the second substrate and a molding compound. A second side of each of the first substrate and the second substrate may be exposed through the molding compound. A perimeter of the first substrate and a perimeter of the second substrate may not fully overlap when coupled through the lead frame.

Abstract: A technique for dissipating heat from a plurality of components is proposed. An electric component (1) includes a substrate (400), a first component (412), a second component (401), and a heat sink (31). The substrate (400) has a first surface (400b) and a second surface (400a) opposite to the first surface (400b). The first component (412) is disposed on a side of the first surface (400b). The second component (401) includes a body (401a) disposed on a side of the second surface (400a), and a lead (401b) that extends from the body (401a) through the second surface (400a) to the first surface (400b). The heat sink (31) is disposed on the side of the first surface (400b), and is used in common for dissipation of heat from the body (401a) through the lead (401b) and dissipation of heat from the first component (412).

Abstract: Provided is an array substrate. The array substrate includes at least one pad group disposed in a peripheral region of a base substrate, wherein the at least one pad group includes a sector pad group in which the pads are distributed in a sector shape. Therefore, the bonding yield between the array substrate and the circuit board is increased.

Abstract: An integrated circuit and method of making an integrated circuit is provided. The integrated circuit includes an electrically conductive pad having a generally planar top surface that includes a cavity having a bottom surface and sidewalls extending from the bottom surface of the cavity to the top surface of the pad. An electronic device is attached to the top surface of the electrically conductive pad. A wire bond is attached from the electronic device to the bottom surface of the cavity. A molding compound encapsulates the electronic device.

Abstract: An electronic device includes a base layer including a flat region and a bendable region extending from the flat region, a display module disposed on the base layer and overlapping the flat region, a window disposed on the display module and having a display region and a non-display region adjacent to the display region, and an antenna layer overlapping the non-display region of the window and disposed on one side of the display module, wherein the antenna layer includes an antenna module and an insulating layer surrounding the antenna module.

Abstract: This disclosure provides systems, devices, apparatus and methods, including computer programs encoded on storage media, for wireless power transmission. In accordance with this disclosure, a wireless power transmission apparatus (such as a charging pad) may support positional freedom such that a wireless power receiving apparatus may be charged regardless of positioning or orientation of the wireless power receiving apparatus. Various implementations include the use of multiple primary coils in a wireless power transmission apparatus. The multiple primary coils may be configured in a pattern, size, shape, or arrangement that enhances positional freedom. In some implementations, the placement of the multiple primary coils may optimize the size and distribution of electromagnetic fields that are available to charge a wireless power receiving apparatus.

Abstract: A commonly designed processor heat exchanger decouples the mounting hardware used to mount the heat exchanger to a processor from the heat exchanger itself. This allows a single heat exchanger design to be mounted to various different types of processors using processor customized mounting brackets that engage with flanges extending out from a body of the heat exchanger.

Abstract: Provided are a flexible circuit mother board and a detection method. The flexible circuit mother board includes flexible circuit daughter boards, at least one detection terminal group and external pad groups corresponding to the flexible circuit daughter boards in one-to-one correspondence. Each flexible circuit daughter board has a bonding pad area adjacent to a corresponding one of the plurality of external pad groups. Each detection terminal group detects at least one flexible circuit daughter board, and each of the at least one detection terminal group comprises a plurality of detection terminals. Each flexible circuit daughter board includes a plurality of capacitors including a first electrode plate and a second electrode plate. Each of the first electrode plate and the second electrode plate is electrically connected to one detection terminal.

Abstract: A package structure includes a semiconductor die and a first redistribution circuit structure. The first redistribution circuit structure is disposed on and electrically connected to the semiconductor die, and includes a first build-up layer. The first build-up layer includes a first metallization layer and a first dielectric layer laterally wrapping the first metallization layer, wherein at least a portion of the first metallization layer is protruded out of the first dielectric layer.

Abstract: Embodiments of the present disclosure include a semiconductor device and methods of forming a semiconductor device. An embodiment is a semiconductor device comprising an interconnecting structure consisting of a plurality of thin film layers and a plurality of metal layers disposed therein, each of the plurality of metal layers having substantially a same top surface area, and a die comprising an active surface and a backside surface opposite the active surface, the active surface being directly coupled to a first side of the interconnecting structure. The semiconductor device further comprises a first connector directly coupled to a second side of the interconnecting structure, the second side being opposite the first side.

Abstract: A test board for testing a semiconductor apparatus includes a first board configured to support a plurality of first Devices Under Test (DUTs) such that the plurality of first DUTs are mounted on the first board, a plurality of first inter-board connectors arranged on the first board, and a plurality of second boards stacked on the first board through the plurality of first inter-board connectors, each second board of the plurality of second boards having a surface configured to support a separate second DUT of a plurality of second DUTs such that the plurality of second DUTs are mounted on separate, respective second boards of the plurality of second board.

Abstract: Embodiments disclosed herein include electronic packages and methods of fabricating electronic packages. In an embodiment, an electronic package comprises an interposer, where a cavity passes through the interposer, and a nested component in the cavity. In an embodiment, the electronic package further comprises a die coupled to the interposer by a first interconnect and coupled to the nested component by a second interconnect. In an embodiment, the first and second interconnects comprise a first bump, a bump pad over the first bump, and a second bump over the bump pad.

Abstract: A multi-chip module (MCM) includes a first integrated circuit (IC) chip to receive first data. The first IC chip includes a first transfer interface to transmit the first data off the first IC chip. A second IC chip includes an input interface to receive the first data from the first IC chip. The second IC chip includes switching circuitry to selectively forward the first data to one of a first output interface or a second output interface. The first output interface is communicatively coupled to a third IC chip, while the second output interface is configured to output the first data from the MCM.

Abstract: A high-frequency module (1) includes a substrate (10), a first electronic component (30) and a second electronic component (40) mounted on a main surface (10a) of the substrate (10). The substrate (10) has a protruding portion (20) projecting from the main surface (10a), the first electronic component (30) is mounted in a region of the main surface (10a) different from a region in which the protruding portion (20) is provided, and the second electronic component (40) is mounted on the protruding portion (20).

Abstract: Provided is a semiconductor device capable of improving the divisibility of a wafer by concentrating crack stress by disposing notch patterns on a scribe line of a wafer, by locally removing a metal thin film in a scribe line and propagating a dividing energy in a vertical direction of a die surface. A semiconductor device includes: die regions spaced apart from each other in a wafer, scribe line regions disposed between neighboring ones of the die regions and covered with a metal material layer, and one or more open areas disposed in each of the scribe line regions and formed by locally removing the metal material layer, wherein each of the open areas includes one or more notch patterns indicating a direction in which the scribe line region is extended.

Abstract: An optical module includes a circuit board having a through hole for the lead terminal, a signal wiring connected to the lead terminal, a ground layer providing a reference potential, an opening through which the ground layer is exposed, and a bonding material connecting the ground layer to the metallic base. The lead terminal extends in a first direction, and the circuit board and the signal wiring extend in a second direction. When the circuit board is viewed from the first direction, the opening overlaps with the signal wiring, or when the opening does not overlap with the signal wiring, a first distance between the signal wiring and a closest point of the opening to the signal wiring is smaller than a second distance between the closest point and an edge of the circuit board.

Abstract: A semiconductor light-emitting device, includes: a semiconductor light-emitting element; a support including a base and a conductive part and configured to support the semiconductor light-emitting element; and a cover configured to overlap the semiconductor light-emitting element as viewed in a first direction, and to transmit light from the semiconductor light-emitting element, wherein the cover includes a base layer having a front surface and a rear surface which transmit the light from the semiconductor light-emitting element and face opposite sides to each other in the first direction, wherein the rear surface faces the semiconductor light-emitting element, wherein the base layer includes a plurality of undulation parts bonded to the support by a bonding material, and wherein the undulation parts are more uneven than the rear surface.

Abstract: A transient or biodegradable battery is provided having a filament structure that limits the speed of reaction allowing for a longer duration of battery power with a controlled current limit. In one embodiment, the filament may be constructed of zinc microparticles or nanoparticles having a thin outer insulation whereby a chemical reaction at the center core results in the progressive disintegration of the insulation revealing more core material. In one embodiment, microparticles or nanoparticles are coated with outer layers of chitosan and Al2O3 nanofilms, respectively, with designable discharge current and battery lifespan by controlling the exposed cross-sectional area of the zinc microparticle center core and the length of the filament, respectively. This novel structure of biodegradable battery provides improved control of battery life and power output, providing a promising solution to power transient medical implants.

Abstract: An interposer includes a base layer including a first surface and a second surface that are opposite to each other. An interconnect structure is disposed on the first surface. The interconnect structure includes a metal interconnect pattern and an insulating layer surrounding the metal interconnect pattern. A first lower protection layer is disposed on the second surface. A plurality of lower conductive pads is disposed on the first lower protection layer. A plurality of through electrodes penetrates the base layer and the first lower protection layer. The plurality of through electrodes electrically connects the metal interconnect pattern of the interconnect structure to the lower conductive pads. At least one of the insulating layer and the first lower protection layer has compressive stress. A thickness of the first lower protection layer is in a range of about 13% to about 30% of a thickness of the insulating layer.

Abstract: A substrate includes a first dielectric layer having a first surface and a second dielectric layer having a first surface disposed adjacent to the first surface of the first dielectric layer. The substrate further includes a first conductive via disposed in the first dielectric layer and having a first end adjacent to the first surface of the first dielectric layer and a second end opposite the first end. The substrate further includes a second conductive via disposed in the second dielectric layer and having a first end adjacent to the first surface of the second dielectric layer. A width of the first end of the first conductive via is smaller than a width of the second end of the first conductive via, and a width of the first end of the second conductive via is smaller than the width of the first end of the first conductive via.

Abstract: A display device includes a supporting substrate including a polymeric material, base substrate disposed on an upper surface of the supporting substrate, a pixel array disposed in a display area of the base substrate, a transfer wiring disposed in a bending area of the base substrate and electrically connected to the pixel array, and an organic filling portion disposed under the transfer wiring in the bending area. The base substrate includes an organic film including a polymeric material, and an inorganic barrier film overlapping the organic film and extending outwardly from an edge of the organic film. The organic filling portion contacts the organic film of the base substrate.