Abstract: A method and apparatus that allows additional contact pads to be added to a package to support debug and test operations is disclosed. In a preferred embodiment, a circuit board apparatus includes a semiconductor package and an interposer for receiving the semiconductor package. The semiconductor package preferably includes a substrate having a matrix of conductive contact pads on both the top and bottom surfaces of the substrate. The interposer preferably includes a body having a matrix of interposer contact bumps on both the inner and outer surfaces of the body. Each interposer contact bump preferably includes a metal coating and is shaped to abut a contact pad of the semiconductor package.

Abstract: A reversible heat sink packaging assembly (400) for integrated circuits is provided. The packaging assembly (400) includes a chip carrier (102) having an opening (104) formed therein and a heat sink (302). The heat sink (302) is attached to one side of a die (304). The die (304) fits into the opening (104) of the carrier (102) with the heat sink (302) abutting one side (208) of the carrier and the die being wire bonded (402) to the other side (108) of the carrier. The packaging assembly (400) can be oriented either device side up or down.

Abstract: A printed circuit board 1 providing superior adhesion between a substrate 2 and a conductor pattern 3 and preventing damage of the substrate 2. The width c of the bottom surface 310 of the conductor pattern 3 is greater than the width d of the top surface 320. Accordingly, the conductor pattern 3 has a trapezoidal cross-section. The two side surfaces 315 of a lower portion 31 of the conductor pattern 3 are coated by a solder resist. The two side surfaces 325 at the upper portion 32 of the conductor pattern 3 are exposed from the solder resist 4. A solder ball 6 engages the two side surfaces 325.

Abstract: An interposer to couple a microelectronic device package to a motherboard is formed from a PCB substrate. Multiple via holes are drilled through a copper-clad PCB substrate and then coated inside with copper. The copper surface coating is etched to form multiple traces. In one embodiment, the substrate is cut through each row of via holes and between each row of via holes to produce multiple individual beam-and-trace interposers. Two or more such interposers may be affixed together to form a beam-and-trace interposer array. Alternatively, the substrate is not cut into strips, and each via hole is filled completely with a conductive material to form an array of solid conductive columns through the substrate.

Abstract: According to the present invention, for a module in which a plurality of integrated circuit devices are mounted in parallel, the inductance generated by the unit length of a branched signal line on a motherboard is so set that it is smaller for a branched signal line a longer distance from its branching point to its distal end, and is so set that it is larger for a branched signal line having a shorter distance from its branching point to its distal end, so that the time required for transmission of a signal from the branching point to the distal end of each branched signal line is the same.

Abstract: A method of assembling a multi-chip device may include coupling solder balls only to selected ones of the conductive pads on an interposer with cache memory devices. The cache memory devices are then tested, and the interposer is coupled to a substrate with the solder balls for further assembly only if the test is passed.

Abstract: A plurality of electronic components having conductive connecting members are surface-mounted to a target surface of a circuit board by specifying terminal-forming areas that are each no greater than the corresponding one of the electronic components and each include at least one terminal part such that at least one of these terminal-forming areas includes a plurality of terminal parts directly and that each pair of the terminal parts within any one of the terminal-forming areas is closer to each other than any pair of the terminal parts in different ones of the terminal-forming areas. An anisotropic conductive layer is formed on this target surface so as to span these terminal-forming areas, and the plurality of electronic components are placed on this anisotropic conductive layer individually above the plurality of terminal-forming areas.

Abstract: An electronic device has a semiconductor chip and a passive component, whose electrical values can be varied. The semiconductor chip is electrically conductively connected to a rewiring structure that, together with the semiconductor chip and with the passive component, is enclosed by a housing made of plastic. A method for producing the electronic device is also described.

Abstract: This invention provides a circuit mounting method and a circuit mounted board which can mount semiconductor elements at a high density. A recessed portion is formed in a board, a memory IC packaged in a chip size package method (CSP) is mounted in the recessed portion, and a memory IC packaged in a thin small outline package method (TSOP) is mounted on the board to cover the recessed portion.

Abstract: An electronic device assembled using a coupler which has an electroconductive region and a resin region on the surface. Flexibility of the resin region absorbs stress caused by difference in thermal expansion coefficient between an organic printed circuit board and a semiconductor chip through the deformation of the electroconductive region. As a result, formation of cracking in the coupler is avoided. It is preferable that the resin region occupies from 20 to 80% of the total surface area of the coupler. The coupler may be formed from a molten blend of the heat resistant resin and a joining metal. The coupler may also be formed by molding a blend of the heat resistant resin and metal powder, wherein the metal powder locating on the surface of the coupler have a joining metal joined thereto.

Abstract: A chip carrier is coupled to a printed circuit board by leads so that the chip carrier stands off from the printed circuit board. A spacer is provided between the chip carrier and the printed circuit board. The spacer reduces g forces on the leads.

Abstract: Power conversion apparatus includes a circuit board with power conversion circuitry and a package. The package includes an upper portion that encloses circuitry on a top surface of the circuit board and a lower portion that encloses circuitry on a bottom surface of the circuit board. The lower portion encloses a region on the circuit board that is smaller than the region enclosed by the upper portion and is arranged to define an overhang region on the bottom surface of the circuit board. The overhang region preferably extends along two or more sides of the periphery of the bottom surface. Interface contacts are provided on the bottom surface in the overhang region for making electrical connections to the circuit board. The power conversion apparatus may be mounted in an aperture in an external circuit board or may be mounted horizontally or vertically to the external board using an interconnect extender.

Abstract: Solder paste is applied beforehand onto through-hole upper lands (or solder) of a printed circuit board and attachment is effected by inserting solder joined to the BGA-side pads into the holes of the through-hole upper lands; solder and solder paste are then melted by heating, causing them to flow into the through-holes and to wet and spread out upon the through-hole bottom face lands, thereby effecting a soldered joint with the BGA-side pads and through-hole upper lands securely attached, and forming solder fillets. In this way, the quality of the solder joints can be ascertained by an ordinary external inspection method.

Abstract: A semiconductor package includes a chip carrier to receive a semiconductor with a dimension generally greater than 26 mm. The chip carrier has a first coefficient of thermal expansion that is larger than the coefficient of thermal expansion of the semiconductor. A stress inhibiting intermediate mounting substrate is connected to the chip carrier through a first array of solder connections. The stress inhibiting intermediate mounting substrate has a second coefficient of thermal expansion that is larger than the coefficient of thermal expansion of the chip carrier and smaller than or equal to the coefficient of thermal expansion of the printed circuit board. Alternate preferred inventive embodiments allow for the cleaning and removal of residual flux and other debris in packaging.

Abstract: A surface laminar circuit board includes an insulating layer, and a signal ground conductive layer disposed on an upper surface of the insulating layer. The conductive layer has a hole formed therein. A photosensitive dielectric layer is disposed on an upper surface of the signal ground conductive layer. The dielectric layer has a photo micro-via formed therein. A signal trace is disposed on the photosensitive dielectric layer, and is electrically coupled with the signal ground conductive layer by way of the photo micro-via. A conductive pad is provided, which has a majority thereof within an area defined by an outer periphery of the hole. The conductive pad is electrically coupled with the signal trace. A surface mounted component is mounted on the conductive pad.

Abstract: An electronic assembly includes one or more discrete capacitors (506, 804, 1204), which are vertically connected to a housing, such as an integrated circuit package (1704). Surface mounted capacitors (506) are vertically connected to pads (602) on a top or bottom surface of the package. Embedded capacitors (804, 1204) are vertically connected to vias (808, 816, 1210, and/or 1212) or other conductive structures within the package. Vertically connecting a surface mounted or embedded capacitor involves aligning (1604) side segments (416) of some of the capacitor's terminals with the conductive structures (e.g., pads, vias or other structures) so that the side of the capacitor upon which the side segments reside is substantially parallel with the top or bottom surface of the package. Where a capacitor includes extended terminals (1208), the capacitor can be embedded so that the extended terminals provide additional current shunts through the package.

Abstract: A die paddle for receiving an integrated circuit die in a plastic substrate. The die paddle is defined by a copper film on the plastic substrate and comprises a plurality of via holes through the plastic substrate, a plurality of opening through the copper film, and a gold-containing ring formed on the peripheral portion of the copper film. The outermost openings (and/or the outermost via holes) and the gold-containing ring are separated by a distance of about 1 to about 20 mils.

Abstract: An electronic component mounted member includes a circuit board, an electronic component connected to the circuit board and an electrically conductive adhesive interposed between the electronic component and the circuit board. In a joining interface of the electrically conductive adhesive and an electrode of the circuit board, an intermediate layer that is formed of a thermoplastic insulating adhesive with a softening temperature of 100° C. to 300° C. is interposed between the electrically conductive adhesive and the electrode. An electrically conductive filler contained in the electrically conductive adhesive is present partially in the intermediate layer, thus allowing an electrical conduction between the electrically conductive adhesive and the electrode of the circuit board.

Abstract: A wiring substrate equipped with a rerouted wiring having one end connected to an electronic-part mounting pad for electrically connecting an electronic part and another end connected to an external-connection terminal. In the wiring substrate, a low-elasticity underlayer made of a material having a lower modulus of elasticity than that of a base material of the wiring substrate is disposed between the base material of the wiring substrate and each of the electronic-part mounting pad and the rerouted wiring. A method of manufacturing the wiring substrate and a semiconductor device using the wiring substrate are also disclosed.

Abstract: An electronic package which includes first and second circuitized substrates secured together by a solder member which includes a first contact portion for attachment to a printed circuit board and a second contact portion used to bond the two substrates together (e.g., to form a multi-chip module). Semiconductor chips can be positioned on and electrically coupled to the formed solder members.

Abstract: A unit interconnection substrate for mounting leadless type electronic parts on a mount substrate by superposing them on each other in two or more stages, comprising an insulating surface on the top surface of which an interconnection circuit with conductor pads and connection terminals is formed, depressions for holding electronic parts formed in a bottom surface of the insulating substrate, connection terminals provided on the bottom surface of the insulating substrate on the periphery of the depression, and connection terminals electrically connected to the connection terminals of the top surface of the insulating substrate via conductor via holes provided in the insulating substrate. Electronic parts are electrically connected to the conductor pads on the top surface of the insulating substrate, thereby to make it possible to mount the electronic parts on the insulating substrate.

Abstract: A multi-level package, and method for making same, that offers a small size with compartmentalized areas that allow for radiation shielding is disclosed. In its simplest embodiment, the invention comprises two cards and an interposer interposed between the two cards. The interposer preferably has an opening, and the combination of the interposer's opening and the two cards form a cavity. The cavity allows for a high amount of components to be packed into a small, three-dimensional space. The interposer supports can act like a Faraday shield. The two cards and interposer can be multi-layered and support any type of chip or package connection on each side of each card or interposer, including through-hole, surface mount, and direct-chip attachment connections. Finally, pick-up plates or heat sinks can be attached to the package.

Abstract: A structure suitable for connecting an integrated circuit to a supporting substrate wherein the structure has thermal expansion characteristics well-matched to the integrated circuit is an interposer. The integrated circuit and the interposer are comprised of bodies that have substantially similar coefficients of thermal expansion. The interposer has a first surface adapted to electrically and mechanically couple to the integrated circuit. The interposer has a second surface adapted to electrically and mechanically couple to a supporting substrate. Electrically conductive vias provide signal pathways between the first surface and the second surface of the interposer. Various circuit elements may be incorporated into the interposer. These circuit elements may be active, passive, or a combination of active and passive elements.

Abstract: A semiconductor device with bump electrodes having acutely shaped tips and method of mounting same. The bump electrodes are brought into contact with respective portions of a conductive pattern of a mounting substrate without any foreign matter between the tips of the bump electrodes and the respective portions of the conductive pattern. Thereafter, sealing material is allowed to surround the bump electrodes.

Abstract: Arrangements are used to improve noise immunity of differential signals.

Abstract: The present disclosure relates that constraining a substrate into a convex arc prior to mounting and affixing of any chips, allows those chips to achieve exemplary final chip-to-chip abutment when the substrate is released and allowed to return to stasis. This is particularly of use where there are any intervening thermal cycles, and the thermal temperature coefficients of expansion for the chip/die and any substrate/mount are significantly different. This will allow the utilization of otherwise more desirable materials for the substrate in spite of some mismatch in thermal coefficients that may exist between the substrate and chips.

Abstract: An electronic component having a substrate on which one or more grooves are formed on its opposing side faces; electrodes formed on the groove and top and bottom faces of the substrate at a portion adjacent to the groove; and a circuit element formed between the electrodes. An electrode is also formed on the opposing side faces of said substrate at a portion other than the grooves. This structure enables to improve the reliability of a soldered portion even for small electronic components with about 10 &mgr;m thick electrodes such as chip resistors, chip capacitors, and chip inductors.

Abstract: A solder connecter assembly having a printed wiring board, an electrode formed on the printed wiring board, a semiconductor package, a pad formed on the semiconductor package, a resist formed on the printed wiring board and having an opening of the resist around the electrode, a solder ball disposed between the electrode and the pad, and a resin fillet formed in the opening and in a vicinity of a connecting part between the solder ball and the electrode.

Abstract: An integrated circuit device module comprises a printed circuit board having opposed sides, the printed circuit board comprising a portion carrying an area contact array on one of the sides of the printed circuit board. The module comprises an integrated circuit device having opposed, top and bottom surfaces, the bottom surface of the integrated circuit device comprising an area contact array for electrical communication with the area contact array on the printed circuit board.

Abstract: In order to reduce the thickness of a semiconductor device and double its capacity, two center pad semiconductor chips stacked one on the other, back to back, are fixed to one face of a wiring substrate. The difference in the length of routing between external lands and fingers is minimized, and each of the center pads and corresponding fingers are connected via metal wires having a high conductivity. The main face of a first center pad semiconductor chip is fixed to the wiring substrate that has first and second wired faces and a through opening. The back face of the first semiconductor chip and the back face of a second semiconductor chip are fixed to each other using a bonding material. The pads on each semiconductor chip are connected to corresponding fingers on the wiring substrate via metal wires. One face of the wiring substrate is sealed with a sealing resin, and on the other face, an area in the vicinity of the through opening is sealed.

Abstract: The present invention is provides an LSI package without employing steps for forming solder bumps on a bare chip and soldering to an interposer. In the present invention, a bare chip is mounted on the LSI package by forming wiring patterns which connect to bare chip I/O terminals in a build-up layer of a substrate. Furthermore, the wiring patterns are formed so as to connect outer I/O terminals on the substrate.

Abstract: A method for controlling the shape and height of solder connections of a surface mount circuit device, such as a flip chip, by way of controlling the manner and extent to which solder is able to flow on a conductor during reflow in order to maximize the distance between adjacent connections. The device is mounted to a circuit board with a conductor pattern defined by a number of conductors, each having a reduced-width portion. A mask is formed on the circuit board to have an opening that exposes a portion of each reduced-width portion, each exposed portion having opposing first and second ends. The device has solder bumps that are staggered so that every other solder bump is registered with a first end of one of the exposed portions, and so that the remaining intervening solder bumps are registered with the opposing second ends of the remaining exposed portions.

Abstract: A supporting substrate for mounting a semiconductor bare chip thereon has a surface provided with electrode pads thereon and bumps on the electrode pads. A sealing resin film is selectivley formed on the periphery of the surface of the supporting substrate, except over the bumps, and further the sealing resin film has at least a thermosetting property. The electrode pads of the supporting substrate and the bumps of the semiconductor bare chip are bonded by a thermo-compression bonding.

Abstract: An electronic component mounted member includes a circuit board, an electronic component connected to the circuit board and an electrically conductive adhesive interposed between the electronic component and the circuit board. In a joining interface of the electrically conductive adhesive and an electrode of the circuit board, an intermediate layer that is formed of a thermoplastic insulating adhesive with a softening temperature of 100° C. to 300° C. is interposed between the electrically conductive adhesive and the electrode. An electrically conductive filler contained in the electrically conductive adhesive is present partially in the intermediate layer, thus allowing an electrical conduction between the electrically conductive adhesive and the electrode of the circuit board.

Abstract: To mount electronic components on a printed circuit board (PCB), the electrical contacts of the components are coupled to PCB bonding pads that are intersected by via pads. To minimize various defects encountered during solder reflow, while concurrently minimizing PCB area and manufacturing costs, the via pads are formed so that the via holes substantially avoid underlying the solder fillets coupling the component contacts to the PCB bonding pads. In one embodiment, the via pads are formed in the inter-pad space beneath the component; in another embodiment they are offset from the bonding pads. A substrate, an electronic assembly, and an electronic system are described.

Abstract: A back-to-back semiconductor device module including two semiconductor devices, the backs of each being secured to one another. The bond pads of both semiconductor devices are disposed adjacent a single, mutual edge of the device module. The device module may be secured to a carrier substrate in a substantially perpendicular orientation relative to the former. Solder reflow or a module-securing device can secure the device module to the carrier substrate. An embodiment of a module-securing device comprises an alignment device having one or more receptacles formed therein and intermediate conductive elements that are disposed within the receptacles to establish an electrical connection between the semiconductor devices and the carrier substrate. Another module-securing device comprises a clip-on lead, where one end resiliently biases against a lead of at least one of the semiconductor devices, while the other end connects electrically to a carrier substrate terminal.

Abstract: An interposer adapted to be used between a mounting board and a semiconductor chip which is to be mounted on the mounting board. The interposer having a heat-resistant insulator having first and second surfaces, the insulator being provided with a plurality of through-holes opened at the first and second surfaces; wiring patterns formed on the first and second surfaces of the insulator electrically connected to each other by means of a conductor provided on an inner wall of at least one of the through-holes; and a capacitor. The capacitor has first electrode formed on the insulator and having a connecting portion formed on an inner wall of at least one of the other through-holes, a dielectric layer formed on the first electrode, and a second electrode formed on the dielectric layer.

Abstract: The transformation of An IC substrate with edge contacts into a ball grid array is accomplished using a flexible circuit that has terminals arranged planarly on the underside for receiving meltable solder humps and whose conductors leading outwardly from the terminals have exposed ends. The upper side of the flexible circuit is connected with the lower side of the substrate, whereupon the edge regions of the flexible circuit are bent up and around the substrate and the ends of the conductors are electrically contacted to the edge contacts of the substrate.

Abstract: There is provided a semiconductor device having a semiconductor chip in which a first protrusion electrode is formed on the semiconductor substrate; and an intermediate substrate which comprises a base substrate, a first external terminal provided in said base substrate, which is joined to said first protrusion electrode, a second external terminal provided in said base substrate, an electrode section being exposed on both surfaces of said base substrate, and a second protrusion electrode formed at one end face of said second external terminal, a plurality of said intermediate substrates being stacked in layers by joining said second protrusion electrode to the other end face of said second external terminal, thus enabling miniaturizing and lightening electronic equipment and realizing high reliability and high performance.

Abstract: A module circuit board for a semiconductor device by a solder reflow process includes a plurality of pads on which the semiconductor device to be mounted, a plurality of terminals formed on a side edge of the board, a resist film covering an area between said pads and said terminal on the board, and a barrier formed between said pads and said terminals.

Abstract: A ball grid array (BGA) electronic component package having a configuration which is capable of improving mounting efficiency as well as preventing footprints from breaking away at circuit-connecting portions of the electronic component package. The BGA package has reinforcing bumps formed in an area located outward of a predetermined area in which conventional circuit-connecting bumps are arranged. Therefore, even if a shock is applied to the BGA package e.g. when a printed circuit board having the BGA package mounted thereon is carelessly dropped during the manufacturing work, at the outer or peripheral portion of the BGA package, which is most sensitive to such a shock, the shock is absorbed by the reinforcing bumps and reinforcing footprints which have no electrical connection with the circuitry of the electronic component package. Thus, the footprints formed on a mounting portion of the BGA package and those formed on the printed circuit board can be prevented from breaking away or being cracked.

Abstract: A molded tape ball grid array package includes a molding compound and a tape substrate having a top surface for mounting a die thereon, a bottom surface for attaching solder balls, and vias for forming connections between the solder balls and the die wherein the molding compound surrounds the die and the tape substrate.

Abstract: A semiconductor module solder bonding of high reliability in which the heat resisting properties of the circuit substrate and electronic parts are taken into consideration. In order to achieve this, there are provided semiconductor devices each having solder bumps as external pads, and a circuit substrate bonded to the external pads of each of the semiconductor devices through a solder paste, each of the solder bumps being made of a first lead-free solder, the solder paste being made of a second lead-free solder having a melting point lower than that of the first lead-free solder.

Abstract: One embodiment comprises a substrate having a top surface for receiving a semiconductor die. According to a disclosed embodiment, an inductor is patterned on the top surface of the substrate. The inductor is easily accessible by connecting its first and second terminals to, respectively, a substrate signal bond pad and a semiconductor die signal bond pad. In another disclosed embodiment, an inductor is fabricated within the substrate. The inductor comprises via metal segments connecting interconnect metal segments on the top and bottom surfaces of the substrate. The first and second terminals of the inductor are easily accessible through first and second substrate signal bond pads. One embodiment comprises at least one via in the substrate. The at least one via provides an electrical connection between a signal bond pad of the semiconductor die and a printed circuit board attached to the bottom surface of the substrate.

Abstract: The present invention provides a semiconductor device of the BGA configuration comprising: a wiring layer 2 arranged on a circuit substrate 1 via an insulation layer; a land metal portion 2 formed on the wiring layer 2; a solder resist 4 layered so as to cover the land metal excluding a center portion thereof and the entire surface of the circuit substrate 1; and a solder ball 5 arranged on the land metal portion defined and surrounded by the solder resist 4; wherein the land metal portion 3 has a solder ball contact surface having a groove (or a line-shaped protrusion) 7 extending continuously.

Abstract: The invention includes a multichip integrated circuit package having at least two chips electrically isolated from one another. Within the multichip integrated circuit package is a slug that is directly coupled to at least two chips, without any intervening insulating layers. The slug is physically separated at an appropriate place between the two chips, so that electrical interference between the two chips is effectively eliminated. Making the integrated circuit package begins with directly attaching the two chips to a heat dissipating slug. The heat dissipating slug can have a pre-cut groove running between the chips. Once the chips are attached to the slug, the slug is molded into the multichip integrated circuit package. Then, the slug is physically separated into two pieces from the underside, the separation running along the pre-cut groove. Usually the slug would be separated by being cut by a saw.

Abstract: A support structure of a piezoelectric vibrator greatly increase a bonding strength between a conductive bonding agent and a mounting substrate. The support structure may be provided in a piezoelectric transformer, a piezoelectric vibrator, a gyroscope, and a multilayered piezoelectric component. The mounting substrate has first to third terminal electrodes provided on both top and bottom surfaces thereof and includes first to third through holes being provided at a central portion of the terminal electrodes, respectively. After the piezoelectric transformer element is positioned on the mounting substrate such that the transformer element is spaced slightly apart from the top surface of the mounting substrate by a predetermined distance, a conductive bonding agent is applied to the node N of vibration of an input electrode of the piezoelectric transformer element and the first terminal electrode, and the first through hole is filled with the conductive bonding agent.

Abstract: A method of fabricating a package for a micro-electromechanical systems (MEMS) device. A flex circuit interconnect subassembly for the package is made by placing a flex circuit on a pad insert, attaching a carrier insert to the pad insert to deflect the lead portions of the flex circuit, and applying a cover insert to the pad insert, after the attachment of the carrier insert, to re-deflect the lead portions of the flex circuit toward the device bond sites. The flex circuit interconnect subassembly may be combined with an electronic device die/carrier subassembly to form a completed electronic device package. The flex circuit interconnect subassembly and the die/carrier subassembly are joined using mechanical interlocking layers. The invention is particularly suited for making such an electronic device die/carrier subassembly which has a MEMS die permanently affixed to a carrier.

Abstract: An electronic device comprising a semiconductor chip which is fixed to the mounting face of a wiring board through an adhesive and in which external terminals are electrically connected with electrode pads of the wiring board through bump electrodes. Recesses are formed in the electrode pads, and in the recesses the electrode pads and the bump electrodes are connected. The electrode pads are formed over the surface of a soft layer, and the recesses are formed by elastic deformation of the electrode pads and the soft layer.

Abstract: A method of manufacturing a semiconductor device comprises: a first step of interposing a thermosetting anisotropic conductive material 16 between a substrate 12 and a semiconductor chip 20; a second step in which pressure and heat are applied between the semiconductor chip 20 and the substrate 12, an interconnect pattern 10 and electrodes 22 are electrically connected, and the anisotropic conductive material 16 is spreading out beyond the semiconductor chip 20 and is cured in the region of contact with the semiconductor chip 20; and a third step in which the region of the anisotropic conductive material 16 other than the region of contact with the semiconductor chip 20 is heated.