Abstract: A multilayer capacitor includes: a body including a capacitance region in which at least one first internal electrode and at least one second internal electrode are alternately stacked on each other interposing at least one dielectric layer therebetween in a first direction; and first and second external electrodes disposed on the body and spaced apart from each other to be respectively connected to the at least one first internal electrode and the at least one second internal electrode, wherein the body includes a side margin overlapping none of the at least one first internal electrode and the at least one second internal electrode in the first direction, and a center width of the side margin is greater than a minimum width of the side margin.

Abstract: An interlayer connective structure is suitable for being formed in a wiring board, in which the wiring board includes two traces and an insulation part between the traces. The insulation part has a through hole. The interlayer connective structure located in the through hole is connected to the traces. The interlayer connective structure includes a column and a pair of protuberant parts. The protuberant parts are located at two ends of the through hole respectively and connected to the column and the traces. The protuberant parts stick out from the outer surfaces of the traces respectively. Each of the protuberant parts has a convex curved surface, in which the distance between the convex curved surface and the axis of the through hole is less than the radius of the through hole.

Abstract: Performance of a semiconductor device is improved. The semiconductor device includes a semiconductor chip and a chip component that are electrically connected to each other via a wiring substrate. The semiconductor chip includes an input/output circuit and an electrode pad electrically connected to the input/output circuit and transmitting the signal. The chip component includes a plurality of types of passive elements and includes an equalizer circuit for correcting signal waveforms of the signal, and electrodes electrically connected to the equalizer circuit. The path length from the signal electrode of the semiconductor chip to the electrode of the chip component is 1/16 or more and 3.5/16 or less with respect to the wavelength of the signal.

Abstract: A package encloses a power semiconductor die that has a first load terminal at a die frontside facing a footprint side of the package and a second load terminal arranged at a die backside facing a top side of the package. The package also includes a lead frame configured to electrically and mechanically couple the package to a support. The lead frame has a planar first outside terminal electrically connected with the first load terminal and a planar second outside terminal electrically connected with the second load terminal. The planar first outside terminal is configured to interface with the support by means of a first contact area. The planar second outside terminal is configured to interface with the support by means of a second contact area. The second contact area has a size in a range between 80% and 120% of a size of the first contact area.

Abstract: Disclosed are optical plugs and optical connectors having one or more integral alignment features used for making optical connections. In one embodiment, an optical connector comprising an optical body and at least one magnetic attachment. The optical body comprises a front side with a first surface, an optical section comprising at least one optical channel, and a datum section disposed on a second surface of the front side and comprising one or more integral alignment features. The optical body also comprises a circuit mounting portion disposed at a rear side of the optical body. The datum section may be arranged on opposite sides of the optical section. Further, the one or more integral alignment feature may be arranged at a top and a bottom of the datum section for alignment in a first direction. The first surface may also be recessed from the second surface.

Abstract: A rack unit configuration is described that includes a first printed circuit board (PCB) assembly interleaved with a second PCB assembly that is inverted with respect to the first PCB assembly. The configuration of the first PCB assembly and the second PCB assembly allow for increased component and power densities within computing systems, memory systems, etc. The increased density may be achieved while allowing sufficient mechanical clearance to allow easy component replacement and servicing (e.g., and hot pluggability). Power density may also be increased with PCB assemblies including nested and interleaved power modules.

Abstract: A connecting element can be used for a multi-chip module. The connecting element is provided for establishing an electrical connection between two elements and has a carrier and a first electrically conductive connecting structure on a first main surface of the carrier. The first connecting structure is designed in such a way that the first connecting structure connects the first and second elements to each other. A multi-chip module can have such a connecting element and two elements, wherein the two elements are electrically connected to each other in a wireless manner by the connecting element.

Abstract: A method of reducing crosstalk. The method may include forming a first contact over a first vertical conductor. The method may include forming a second contact over a second vertical conductor. The method may include forming a capacitive coupler between the first contact and the second contact, wherein the capacitive coupler is to cancel crosstalk received at the second vertical conductor from the first vertical conductor.

Abstract: Embodiments of the invention provide methods and configuration for packaging multiple semiconductor ships in a semiconductor package. In one embodiment, an integrated circuit system includes a printed circuit board, a first MOSFET device disposed on a first surface of the printed circuit board, and a second MOSFET device disposed on a second surface of the printed circuit board, wherein the first MOSFET device overlaps an edge of the second MOSFET device in a direction extending through the printed circuit board.

Abstract: A micro-wire electrode includes a substrate and an anisotropically conductive electrode extending in a length direction formed over the substrate. The electrode includes a plurality of electrically connected micro-wires formed in a micro-pattern over the substrate. The micro-pattern includes a plurality of substantially parallel and straight micro-wires extending substantially in the length direction and a plurality of angled micro-wires formed at a non-orthogonal angle to the straight micro-wires electrically connecting the straight micro-wires so that the anisotropically conductive electrode has a greater electrical conductivity in the length direction than in another conductive electrode direction.

Abstract: An electronic device may contain components such as flexible printed circuits and rigid printed circuits. Electrical contact pads on a flexible printed circuit may be coupled electrical contact pads on a rigid printed circuit using a coupling member. The coupling member may be configured to electrically couple contact pads on a top surface of the flexible circuit to contact pads on a top surface of the rigid circuit. The coupling member may be configured to bear against a top surface of the flexible circuit so that pads on a bottom surface of the flexible circuit rest against pads on a top surface of the rigid circuit. The coupling member may bear against the top surface of the flexible circuit. The coupling member may include protrusions that extend into openings in the rigid printed circuit. The protrusions may be engaged with engagement members in the openings.

Abstract: A circuit including a flexible substrate and at least one electric element attached to the substrate, the substrate including at least one cavity arranged near the electric element and helping to break or distort the electric element in response to a flexion or stretching of the substrate. Application in particular is to the manufacture of tear-proof electronic micromodules.

Abstract: A semiconductor package substrate suitable for supporting a damage-sensitive device, including a substrate core having a first and opposite surface; at least one pair of metal layers covering the first and opposite surfaces of the package substrate core, which define first and opposite metal layer groups, at least one of said layer groups including at least one metal support zone; one pair of solder mask layers covering the outermost metal layers of the at least one pair of metal layers; and a plurality of routing lines; wherein the at least one metal support zone is formed so that it lies beneath at least one side of the base of the damage-sensitive device and so as to occupy a substantial portion of the area beneath the damage-sensitive device which is free of said routing lines; a method for the production of such substrate is also described.

Abstract: The invention relates to a high-voltage insulation circuit board which is used in an electric power apparatus such as an electric power converter or the like such as power semiconductor device, inverter module, or the like and provides an insulation circuit board in which electric field concentration at the end sections of a wiring pattern is reduced, partial discharging is suppressed, and a reliability is high. According to the invention, there is provided an insulation circuit board having: a metal base substrate; and wiring patterns which are formed onto at least one of the surfaces of the metal base substrate through an insulation layer, characterized in that between two adjacent wiring patterns in which an electric potential difference exists among the wiring patterns, at least one or more wiring patterns or conductors which are in contact with the insulation layer and have an electric potential in a range of the electric potential difference between the adjacent wiring patterns are arranged.

Abstract: A printed wiring board includes an outermost interlayer resin insulation layer, n outermost conductive layer formed on the outermost interlayer resin insulation layer and including multiple alignment marks, a connection wiring structure connecting the alignment marks, and a solder-resist layer formed on the outermost interlayer resin insulation layer and the outermost conductive layer. The solder-resist layer has openings exposing the alignment marks, respectively, and each of the alignment marks has an electroless plated film formed on each of the alignment marks.

Abstract: A substrate includes: a base; and a plurality of bonding terminals arranged on at least one surface of the base, wherein the plurality of bonding terminals include a first bonding terminal and a second bonding terminal, the first bonding terminal and the second bonding terminal include, in plan view of the base, a circle contacting portion extending along the circumference of a circle tangent to the first bonding terminal and the second bonding terminal, all of the plurality of bonding terminals are arranged so as not to protrude from an area including the circle and the inside thereof, and the circle contacting portion includes at least a first circle contacting portion disposed in the first bonding terminal and a second circle contacting portion disposed in the second bonding terminal.

Abstract: A printed circuit board includes a board body having a routing-limited area. The routing-limited area is provided with at least one solder pad that is adapted for supporting a metal support thereon. Preferably, the printed circuit board further includes a protrusion block disposed on the solder pad, and having a height greater than that of a signal trace that passes the routing-limited area.

Abstract: A printed wiring board has a packaging substrate having multiple pads, and a transmission substrate mounted on the multiple pads of the packaging substrate. The packaging substrate has a pad group constituted of pads which mount an electronic component, the multiple pads mounting the transmission substrate includes a first pad positioned in a peripheral portion of the packaging substrate and a second pad positioned between the first pad and the pad group, the second pad is electrically connected to a signal pad of the pads in the pad group, and the transmission substrate includes a horizontal wiring which electrically connects the second pad and the first pad and which transmits a signal between the second pad and the first pad.

Abstract: The present description relates to the field of fabricating microelectronic devices, wherein a microelectronic device may have a hexagonal confirmation for signal nodes and ground nodes which utilizes the cross-talk reduction by cancellation property of geometrically symmetry and orthogonality to reduce signal node to ground node ratio for increasing signaling density.

Abstract: A microelectronic assembly can include a circuit panel having first and second surfaces and panel contacts at each surface, and first and second microelectronic packages having terminals mounted to the panel contacts at the first and second surfaces, respectively. The circuit panel can electrically interconnect terminals of the first package with corresponding terminals of the second package. Each package can include a substrate having first and second surfaces, a microelectronic element, conductive structure extending above a front face of the microelectronic element, and parallel columns of terminals at the second surface. The terminals of each package can include first terminals in a central region of the respective second surface and configured to carry address information usable by circuitry within the package to determine an addressable memory location within the respective microelectronic element.

Abstract: A microelectronic package can include a substrate and a microelectronic element having a rear face facing a first surface of the substrate, a front face, and a column of element contacts extending in a first direction. The microelectronic element can include stacked electrically interconnected semiconductor chips. Edges of the microelectronic element can define an axial plane extending in the first direction and a third direction normal to the rear face. The package can include columns of terminals extending in the first direction at a second surface of the substrate. The terminals can include first terminals exposed in a central region of the second surface and configured to carry address information usable by circuitry within the package to determine an addressable memory location. The central region may have a width not more than 3.5 times a minimum pitch between adjacent terminal columns. The axial plane can intersect the central region.

Abstract: A microelectronic package can include a microelectronic element having a face and a plurality of element contacts thereon, a substrate having first and second surfaces, and terminals on the second surface configured for connecting the package with at least one external component. The substrate can have substrate contacts on the first surface facing the element contacts of the microelectronic element and joined thereto. The terminals can include first terminals arranged at positions within first and second parallel grids. The first terminals of each grid can be configured to carry address information usable by circuitry within the microelectronic package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within the microelectronic element. The signal assignments of the first terminals in the first grid can be a mirror image of the signal assignments of the first terminals in the second grid.

Abstract: A microelectronic assembly can include a circuit panel having first and second panel contacts at respective first and second surfaces thereof, and first and second microelectronic packages each having terminals mounted to the respective panel contacts. Each package can include a microelectronic element having a face and contacts thereon, a substrate having first and second surfaces, and terminals on the second surface configured for connecting the package with an external component. The terminals can include first terminals at positions within first and second parallel grids. The first terminals can be configured to carry address information usable by circuitry within the package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within the microelectronic element. Signal assignments of the first terminals in the first grid can be a mirror image of signal assignments of the first terminals in the second grid.

Abstract: A microelectronic assembly can include a microelectronic package connected with a circuit panel. The package has a microelectronic element having a front face facing away from a substrate of the package, and electrically connected with the substrate through conductive structure extending above the front face. First terminals provided in first and second parallel grids or in first and second individual columns can be configured to carry address information usable to determine an addressable memory location from among all the available addressable memory locations of the memory storage array. The first terminals in the first grid can have signal assignments which are a mirror image of the signal assignments of the first terminals in the second grid.

Abstract: A microelectronic element having a memory storage array has a front face facing away from a substrate of a microelectronic package, and is electrically connected with the substrate through conductive structure extending above the front face. First terminals are disposed at locations within first and second parallel grids of the package. The first terminals of each grid are configured to carry address information usable to determine an addressable memory location from among all the available addressable memory locations of the memory storage array. The first terminals in the first grid have signal assignments which are a mirror image of the signal assignments of the first terminals in the second grid.

Abstract: A differential transmission circuit includes a pair of transmission line conductors and a ground conductor layer, wherein the pair of transmission line conductors include a first straight line region where both the pair of transmission line conductors extend in parallel to each other in a first direction with a first width in a first layer, a first cross region where one of the pair of transmission line conductors is formed in the first layer, the other thereof is formed in a second layer, and the pair of transmission line conductors cross the each other in a three-dimensional manner, the first cross region being disposed on the front side of the first straight line region, and wherein each of the widths of the pair of transmission line conductors in the first cross region is smaller than the first width.

Abstract: A printed wiring board including a core substrate, a build-up layer formed over the core substrate and including a first insulating layer, a conductor layer formed over the first insulating layer, and a second insulating layer formed over the conductor layer, and one or more wiring patterns formed over the first insulating layer. The conductor layer includes conductor portions, and the conductor portions have notched portions, respectively, facing each other across the wiring pattern.

Abstract: A package structure comprises a substrate, a plurality of electronic components configured and structured on the substrate, a plurality of metal resilient units electrically connected to the substrate, and an encapsulation body encapsulating the plurality of electronic components and the plurality of resilient units together with the substrate. Part of each of the plurality of metal resilient units away from the substrate is exposed out of an exterior surface of the encapsulation body.

Abstract: A printed circuit board includes a first to a fifth connector pads, a first to an eighth coupling capacitor pads, a first to a tenth transmission lines, a first via and a second via, a first to a fourth sharing pads, and a voltage converting circuit. The printed circuit board is operable to selectively support different types of connectors.

Abstract: A process for fabricating a wiring board is provided. In the process, a wiring carrying substrate including a carry substrate and a wiring layer is formed. Next, at least one blind via is formed in the wiring carrying substrate. Next, the wiring carrying substrate is laminated to another wiring carrying substrate via an insulation layer. The insulation layer is disposed between the wiring layers of the wiring carrying substrates and full fills the blind via. Next, parts of the carry substrates are removed to expose the insulation layer in the blind via. Next, a conductive pillar connected between the wiring layers is formed. Next, the rest carry substrates are removed.

Abstract: Embodiments of the present invention provide a semiconductor package which includes: a semiconductor chip to which one end of each of a plurality of wires is connected; and a board on which the semiconductor chip is fixed, and a plurality of board wires to which the plurality of corresponding wires are connected are disposed, wherein the board includes: a first wiring pair that includes a first pair of wires in parallel with each other and first two board wires connected to the corresponding wires, one of the wires connected to one of the board wires crossing the other board wire without contact with the other board wire, and a second wiring pair that is provided adjacent to the first wiring pair and includes a second pair of wires in parallel with each other and second two board wires connected to the corresponding wires without a crossing.

Abstract: A magnetic component includes a bobbin structure adapted for attachment to a circuit board. The magnetic component may include a magnetically permeable core and a conductive winding. The bobbin structure may include a gap for inserting the edge of a circuit board. Potential applications of the magnetic component include mechanically and electrically interconnecting two or more circuit boards in a substantially side-by-side configuration while providing increased heat dissipation from the magnetic component, improving power density of the electronic device, reducing electronic device profile, allowing magnetic isolation between high-voltage and low-voltage circuits and allowing single-sided and double-sided circuit boards to be used in a single circuit. Also, a circuit board assembly may have two or more circuit boards electrically and mechanically connected by at least one magnetic component.

Abstract: Embodiments are directed to an apparatus and fabrication method to form pad arrays on the edge of a substrate wafer substrate. Embodiments of the invention make it possible for surface mount devices to be bonded vertically (i.e. on their side) using standard semiconductor assembly processes.

Abstract: Embodiments of the present invention relate to circuit layouts that are compatible with printing electronic inks, printed circuits formed by printing an electronic ink or a combination of printing and conventional blanket deposition and photolithography, and methods of forming circuits by printing electronic inks onto structures having print-compatible shapes. The layouts include features having (i) a print-compatible shape and (ii) an orientation that is either orthogonal or parallel to the orientation of every other feature in the layout.

Abstract: A filter of the present invention is a filter including a substrate and a filter element mounted on the substrate, wherein the substrate is provided with a plurality of wiring layers including a filter element wiring layer which is formed with wirings and connected with the filter element, an insulating layer interposed between the plural wiring layers and a ground pattern formed in at least a part of a wiring layer under the filter element wiring layer; and the thickness of the insulating layer interposed between the filter element wiring layer and the other wiring layer is smaller than the width of the wiring formed in the filter element wiring layer, and is larger than the thickness of the other wiring layer. By such a configuration, a thin, high-suppression and high-isolation filter can be realized.

Abstract: Disclosed is an electronic device module including a module substrate having first and second electronic device pair portions. The first electronic device pair portion may include a first and a second contact pad area and a first via area between the first and second contact pad areas. The first electronic device pair portion may also include a first layer and a second layer. The first layer may include a plurality of first lines connecting a plurality of contact pads in the first contact pad area on one side of the module substrate to a plurality of vias. The second layer may include a plurality of second lines connecting a plurality of contact pads in the second contact pad area to a plurality of vias in the via area. The second layer may also include a plurality of third lines connecting the first and second electronic device pair portions.

Abstract: A printed circuit board (PCB) includes a ball grid array (BGA). The PCB further includes a first BGA pad having a circular shape, and a first via having a circular shape, where the circular shape of the first via overlaps a portion of the circular shape of the first BGA pad and is rotated diagonally relative to a center of the first BGA pad. The PCB also includes a second BGA pad having a circular shape, and a second via having a circular shape, where the circular shape of the second via overlaps a portion of the circular shape of the second BGA pad and is rotated diagonally relative to a center of the second pad, and where a center of the second via is located at a first distance from the center of the first via and at a first angle relative to an axis that crosses a center of the first via.

Abstract: Provided is a method and system for designing an integrated circuit (IC) substrate, the substrate being formed to include at least one die. The method includes providing at least portions of IC power and a grounding function on a metal 2 substrate layer and utilizing all of a metal 3 substrate layer for the grounding function. Portions of the metal 2 layer and a metal 4 layer are utilized for the IC power, wherein all of the IC power is centralized underneath the die.

Abstract: A wired circuit board includes a first insulating layer; a first wire formed on the first insulating layer; a second insulating layer formed on the first insulating layer so as to cover the first wire; and a second wire formed on the second insulating layer so as to be arranged in opposed relation to the first wire in a thickness direction. The thickness of the first wire is 1 ?m or less and is ? or less of the thickness of the second insulating layer.

Abstract: A method and apparatus for active line interface isolation have been described.

Abstract: A microelectronic package having a radio frequency (RF) amplifier circuit and, incorporating harmonic rejection filters and matching circuits integrally formed in the package is disclosed. A harmonic rejection filter may comprise a metal-insulator-metal (MIM) capacitor serially coupled between bond pads disposed on a RF amplifier circuit die, a first wire bond coupling a first bond pad to a package output, where the first bond pad is coupled to the output of the RF amplifier, and a second wire bond coupling a second bond pad to a package ground. The harmonic rejection filter may be appropriately configured to filter one or more harmonics at different frequencies.

Abstract: The circuit device includes a first transmitting inductor, a first insulating layer, a first receiving inductor, and a second receiving inductor. The first transmitting inductor is constituted of a helical conductive pattern and receives a transmitted signal. The first receiving inductor is located in a region overlapping the first transmitting inductor through the first insulating layer. The first receiving inductor is constituted of a helical conductive pattern, and generates a received signal corresponding to the transmitted signal input to the first transmitting inductor. The second receiving inductor is connected in series to the first receiving inductor, and constituted of a helical conductive pattern. The second receiving inductor generates a voltage in an opposite direction to that generated by the first receiving inductor, in response to a magnetic field of the same direction.

Abstract: Provided is a signal transmission circuit capable of realizing the same effects as those in a conventional manner that employs a complicated circuit by using no complicated circuit, that is, by a simple circuit. The signal transmission circuit includes: a transmission path having a first impedance; a terminating resistor having a predetermined resistance; a transmission path having a second impedance, which is connected to the transmission path and the terminating resistor, the second impedance being higher than both of the first impedance and the predetermined resistance; and an input buffer for receiving a signal at a connection portion of the transmission path and the transmission path.

Abstract: An electrically conductive structure includes a first conductive structure and a second conductive structure. Each has a conducting section at one end and a coupling section at the other end. The first and second conducting sections are electrically connected to a power and ground contact of an electronic device, respectively. The first and second coupling sections are respectively connected with power and ground layer of a circuit board. The first coupling sections are connected with the first conducting section through first extending sections and the second coupling sections are connected with the second conducting section through second extending sections. At least two coupling sections of the conductive structures are arranged in pairs. The first conductive structure and the second conductive structure are arranged in a staggered array to form two wiring loops having opposite current directions, thereby generating a magnetic flux cancellation effect.

Abstract: In accordance with a first embodiment, the present invention provides a circuit substrate comprising a first surface; a second surface; a first via having a first end near said first surface and a second end near said second surface; a second via having a first end near said first surface and a second end near said second surface; a first conductive element electrically coupling said first end of said first via and said first end of said second via; a second conductive element electrically coupling said second end of said first via and said second end of said second via; an input signal line coupled to said first via; and an output signal line coupled to said second via.

Abstract: An exemplary PCB includes a first reference layer, a first signal layer, a second signal layer, and a third signal layer in that order, a first differential pair is arranged in the first signal layer in edge-coupled structure and references the first reference layer, a distance between the first signal layer and the second signal layer is greater than a distance between the first reference layer and the first signal layer, a second differential pair is arranged in the second signal layer and the third signal layer in broad-coupled structure. The PCB has a high density layout of transmission lines.

Abstract: A semiconductor module includes a plurality of rectangular shaped semiconductor devices which are arranged in two rows such that each pair of adjacent semiconductor devices is in orientations differed by 90 degrees from each other. A plurality of wirings connect the semiconductor devices included in one of the two rows to the semiconductor devices included in the other row such that the semiconductor devices arranged in the same orientations are connected to each other.

Abstract: A printed circuit board includes a base and a signal trace laid on the base. The signal trace includes a plurality of straight line segments parallel to the first fibers. The signal trace is laid on the base in such a manner that the line segments of the signal trace mapped on the base partly superpose the first fibers and partly superpose gaps between two adjacent first fibers.

Abstract: In some embodiments, a system includes a memory controller chip, memory chips on a first substrate, and a module connector. A first group of conductors is included to provide read data signals from at least some of the memory chips to the memory controller chip, and a second group of conductors to provide read data signals from the connector to the memory controller chip. The module connector may receive a continuity card or memory module. Other embodiments are described.

Abstract: Provided is a system adopting a differential signaling system including a low frequency signaling line arranged to be adjacent to a pair of differential signaling lines in parallel to each other, for transmitting a signal having a frequency which is smaller than a frequency of a signal to be transmitted through the pair of differential signaling lines, in which a transmission end of the low frequency signaling line is connected to a ground pattern through a first capacitive element, and a reception end of the low frequency signaling line is connected to the ground pattern through a second capacitive element. Thus, it is possible to provide, easily and at a low cost, a differential signaling system in which a common mode noise is eliminated without increasing the number of pins.