Abstract: An electrical connecting device including a first circuit board providing thereon with input/output terminals, each of the terminals having a tip surface coated with gallium and a second circuit board providing thereon with contact terminals, each of the terminals having a tip surface coated with indium or tin. A low-melting point alloy layer is formed by a mutual action between gallium and indium or tin, when the input/output terminals of the first circuit board are in contact with the respective terminals of the second circuit board and the terminals are electrically connected to each other. The second metal layer includes a plurality of wire-like metal supports extending substantially perpendicular to the surface of the terminal and a low-melting point metal retained by the wire-like metal supports.

Abstract: Optoelectronic active/passive components (15) are directly mounted to a front surface of a capsule (1) of an electrically isolating, opaque material. The surface on which the components (15) are mounted is retracted in relation to other parts of the front surface where holes (11) for guide pins of a connectable coupling device (7) for optical fibers are provided. The components (15) are electrically connected to, e.g. by means of loose wires, conductor paths (17) also arranged on the retracted front surface part. In a particular designed mounting method the optical components may be provided in the shape of a plate having its electric terminals at its rear side. On the electric terminals isles, e.g. of tin solder, are placed, the plate is placed at the front side of the capsule, where holes are provided extending into the capsule up to electric conductive paths inside the capsule, and the soldering isles are heated so that the tin solder flows into the holes and contacts the electric conductors therein.

Abstract: The present invention is a printed circuit board design having a configurable voltage supply and a method for implementing a configurable voltage supply PCB with a family of circuit designs. The printed circuit board is designed such that voltage supply planes can be configured to match the device requirements for different ICs inserted into the PCB. The PCB comprises electrically isolated conductive layers that are split into a plurality of electrically isolated fixed and undefined voltage planes. The fixed voltage planes are each coupled to a different supply voltage provided by an external power supply. Undefined voltage planes are coupled to fixed voltage planes with insertable conductive jumpers to obtain the desired voltage supply for each voltage plane. The voltage plane configuration of a particular PCB can be changed depending on where jumpers are inserted to accommodate device voltage requirements over a family of devices.

Abstract: A personalizable multi-chip carrier including a substrate, first and second pluralities of conductors arranged on respective first and second parallel planes, the first and second pluralities of conductors defining a grid of conductors arranged over the substrate and defining a multiplicity of crossing locations at which conductors of the first and second pluralities cross each other, apparatus for interconnecting the first and second pluralities of conductors at locations adjacent the multiplicity of crossing locations and including a plurality of fusible links.

Abstract: An interconnection topography for microprocessor-based communication nodes consists of opposite arrays of client nodes and resource nodes, with each client node connected to one resource node by a data transfer link, each resource node connected to a resource trunk by a data transfer link, and each node connected to just four neighboring nodes by data transfer links. Communication nodes in the topography are microprocessor controlled, and comprise random access memory and data routing circuitry interfaced to the data transfer links. In one aspect resource nodes are provided with a map of the interconnection topography for use in routing data. In another aspect, individual ones of the communication nodes are programmed as servers for receiving client requests and scheduling routing of resource data.

Abstract: A signal line network on a substrate for interconnecting IC chips is programmable after manufacture to define the desired connections. The signal lines comprise line segments arranged end-to-end in both horizontal and vertical directions and are connectible at their ends and the vertical and horizontal segments are connectible at their crossings. A dedicated contact pad is connected to each segment. A plurality of bonding pads are adjacent several segments and each pad has arms extending across the several segments and are individually connectible to them. All connectible junctions comprise amorphous silicon antifuses which are normally insulators and are selectively programmable after the substrate is manufactured by applying a voltage pulse across the antifuse to render it conductive. The pads are arranged in a pattern in cells, all cells having the same pad pattern to facilitate probe connections for programming and testing.

Abstract: A method is provided for hermetically sealing a surface-mounted thick film electronic module within a cover soldered to a ceramic substrate, under the circumstances in which the input/output terminals of the electronic module are electrically interconnected with their corresponding external conductors on the exterior of the cover with a number of conductors. The integrity of the hermetic seal is promoted by routing the conductors beneath the ceramic substrate, as opposed to printing the conductors directly on the surface of the ceramic substrate, which necessitates that a dielectric material be placed intermediate the conductors and the bond material so as to electrically isolate the conductors from the bond material and cover. Consequently, an advantage of the present invention is the avoidance of a material mismatch between the dielectric material and the bonding material and the cover.

Abstract: An electronic package that is tested before the leads of the package are cut and bent into a final shape. The electronic package has a plurality of leads that extend from an outer housing of the package. The package is typically rectangular in shape and has a group of leads extending from each side of the housing. Extending along each group of leads is a strip of dielectric material that is spaced an offset distance from the side of the housing. The package is tested by placing a plurality of corresponding test pins into contact with the leads over their final cut and formed length in an area between the housing and the dielectric strip. The area of contact corresponds to the ends of the final assembled leads, so that the actual impedance of the leads over their final cut and formed length are tested. The dielectric strip provides structural support for the leads during the handling and testing of the package.

Abstract: A plurality of semiconductor arrangements arranged on interconnects are cected parallel to one another in a module. The arrangements lie opposite one another in pairs. At least one pair and at most two pairs of semiconductor arrangements are arranged to follow one another in the direction of an axis of the module and are further connected to lead conductors. Positions of the lead conductors with respect to the contacted semiconductor arrangements are the same for each pair of semiconductor arrangements or, respectively, two respective pairs of semiconductor arrangements. Corresponding lead conductors are connected to one another above the interconnects.

Abstract: An electronic device (100) has a heatsink (116) and electrical contacts (120) which are originally all part of a support frame (200). After assembly, the border of the support frame (202) is broken off, thereby electrically isolating the electrical contacts (120) from one another, and from the heatsink (116). The electrical contacts (120) and the heatsink (116) are coplanar. In one version, the electrical contacts (120) do not extend past the circuit board (102) of the device (100).

Abstract: A direct connection for printed circuit boards where a primary board has a slot therethrough with slight edge projections which control the width of the slot to close tolerances. Spaced parallel conductive strips on the surfaces of the primary board terminate at the slot. A secondary board has an insert portion sized and configured for insertion into the slot in a close fit with the edge projections to maintain the boards mutually perpendicular. Spaced parallel strips on the insert are disposed adjacent the termination of the primary board strip. The strips are interconnected by soldering to provide direct circuit interconnection between the primary and secondary boards.

Abstract: The present invention provides an improved circuit board for mounting integrated circuit chips and a technique for manufacturing the circuit board. The board permits direct chip attachment to the circuit board by providing the necessary geometry for the footprint pattern of the chip connections without the necessity of multi-level packaging using chip carriers. The circuit board includes a substrate with plated through holes, and a film of photoresist dielectric material disposed on the substrate. The dielectric material is photo patterned to form vias which are then filled with conductive material. Electrical connection pads are formed on the exposed surface of the film of dielectric material in the pattern of the chip footprint to be mounted thereon.

Abstract: A method for manufacturing a position detector having a movable permanent magnet (5) and a circuit board (6) having a magnetic sensor circuit (10.about.13) mounted thereon for detecting the displacement of the permanent magnet. A selective connection portion (8,9) in the magnetic sensor circuit capable of being selectively placed into at least two different circuit patterns exhibiting two different output characteristics (A,B) is provided. Then, the connection in the selective connection portion (8,9) is changed by adding an electrical conductor (FIGS. 1a, 1b) or removing (FIGS. 2a, 2b) portions of pattern conductors in the selective connection portion (8,9) to place the magnetic sensor circuit into either one of the at least two different circuit patterns (FIGS. 4,5) according to necessity.

Abstract: A circuit control device includes two intermating foil pads separated from one another by a narrow gap having a maximum dimension of 0.006 inches. A circuit path having one side connected to one of the pads and a second side connected to the other of the pads is selectively closed and opened by solder application and removal operations. Interdigitated, triangular fingers which are intermated to form the device ensure the formation of acutely angled junctures along the gap to ensure solder bridging of the gap. Emergency control elements are coupled to the circuit control device to permit control of an associated circuit path if the circuit control device itself fails. In that event, an emergency control device is coupled to the emergency control elements to control opening and closing of the circuit path.

Abstract: A two-layer or multilayer printed circuit board (1) comprises a support plate (2) carrying a first conductor pattern (3) and a second conductor pattern (21) which is connected to the support plate (2) via an adhesive layer (13) consisting of adhesive material, a solder-stop layer (30) being applied to the second conductor pattern.

Abstract: A multi-layer circuit board includes electrical interconnections between adjacent circuit board layers of the multi-layer board. A via hole is provided through a circuit board layer. The via hole is filled with a via metal. The via metal is plated with a low melting point metal. An adhesive film is deposited over the circuit board layer. Adjacent layers of the multi-layer circuit board are stacked and aligned together. The layers are laminated under heat and pressure. The low melting point metal provides an electrical interconnection between adjacent layers.

Abstract: An electrical interconnect and a method of fabricating an electrical interconnect are provided. A first transparent dielectric layer is disposed on top of a support structure. A conductive circuit layer is plated above the first dielectric layer. Separate conductive layers are plated on top of the conductive circuit layer to produce conductive vias. A second transparent dielectric layer is disposed around the conductive layers. Contact tips are electrically connected to the top surface of the separate conductive layers. The interconnect may be visually aligned so that the contact tips brought into contact with target connections. In addition, the support structure may be partially removed to allow a flexible interconnect.

Abstract: A multi-layer printed circuit board or card including at least one passage in at least one of the layers of the circuit board or card for preventing the diffusion of heat throughout the circuit board or card during the securing or removal of components in plated through holes in the circuit board or card by the heating of the plating material to a temperature above a melting point of the plating material.

Abstract: A modulated electronic breadboard assembly kit for constructing and testing prototype circuits. The kit includes a motherboard that has a plurality of connectors having leads that are connected to a plurality of corresponding pins. The leads between the various connectors can be coupled together by wires wrapped around the pins. The kit also contains a plurality of discrete modules which can be plugged into the connectors of the motherboard. The discrete modules each provide a basic electronic function such as an operational amplifier, an analog to digital converter, a comparator, etc. A prototype circuit can be built with the present invention by merely selecting the desired circuit functions, plugging the corresponding modules into the motherboard and then wiring the leads of the board to connect the modules.

Abstract: A substantially planar insulating sheet of high temperature printed circuit board material (11) is used to form a leadframe strip (18, 19, 21) for a semiconductor package (20). The leadframe strip (18, 19, 21) includes a die attach opening (12) through the insulating sheet (11). A plurality of metallized areas (13, 22, 23) on the insulating sheet (11) form bonding pads (13) and package leads (22). Conductive holes (14) electrically connect the bonding pads (13) and the package leads (22).

Abstract: An integrated circuit packaging system with an integrated circuit die mounted onto a substrate having a top side ground plane between the integrated circuit and the substrate, a bottom side ground plane and short high frequency connections between the two ground planes. The top side ground plane decreases signal degradation due to reflections by providing high frequency ground access close to the die and by providing a transmission line for bond wires. A grid of conductive vias through the substrate improves thermal conductivity and provides the short high frequency current path for the top side ground plane. The die is separated from the top side ground plane by a dielectric layer which also has a conductive layer next the die to provide a back bias voltage.

Abstract: An electrical packaging structure has a plurality of semiconductor chips arranged on a substrate and input wirings to the semiconductor chips connected thereto. The input wirings are distributed through a wiring board arranged on the substrate.

Abstract: A system and method for interconnecting electronic components on a circuit board that minimize etch lines, minimize stub lengths, reduce the number of vias that are needed, and densely pack electronic components on the circuit board. According to system and method, electronic components are attached to the top planar surface of the circuit board such that adjacent components are rotated 180.degree. in the plane of the top planar surface. These adjacent electronic components also are offset from one another. The electronic components that are attached to the bottom planar surface of the circuit board also have adjacent electronic components rotated 180.degree. in the plane of the bottom planar surface, and are offset. The arrangement of the components disposed at the bottom planar surface is a mirror image of the components disposed at the top planar surface.

Abstract: The invention concerns a Multi-Chip Module (MCM), which can be viewed as similar to a printed circuit board, but with the conductors interwoven in a 3-dimensional array. In the invention, the conductors are arranged such that both power supply conductors and ground conductors are interwoven around signal conductors, and provide shielding for the signal conductors, thus reducing cross-talk.

Abstract: A method is disclosed of simultaneously laminating circuitized dielectric layers to form a multilayer high performance circuit board and making interlevel electrical connections. The method selects two elements which will form a eutectic at one low temperature and will solidify to form an alloy which will only remelt at a second temperature higher than any required by any subsequent lamination. The joint is made using a transient liquid bonding technique and sufficient Au and Sn to result in a Au-Sn20wt% eutectic at the low temperature. Once solidified, the alloy formed remains solid throughout subsequent laminations. As a result, a composite, multilayer, high performance circuit board is produced, electrically joined at selected lands by the solid alloy.

Abstract: A semiconductor package is described which has external connection points (pins, pads, etc.) which may be configured from outside of the package. In one embodiment, this is accomplished with programming holes which pass through and form contact surfaces with various conductors within the package. Conductive material is then deposited into selected holes, forming connections between all of the contact surfaces in any hole. In another embodiment, configurability is accomplished via conductive pads disposed on the exterior surface of the package. Conductive jumpers are then used to connect selected pads. An auxiliary externally effected power plane and bus-bar structure are also described.

Abstract: There is provided a configurable electronic circuit board which comprises a board including many modular sockets in a minimum unit each having a size and the number of pins both standardized, the modular sockets being arranged regularly parallely and connected to each other at terminals thereof through simple wirings, a pin adapter composed of adapter pins insertable into the modular socket, of an adapter socket into which electronic circuit parts are insertable, and of socket wirings for making connection between the adapter socket and the adapter pins, a switching station adapter composed of adapter pins insertable into the modular socket, and of a wiring changeover switch and a fuse for determining the connection of wiring among the adapter pins, and a bypass adapter being inserted into a modular socket not used, and composed of adapter pins insertable into the modular socket, and of fixed wiring for simply bypass-connecting among the adapter pins, whereby an arbitrary circuit is realizable by inserting ea

Abstract: Disclosed is a electrical circuit (20) that includes a plurality of integrated circuits (22a,22b,22c,22d). At a distance from the perimeter (30,32) of each integrated circuit are disposed a series of spaced-apart bond pads (28). The integrated circuits are placed on a substrate material (24), such that there exists a plurality of channels (36, 38, 40) between the integrated circuits. Rows and columns of conductive traces are formed on the substrate material. Electrical connections are routed between the bond pads, preferentially using the conductive traces formed in the side channels (36, 38) that lie between the perimeter of an integrated circuit and its associated bond pads. The number of conductive traces routed in central channel (40) is minimized in order to reduce the overall area required for interconnections, thereby maximizing the area available for mounting integrated circuits on the substrate.

Abstract: An interlayer connection structure for an integrated circuit includes a substrate, a first level horizontal conductor formed on the substrate, an interlayer insulator formed to cover the first level conductor, a second level horizontal conductor formed on the interlayer insulator, and a vertical conductive pillar extending through the interlayer insulator for interconnecting the first level horizontal conductor and the second level horizontal conductor. The vertical conductive pillar has a side surface coplanar with a longitudinal side surface of the first level horizontal conductor at a position where the vertical conductive pillar is in electric contact with the first level horizontal conductor.

Abstract: A multi-chip semiconductor module (10,20) includes a plurality of semiconductor chips (13,13') mounted on a substrate (11) and a plurality of conductive vias (16) extending through the substrate (11). A conductive network (17) formed on the substrate and a plurality of leads (19) are mounted to edges of the substrate (11) and extend away from the substrate (11). Each of the leads (19) is electrically coupled to a contact pad (14) of an integrated circuit chip (13,13'), and each conductive vias (16) has a first end coupled to the conductive network (17) and a second end exposed on the bottom surface of the substrate (11) allowing electrical access to many of the contact pads (14) of the integrated circuit (13,13').

Abstract: To minimize the area of an L-shaped channel wiring region between VLSI circuit blocks, a trunk 1 is formed in the direction along L-shaped sides A and B in the wiring region interposed between the L-shaped sides A and B of circuit blocks CB1 and CB2 having terminals on their sides. The trunk 1 is converted into a polygonal line so as to occupy two tracks. The polygonal line is obtained by combining a line segment in the direction along the L-shaped sides A and B with a line segment parallel to the middle angle direction D of an L-shaped angle.