Abstract: Multistage configuration and power setting for a processor includes an on-die configuration signal fuse block programmed during manufacturing, configuration signal Control and I/O circuitry, a configuration change control signal output indicating when the configuration signals are going to change, and voltage regulators and clock generators that rely on the configuration change control signal to begin the system configuration change and boot sequences. The processor actively drives its configuration signal states. Multistage configuration and power setting also enables the processor to change its configuration states during operation.

Abstract: An integrated circuit package is constructed by attaching lower dies to a substrate that has bond fingers deposited on its surface. One lower die and its associated bond fingers are located offset from the center of the substrate. The lower dies are electrically coupled to the substrate's bond fingers with lower bond wires. An upper die is stacked on at least one of the lower dies. The upper die is electrically coupled, with bond wires, to the lower die upon which it is mechanically coupled. Each of the lower dies may be coupled to the other lower die with bond wire bridges that span the lower bond wires. The upper die may be electrically coupled, with bond wire bridges, to any or all of the lower dies.

Abstract: A wiring substrate for a display panel having a plurality of wiring electrodes thereon includes an airtight container formed by disposing an opposing substrate through a frame member on the surface of the substrate having the wiring electrodes. The airtight container has an image forming member therein, in which an average angle between a cross section of the wirings and the wiring substrate in an orthogonal projection area of the image forming member onto the wiring substrate is obtuse, while an average angle between a cross section of the wirings and the wiring substrate in an area where the frame member is disposed is acute.

Abstract: An interconnect architecture in which a substrate such as a printed circuit board includes multiple conductive layers separated by one or more interposed insulating layers, the conductive layers being adapted to receive a high density array of interconnect elements such as a ball grid array (BGA). In certain preferred embodiments, a printed circuit board may provide a very low resistance interconnect forming the drain and source terminals of a lateral power MOSFET device incorporating a high density array of alternating source and drain interconnect elements, such as a BGA. In such embodiments, source and drain currents may be routed on different conductive layers separated by one or more interposed insulating layers. The upper conductive layer may include laterally non-conductive regions accommodating conductive columns that are connected to the lower conductive layer.

Abstract: A conductive sash is etched around the periphery of a land grid array interconnection on a carrier for dense integrated circuit connections. If the array comprises more than one module or module chip domain, the conductive sash is also positioned between the modules. The dimensions of the sash are such that it is slightly larger than a frame of an interposer or other electrical connector which is placed upon the array. In this fashion, the interposer or other electrical connector rests upon the sash and provides protection against particulate and gaseous contamination of the array.

Abstract: An electronic device having stacked modules and method for producing it are described. Each module has a chip. Each chip is mounted on a stack intermediate plane. The stack intermediate planes of a stack have identical layouts, while chip select circuits which can be set irreversibly via contact areas are disposed on the chips, which chip select circuits enable an irreversible assignment of the contact areas to the stack intermediate planes.

Abstract: Disclosed is a technique capable of improving a power supply efficiency in a power supply circuit. A power MOSFET in a high side of a combined power MOSFET constituting a DC-DC converter is constituted of a horizontal MOSFET, and a power MOSFET in a low side thereof is constituted of a vertical MOSFET.

Abstract: An information-processing device comprises at least one crossbar-board; a plurality of back panels detachably connected electrically and mechanically to different sides of the crossbar-board; and at least one motherboard detachably connected electrically and mechanically to each of the back panels. The crossbar-board has a switching element mounted thereon. The motherboard has an information-processing semiconductor element mounted thereon.

Abstract: An electronic assembly is disclosed. The electronic assembly includes a lower portion and a first elongate trace formed on an upper surface of the lower portion. The trace is covered by an upper portion, and an opening formed through an upper surface of the upper portion extends to the trace to expose a portion of the trace. A second elongate trace is formed on the upper portion. A portion of the second elongate trace positioned in the opening formed through the upper surface of the upper portion contacts the first elongate trace through the opening to form an electrical interconnection between the first trace and the second trace.

Abstract: In a computer system having redundant SCSI controllers cards, a SCSI controller interface for receiving multiple interchangeable SCSI controller cards is configured so that the data bus paths between each of the SCSI controller slots and the controller circuitry do not cross.

Abstract: A center bond flip chip device carrier and a method for making and using it are described. The method includes forming a seat with a cut out portion in at least one trace on a substrate and providing an elastomeric material over the substrate. The seat is sized and configured to receive a conductive connecting structure. The elastomeric material has a gap at the seat to allow electrical connection of the conductive connecting structure with a semiconductor die.

Abstract: In a holding and heat dissipation structure for a heat generation part for dissipating heat generated from the heat generation part having lead portions protruded from the main body thereof are soldered at a main substrate, a terminal plate is disposed at a position opposing to the main substrate with a predetermined distance therebetween, and a part housing portion for holding the part is provided at the terminal plate. The part housing portion is concavely formed. Insertion holes for inserting the lead portions protruded from the main body are formed at the part housing portion and the main substrate, respectively. The lead portions are inserted into these insertion holes, and the lead portions and the land portions of the main substrate are fixed to each other by the soldering in a state that the main body is separated from the bottom surface of the part housing portion.

Abstract: A layout structure of electrode lead wires for organic light-emitting diode (OLED) display is provided for saving materials, simplifying fabrication process, and reducing power consumption so as to lower down the required driving voltage. The display comprises a plurality of cathode and anode electrodes and a plurality of electrode lead wires connected to the cathode electrodes and the anode electrodes respectively. The cathode and the anode lead wires made of a multi-layer metallic material having high conductivity and low impedance are laid on the same side of the transparent substrate.

Abstract: A reconfigurable processor module comprising hybrid stacked integrated circuit (“IC”) die elements. In a particular embodiment disclosed herein, a processor module with reconfigurable capability may be constructed by stacking one or more thinned microprocessor, memory and/or field programmable gate array (“FPGA”) die elements and interconnecting the same utilizing contacts that traverse the thickness of the die. The processor module disclosed allows for a significant acceleration in the sharing of data between the microprocessor and the FPGA element while advantageously increasing final assembly yield and concomitantly reducing final assembly cost.

Abstract: A module substrate has a plurality of module data terminal pairs individually provided in association with respective chip data terminals in a plurality of memory chips, and a plurality of module data wirings which respectively connect between the plurality of module data terminal pairs. The plurality of module data wirings are connected to their corresponding chip data terminals and are configured so as to be available as a memory access data bus. In a memory system in which a plurality of memory modules are arranged in parallel, module data wirings of each individual memory modules are connected in serial form, and each individual module data wirings do not constitute branch wirings with respect to a data bus on a motherboard of the memory system. In the memory modules, parallel access for the number of bits corresponding to the width of the memory access data bus is assured.

Abstract: A method for making and repairing connections between first and second circuits, such as flex circuits. An article 10 includes: a flexible dielectric substrate 12 having first and second edges 14/16, and a plurality of conductive circuit traces 18 arranged on or within the substrate, wherein each of the traces extends from proximate the first edge 14 to proximate the second edge 16. Each of the circuit traces 18 includes: a first connection feature 20 disposed proximate the first edge 14; a second connection feature 22 disposed proximate the second edge 16; and at least one third connection feature 24 disposed between the first and second edges 14/16. Each of the first, second, and third connection features 20/22/24 is a plated through hole, a plated blind via, or a mounting pad. This article 10 may be used to connect together the first and second circuits 50/60 using the first and second connection features 20/22, such as by soldering. If either of the two circuits needs to be subsequently detached (e.g.

Abstract: A computer system including a microprocessor and a system memory coupled t provide storage to facilitate execution of computer programs by the microprocessor. An input is coupled to provide input to the microprocessor. A display is coupled to the microprocessor by a video controller and a mass storage is coupled to the microprocessor. A printed circuit board is electrically coupled to the microprocessor. The printed circuit board includes a circuit substrate having two spaced apart major surfaces and a plurality of rows of interconnect assemblies. Each row of interconnect assemblies includes a first and a second interconnect pad on a major surface of the circuit substrate. The first and the second interconnect pads are positioned on a respective reference axis. The first interconnect pad is spaced apart from the second interconnect pad by a first distance. A first and a second conductive via extend through the circuit substrate.

Abstract: In a memory module arranged with the connection terminals located on both sides of the circuit board, the connection terminals for transmitting a common signal to all memory modules conducts with the connection terminals that are directly facing each other on the opposite sides of the circuit board, and the connection terminals for transmitting an intrinsic signal to the respective memory modules conduct with connection terminals that are not directly facing each other through the circuit board.

Abstract: A multilayered wiring board comprising a first stacked structure consisting essentially of a first insulating layer having a first parallel conductor array and a second insulating layer formed thereon, having a second parallel conductor array oriented orthogonal to the first parallel conductor array, the first and second parallel conductor arrays being electrically interconnected by a first through conductor array; and a second stacked structure consisting essentially of a third insulating layer having a third parallel conductor array crossing at an angle of 30 to 60 degrees to the first parallel conductor array and a fourth insulating layer formed on top of the third insulating layer, having a fourth parallel conductor array orthogonal to the third parallel conductor array, the third and fourth parallel conductor arrays being electrically interconnected by a second through conductor array, wherein the second stacked structure is overlaid on the first stacked structure by interposing therebetween an intermedi

Abstract: In a computer system having redundant SCSI controllers cards, a SCSI controller interface for receiving multiple interchangeable SCSI controller cards is configured so that the data bus paths between each of the SCSI controller slots and the controller circuitry do not cross.

Abstract: A power electronics module has a metal substrate, a printed circuit card carried on one of the faces of the substrate, and components, at least some of which are power components, mounted on the card. The card also carries electrical interconnection tracks between the components themselves and with external power supply. Conductive bridges of a shape enabling each of them to extend over a power component mutually interconnect short segments of interconnection tracks, that carry power current.

Abstract: An integrated circuit package includes at least one one-time programmable element, such as a fuse, having a first end and a second end separated by a programmable link. The programmable element is positioned on a surface other than the top surface, e.g., a side surface or the bottom surface of the package substrate to render them less conspicuous to unscrupulous suppliers intent on tampering with the package. The information programmed by the fuses may relate to speed or voltage ratings for a microprocessor.

Abstract: In one embodiment, a dummy via is created in a circuit board. The dummy via is positioned and coupled to a portion of a transmission line. This portion of the transmission line is further coupled to a signal lead of a connector, which creates additional capacitance to lower the impedance of the connector.

Abstract: A circuit board including differential bus traces on or buried within both sides of the board, interconnecting electronic devices such as disk drives, processors, and connectors for external cables. Via fields, which mimic the size and configuration of the device and cable connector fields, are located between each connector on the board. The via fields link bus traces on or within one side of the board with respective bus traces on or within the other side of the board. The via fields may include subtle, unequal undulations in the trace patterns to provide equalization in the lengths of all trace pairs. The via fields and the connector fields both include repetitive conductor order reversals in the trace connections on opposing sides of the board, to reduce crosstalk between channels. The via fields may be oriented parallel with respect to collinearly arranged devices, or orthogonal with respect to devices or connectors which are parallel.

Abstract: A power source (ground) line, which would have been formed with a broad conducting path is divided into multiple fine-line interconnections. A short-circuiting joint is formed to connect between the divided, multiple fine-line interconnections.

Abstract: Provided is a semiconductor memory module capable of decreasing a parasitic capacitance and a parasitic inductance which are incidental to a signal transmission path, thereby reducing a distortion of a signal waveform. In a memory module, four DRAMs are provided on a muttilayer printed circuit board in one line corresponding to a direction of arrangement of external terminals thereof and board terminal groups of the module are provided to make a pair along two long sides of the multilayer printed circuit board. The DRAM has external terminals extended from one of the long sides and external terminals extended from the other long side. Board terminals and board terminals in the board terminal group of the module are connected to the DRAM, and board terminals and board terminals in the board terminal group TGB of the module are connected to the DRAM.

Abstract: A flexible wiring board that can bridge wires and also can prevent production of conductive foreign materials in use, to secure good performance of a magnetic head. The flexible wiring board for connecting therethrough a suspension substrate having mounted thereon a magnetic head of a hard disk drive and a control circuit substrate for actuating the magnetic head includes a short-circuit forming portion for forming a shorting portion for bridging wires to prevent electrostatic destruction of the magnetic head; and a cut for removing the shorting portion. When the flexible wiring board is cut along the cut, the shorting portion can be removed without producing conductive foreign material resulting from the cutting off of the shorting portion.

Abstract: An apparatus for use with data processing systems. The apparatus provides a split metallic conducting plane having a split formed by a substantially-dielectric-filled moat spanning a width of a side of a first metallic conducting part running substantially parallel to a side of a second metallic conducting part, with the moat structured such that the side of the first metallic part has at least two indentations and such that the side of the second metallic part has at least two indentations, and where a metallic trace is located proximate to the split metallic conducting plane.

Abstract: In a semiconductor package which contains an IC element therein and effects the inputting and outputting of a signal to the IC element through a plurality of pads, a group of signals is layout-patterned so as to divided into a plurality of groups such as a group of signals weak against noise, a group of signals liable to discharge noise and a group of signals exchanging a heavy current and so that the groups may be isolated from one another.

Abstract: An electrical interconnection medium is provided having first and second overlying interconnection layers. Each interconnection layer includes parallel conductors, and the conductors of the first and second interconnection layers are oriented orthogonally to each other. The conductors can be interconnected to form at least two electrical planes, with the conductors of the electrical planes being substantially interdigitated on each interconnection layer, portions of each plane appearing on both layers. The interconnection medium advantageously is employed as a multichip module. A method of designing such an MCM includes providing arranged conductive regions in a spaced manner, cutting selected sections to form signal conductor paths, and then filling spaces between like power and ground conductors.

Abstract: An electrical interconnection medium is provided having first and second overlying interconnection layers. Each interconnection layer includes parallel conductors, and the conductors of the first and second interconnection layers are oriented orthogonally to each other. The conductors can be interconnected to form at least two electrical planes, with the conductors of the electrical planes being substantially interdigitated on each interconnection layer, portions of each plane appearing on both layers. The interconnection medium advantageously is employed as a multichip module. A method of designing such an MCM includes providing arranged conductive regions in a spaced manner, cutting selected sections to form signal conductor paths, and then filling spaces between like power and ground conductors.

Abstract: A universal design of a multiple layer printed circuit board incorporates a series of routing vias interconnecting the various layers. The routing vias are connected to conductive traces in the internal trace layers by internal junctions. The internal junctions are located on the via so that internal junctions may be selectively severed by means of a laser or high pressure water cutting system or other fine line cutting tool or mechanism to customize the circuit design for a particular semiconductor device or integrated circuit.

Abstract: The present invention relates generally to a new method and apparatus to enable high yielding double sided and/or multipass screening in the manufacture of multilayer ceramic packages. Also, the present invention enables the screened features to be buried partially or fully with flat surface being available for high yielding post-sinter operations.

Abstract: A method for isolating a pin of a ball grid array (BGA) device mounted on a printed circuit board, and routing the signal carried by the isolated pin to an alternate location. The BGA device pin is isolated by removing the solder ball to expose the device pad. A rework or engineering wire is then soldered to the BGA device pad using a high temperature solder. The rework wire is then routed between the other solder pads to the edge of the BGA device package. The BGA device is then reflowed at a temperature lower than the reflow temperature of the high temperature solder. The rework wire is used to route the signal carried by the isolated BGA pin to an alternate location. The present invention provides for higher process yields than conventional rework processes.

Abstract: A printed circuit board (PCB) includes a first 90.degree. signal line. The first 90.degree. signal line connects a first location on a first layer of the PCB to a second location on a second layer of the PCB. The PCB includes a second 90.degree. signal line. The second 90.degree. signal line is adjacent and equal in length to the first 90.degree. signal line. The second 90.degree. signal line connects a third location on the first layer of the PCB to a fourth location on the second layer of the PCB.

Abstract: When a plurality of hard disks are connected by using a backplane, in order to enable a low-noise installation of the bus and a high-density installation of the hard disk to be simultaneously realized, a signal line of the bus and connectors are installed to the backplane, slots are set to installing regions of the drives, wirings of the signal lines between the connectors are set to, for example, a U-character shape, and a length of signal lines between the connectors is set to be longer than a distance between the connectors adjacent to the bus.

Abstract: A wiring board to be provided between a packaged electronic component having an integrated circuit and a mother board on which the packaged electronic component should be mounted, includes a base made of an insulating material, a first circuit pattern which is provided on a first surface of the base and has terminals connectable to terminals of the packaged electronic component for external connections, and a second circuit pattern which is provided on a second surface of the base opposite to the first surface thereof and has terminals connectable to terminals provided on the mother board.

Abstract: A mounting assembly of an integrated circuit device includes an integrated circuit device having pads on its lower side, through holes formed in a mounting substrate at positions opposed to the pads of the integrated circuit device, and solders for connecting the pads of the integrated circuit device with the through holes. An electrode is provided on the inside wall of each through hole, and the mounting substrate includes therein wirings connected to the electrodes. The solder is filled into the through holes to such an extent that the solder filled in the through holes can be visually checked from the lower side of the substrate.

Abstract: A multilayer circuit substrate with a circuit repairing function which has a circuit substrate having a circuit pattern and repair pattern on the inner layer via an inter-substrate insulation film and having circuit repairing areas for cutting and bonding the circuit on these patterns, a terminal bonding pad for bonding electronic circuit parts mounted on this substrate, and a conductive via hole for bonding said circuit pattern to the terminal bonding pad, wherein at least the circuit repairing area of the repair pattern and at least the circuit repairing area of said circuit pattern which are set on said inner layer are brought close to each other and positioned on the same plane.

Abstract: A microcomputer module 21 and a memory module 31 are mounted on a mounting substrate 42 in such a manner that first outer leads 23 of the microcomputer module 21 and first outer leads 33 of the memory module 31 are connected together in an overlapped manner.

Abstract: An inexpensive high-frequency circuit device and its electronic component which allows two traces or lines to cross on the same surface without affecting other circuits characteristics. At least one of the lines is a high-frequency signal line.

Abstract: When a plurality of hard disks are connected by using a backplane, in order to enable a low-noise installation of the bus and a high-density installation of the hard disk to be simultaneously realized, a signal line of the bus and connectors are installed to the backplane, slots are set to installing regions of the drives, wirings of the signal lines between the connectors are set to, for example, a U-character shape, and a length of signal lines between the connectors is set to be longer than a distance between the connectors adjacent to the bus.

Abstract: A power module with leads extending upwardly. The circuit components and connections of the power module are arranged upon a substrate having interface leads attached thereto extending away from the undersurface of the substrate. The interface leads extend through openings in a form fitting molded case. The case has an open center region to facilitate performance of final assembly steps upon the module and is subsequently covered with a rugged lid and is encapsulated with a suitable potting material. The interior of the module is filled with a gel to provide moisture-proof protection.

Abstract: A technique is provided for correcting miswiring on a chip for test purposes. When an IC chip has been formed during a prototype operation, often I/O wiring is found to be deficient. This deficiency can be corrected by providing an interposer which has pads on one surface corresponding to the pads on the IC chip and pads on the opposite surface of the interposer corresponding to the desired output connections. Vias are formed through the interposer and the miswired connections on the chip surface are wired through the vias to the proper connections for the output of the chip as well as the proper connections on the chip being wired to the proper connections for the output connection on the opposite surface of the interposer.

Abstract: A layered circuit-board designing method and layered circuit-board where circuit-boards to be overlaid are connected at the center or an arbitrary position of each circuit-board. The layered circuit-board includes an upper-layer first circuit-board, a lower-layer third circuit-board, and an intermediate-layer second circuit-board between the first and third circuit-boards. A first connector is mounted on the first circuit-board, a second connector is mounted on the third circuit-board, a third connector is mounted on the top surface of the second circuit-board, while maintaining the positional relation between the third connector and the first connector, and a fourth connector is mounted on the bottom surface of the second circuit-board, while maintaining the positional relation between the fourth connector and the second connector. In addition, through holes are provided at pins of the third and fourth connectors for passing through the front and bottom surfaces of the second circuit-board.

Abstract: A rework configuration is provided for disconnecting defective lithography-formed conductors and/or overlying electrical components from the printed circuit wiring netlist and connecting rework elements at the substituted sites. In particular, defective regions can be severed at spaced first and second target areas upon the upper surface of the PCB and one or more interconnect structures can be coupled therebetween. The interconnect structures allow re-routing of PCB conductors, allow connectivity between the upper and lower surfaces, allow connectivity to power and ground planes, and allow pull-up, pull-down and decoupling connectivity.

Abstract: The invention uses a programmable interconnect substrate having a plurality of conductive and interconnectable vias located on one or both surfaces thereof. A customized pattern of bonding pads is then formed over the one or both surfaces of the substrate which correspond to the terminal footprints of specific surface mounted packages intended to be mounted on the substrate. A generalized pattern of bonding pads may also be formed on the surfaces of the substrate for electrically connecting terminals of bare dice thereto by means of thin wire. All bonding pads are electrically connected to one or more vias by direct electrical contact or by a conductive trace extending from the bonding pad to a nearby via.

Abstract: A method and apparatus providing an automated means for detecting unsoldered thru-hole connector leads is herein disclosed. This means consists of a thru-hole connection pad and a test pad positioned in close proximity to each lead of an electrical component. A thru-hole connection pad is formed about the periphery of each thru-hole. It serves to form a solder pad for securing the lead to the printed circuit board and establishes an electrical connection between the component and reverse sides of the printed circuit board. A test etch easily accessible by an automated testing device is positioned within close proximity of each thru-hole connection pad. As each lead is individually soldered to the printed circuit board, a solder bridge must also be formed across the thru-hole connection pad and the test etch thereby establishing an electrical connection between the lead and the test etch. This electrical connection is used by an automated testing device to detect any unsoldered leads.

Abstract: A method for electrically connecting a surface conductor to an edge conductor on an intersecting side of a non-conductive substrate, includes the steps of forming a through-hole in the substrate, and metallizing the through-hole to form a conductive via. Then, the substrate through the via is cut to form an intersecting side. An electrical connection may be made between a surface conductor through the via to an edge conductor on the intersecting side of the substrate. A preferred embodiment further includes forming an insulating sealing plug in the via, prior to cutting the intersecting side. The above method provides an edge connection without the need to wrap a conductive conduit around the corner of the substrate. Such wrap-around conduits are vulnerable to damage during subsequent handling of the substrate.

Abstract: Disclosed is a parallel processor packaging structure and a method for manufacturing the structure. The individual logic and memory elements are on printed circuit cards. These printed circuit boards and cards are, in turn, mounted on or connected to circuitized flexible substrates extending outwardly from a laminate of the circuitized, flexible substrates. Intercommunication is provided through a switch structure that is implemented in the laminate. The printed circuit cards are mounted on or connected to a plurality of circuitized flexible substrates, with one printed circuit card at each end of the circuitized flexible circuit. The circuitized flexible substrates connect the separate printed circuit boards and cards through the central laminate portion. This laminate portion provides XY plane and Z-axis interconnection for inter-processor, inter-memory, inter-processor/memory element, and processor to memory bussing interconnection, and communication.