Abstract: According to an aspect, a force sensor includes: a plurality of first electrodes that are arranged along a substrate; an elastic body that is in contact with the first electrodes; a second electrode that is in contact with the elastic body, the elastic body being interposed between the second electrode and the first electrodes; and a third electrode that is provided on the substrate side of the second electrode and configured to be electrically coupled to the second electrode. The elastic body includes a conductive particle that electrically couples the first electrodes and the second electrode when force is applied that causes the first electrodes and the second electrode to be approached. The third electrode has a continuous lattice shape that separates at least the first electrodes adjacent in one direction from each other.

Abstract: An integrated circuit package is disclosed. The integrated circuit package includes a first integrated circuit die, a second integrated circuit die, an organic substrate, wherein both the first integrated circuit die and the second integrated circuit die are connected to the organic substrate, a multi-die interconnect bridge (EMIB) embedded within the organic substrate, and a termination resistor associated with a circuit in the first integrated circuit die, wherein the termination resistor is located within the multi-die interconnect bridge embedded within the organic substrate.

Abstract: To mitigate a bending stress in the flexible wiring substrate in a structure, a display panel, to which the flexible wiring substrate connects, is curved along a first direction, and the flexible wiring is bent back to the rear of the display panel. The flexible wiring substrate connects with the display panel at a first region and at a second region; the flexible wiring substrate connects with the wiring substrate at a third region and at a fourth region. The flexible wiring substrate has a narrowest width in the first direction at an intermediate region between the display panel and the wiring substrate. A first wiring group in the flexible wiring substrate connects the first region with the third region or the fourth region, a second wiring group in the flexible wiring substrate connects the second region with another one of the third region or the fourth region.

Abstract: Embodiments include semiconductor packages and a method of forming the semiconductor packages. A semiconductor package includes a package substrate with a top surface, a corner portion, and a plurality of solder balls on the top surface of the package substrate. The semiconductor package also includes a pattern on the corner portion of the package substrate. The pattern may have a width substantially equal to a width of the solder balls. The pattern may also include a continuous line having solder materials. The semiconductor package may include a plurality of conductive pads on the package substrate. The conductive pads may be coupled to the pattern. The pattern may have a z-height that is substantially equal to a z-height of the solder balls, and have one or more outer edges, where the outer edges of the pattern are sidewalls. The sidewalls of the pattern may be substantially vertical or tapered sidewalls.

Abstract: The present invention provides a method for determining hydrogen sulfide (H2S) by headspace single-drop liquid phase microextraction and intelligent device colorimetry, which comprises: taking a silver-gold core-shell triangular nanosheet (Ag@Au TNS) as a nanodetection probe, in combination with an analysis method of headspace single-drop microextraction (HS-SDME), specifically extracting H2S volatilized from a sample to be detected by the nanodetection probe, and detecting H2S in the extracted sample with the help of the photographing function of an intelligent device and a color picking software. Compared with the prior art, the present invention adopts intelligent device colorimetry, with the limit of detection of about 65 nM and the linear range of 0.1-100 ?M, and the established method can be applied to the determination of H2S in actual samples such as egg white, milk and other opaque samples, and has the advantages of few procedures, simple operation, high detection efficiency and the like.

Abstract: Some embodiments relate to a semiconductor structure. The semiconductor structure includes a first substrate including a first plurality of conductive pads that are laterally spaced apart from one another on the first substrate. A first plurality of conductive bumps are disposed on the first plurality of conductive pads, respectively. A multi-tiered solder-resist structure is disposed on the first substrate and arranged between the first plurality of conductive pads. The multi-tiered solder-resist structure has different widths at a different heights over the first substrate and contacts sidewalls of the first plurality of conductive bumps to separate the first plurality of conductive bumps from one another.

Abstract: An apparatus may include a sense resistor comprising a plurality of parallel-coupled resistor elements, a plurality of positive voltage sense points, and a plurality of negative voltage sense points. A first passive combination network may be configured to combine the plurality of positive voltage sense points into a single positive sense terminal and a second passive combination network may be configured to combine the plurality of negative voltage sense points into a single negative sense terminal. The first passive combination network and the second passive combination network may be arranged such that a sense voltage is measurable between the single positive sense terminal and the single negative sense terminal and a dependence of the sense voltage on a variation in current density in the parallel-coupled resistor elements is minimized.

Abstract: A pattern forming method is disclosed. The pattern forming method includes buffing a surface of a product containing aluminum, masking at least a part of the buffed surface with an etching resist, etching a part of the buffed surface not masked by the etching resist, removing the etching resist from the surface, and anodizing the surface from which the etching resist is removed.

Abstract: A flexible conductive paste and a flexible electronic device are provided, which relate to the technical field of new materials. The flexible conductive paste includes: 3% to 7% by weight of a film former; 20% to 50% by weight of a conductive powder; 25% to 45% by weight of a liquid metal microcapsule; 10% to 30% by weight of a solvent; 0.1% to 5% by weight of a curing agent; and 0.5% to 5% by weight of a functional additive. The wall of the liquid metal microcapsule is a coating resin, the core of the liquid metal microcapsule is a liquid metal. The melting point Tm of the liquid metal satisfies Tm?T1. The film former has a molecular weight within a range of 15000 to 30000, and has a glass transition temperature Tg smaller than or equal to T1. T1 is a temperature at which the flexible conductive circuit manufactured by the flexible conductive paste is deformed. The flexible conductive circuit of the present disclosure can have better conductivity and better flexibility simultaneously.

Abstract: To mitigate a bending stress in the flexible wiring substrate in a structure, a display panel, to which the flexible wiring substrate connects, is curved along a first direction, and the flexible wiring is bent back to the rear of the display panel. The flexible wiring substrate connects with the display panel at a first region and at a second region; the flexible wiring substrate connects with the wiring substrate at a third region and at a fourth region. The flexible wiring substrate has a narrowest width in the first direction at an intermediate region between the display panel and the wiring substrate. A first wiring group in the flexible wiring substrate connects the first region with the third region or the fourth region, a second wiring group in the flexible wiring substrate connects the second region with another one of the third region or the fourth region.

Abstract: A three-dimensional (3D) metal object manufacturing apparatus selects operational parameters for operation of the printer to form vias in substrates. The apparatus identifies the bulk metal being melted for ejection and uses this identification data to select the operational parameters. The apparatus identifies the via holes in the substrate and positions an ejector opposite the via holes to eject drops of melted bulk metal toward the via holes to fill the via holes.

Abstract: A ceramic electronic component of the present disclosure includes a component body including a ceramic layer, at least one terminal electrode provided on one main surface of the component body, and an insulating covering layer provided across the ceramic layer and the terminal electrode to cover part, instead of an entire circumference, of a peripheral edge portion of the terminal electrode, wherein when viewed in plan view from one main surface of the component body, the covering layer intersects with the terminal electrode at a non-perpendicular angle at an intersection of the covering layer and the terminal electrode not covered with the covering layer.

Abstract: A component includes a plurality of electrical connections on a process side opposed to a back side of the component. Each electrical connection includes an electrically conductive multi-layer connection post protruding from the process side. A printed structure includes a destination substrate and one or more components. The destination substrate has two or more electrical contacts and each connection post is in contact with, extends into, or extends through an electrical contact of the destination substrate to electrically connect the electrical contacts to the connection posts. The connection posts or electrical contacts are deformed. Two or more connection posts can be electrically connected to a common electrical contact.

Abstract: An integrated circuit device wafer includes a silicon wafer substrate and a back side metallization structure. The back side metallization structure includes a first adhesion layer on the back side of the substrate, a first metal later over the first adhesion layer, a second metal layer over the first metal layer, and a second adhesion layer over the second metal layer. The first includes at least one of: silicon nitride and silicon dioxide. The first metal layer includes titanium. The second metal layer includes nickel. The second adhesion layer includes at least one of: silver, gold, and tin. An indium preform is placed between the second adhesion layer and the lid and the indium preform is reflowed.

Abstract: A printed circuit board module (10) has a printed circuit board (20) with a first side (21), a second side (22) and a contact hole (30). A sleeve-type via (32) is provided in the contact hole 30. An annular ring (35, 36) is associated with the via (32), on at least one side (33, 34). The annular ring (35, 36) is arranged on the first side (21) or on the second side (22) of the printed circuit board (20). The annular ring (35, 36) is electrically connected to the via (32). The annular ring (35, 36) has an annular ring edge (40), at least in sections. The printed circuit board module (10) has a solder resist layer (50). It extends, at least in sections, from outside the annular ring edge (40) over the annular ring edge (40) to an outer region (42) of the annular ring (35, 36). An inner region (44) not covered with the solder resist layer (50), remains on the annular ring (35, 36).

Abstract: Methods of forming connectors and packaged semiconductor devices are disclosed. In some embodiments, a connector is formed by forming a first photoresist layer over an interconnect structure, and patterning the first photoresist layer. The patterned first photoresist layer is used to form a first opening in an interconnect structure. The patterned first photoresist is removed, and a second photoresist layer is formed over the interconnect structure and in the first opening. The second photoresist layer is patterned to form a second opening over the interconnect structure in the first opening. The second opening is narrower than the first opening. At least one metal layer is plated through the patterned second photoresist layer to form the connector.

Abstract: A semiconductor device includes a solder bump overlying and electrically connected to a pad region, and a metal cap layer formed on at least a portion of the solder bump. The metal cap layer has a melting temperature greater than the melting temperature of the solder bump.

Abstract: [Purpose] To provide is a method capable of producing a heat-dissipating unit easily and at low cost. [Solution] The method of producing a heat-dissipating unit 12 includes: inserting pins 17 punched out of a second plate member 22 for pins into a plurality of through-holes 16 formed in a first plate member 20 for a substrate. In the first plate member 20, a plurality of substrate forming portions 25 is provided side by side in the longitudinal direction of the first plate member 20. In the second plate member 22, a plurality of pin punch-out portions 26 is provided side by side in the longitudinal direction of the second plate member 22.

Abstract: This invention provides an electro-optical module with reduced noise in driving voltage. The invention can include a power supply substrate that is arranged separately from the flexible substrate having a driver, so that the noise of the driving voltage supplied from the power supply substrate is reduced.

Abstract: The present invention relates to a circuit substrate arrangement comprising a base layer (2) made from aluminium, a circuit layer (3) made from copper, a dielectric layer (4) arranged between the base layer (2) and the circuit layer (3), an opening (5) passing through the base layer (2), the circuit layer (3) and the dielectric layer (4) and an electrical contact (6) between the base layer (2) and the circuit layer (3), wherein the electrical contact (6) comprises a rivet (7), wherein a frictionally connected joint (8) is formed between the rivet (7) and the base layer (2) and wherein an integrally bonded joint (9) is formed between the rivet (7) and the circuit layer (3).

Abstract: This invention provides an electro-optical module with reduced noise in driving voltage. The invention can include a power supply substrate that is arranged separately from the flexible substrate having a driver, so that the noise of the driving voltage supplied from the power supply substrate is reduced.

Abstract: This invention provides an electro-optical module with reduced noise in driving voltage. The invention can include a power supply substrate that is arranged separately from the flexible substrate having a driver, so that the noise of the driving voltage supplied from the power supply substrate is reduced.

Abstract: An integrated circuit multichip stacked packaging structure and method, including: first pins, provided at bottom surface of first chip; second pins, provided at top surface of second chip; circuit layers, provided at top surface of substrate, and/or circuit layers, provided at bottom surface of substrate, and/or circuit layers, provided within substrate; first chip, provided at top surface of substrate; second chip, provided at top surface of first chip; first pin is electrically connected at least to one of circuit layers provided with circuit pins, substrate is provided with connecting through hole, which is docked with circuit pin, first opening thereof is docked with first pin, second opening thereof is operating window, electrically-conductive layer is provided within connecting through hole, and electrically connects first pin to circuit pin; second pin is electrically connected at least to one of circuit layers; second pin is electrically connected to circuit layer via electrically-conductive layer.

Abstract: Apparatuses and methods for providing thermal pathways from a substrate to a thermal bonding pad. The thermal pathways may be metal extensions of the thermal bonding pad that are disposed in channels formed in a backside passivation layer underneath the thermal bonding pad, and may be in direct contact with an underlying substrate. The thermal pathways may provide improved thermal dissipation from the substrate.

Abstract: An embodiment ladder bump structure includes an under bump metallurgy (UBM) feature supported by a substrate, a copper pillar mounted on the UBM feature, the copper pillar having a tapering curved profile, which has a larger bottom critical dimension (CD) than a top critical dimension (CD) in an embodiment, a metal cap mounted on the copper pillar, and a solder feature mounted on the metal cap.

Abstract: A wiring substrate includes a resin substrate in which first and second through holes are formed, a metallic foil on one surface of the resin substrate coating the through holes and separated into first and second side metallic foils by a border, a first connecting portion formed by a plating film inside the first through hole, a second connecting portion formed by a plating film inside the second through hole, a first slit facing the border and penetrating through the metallic foil and the first connecting portion, a second slit facing the border and penetrating through the metallic foil and the second connecting portion, first and second plating layers on front surfaces of the first and second side metallic foils, bottom surfaces of the first and second connecting portions, and side surfaces inside the first and second slits of the first and second side metallic foils.

Abstract: A display device includes: a display substrate in which a display for displaying an image is formed; an encapsulation substrate, which is assembled on the display substrate and has a first surface facing the display substrate and a second surface opposite to the first surface; and a circuit substrate for transferring an electrical signal to the display, where a plurality of pads, which are electrically connected to the display and connected to the circuit substrate, are formed on the first surface of the encapsulation substrate, and at least one connector is formed on surfaces of the display and the encapsulation substrate which face each other, the connector configured to provide a connection path between the display and the circuit board by being adhesively pressed in a vertical direction.

Abstract: A method of forming a semiconductor package includes providing a substrate having one or more conductive elements disposed therein. Each conductive element extends from a first surface of the substrate toward a second surface of the substrate extending beyond the second surface. The second surface comprises one or more substrate regions not occupied by a conductive element. A first die is attached within a substrate region, and the first die is coupled to at least one of the conductive elements. The first die may be coupled to at least one of the conductive elements by a wire bond connection. Alternatively, an RDL is formed over the second surface, and the first die is coupled to at least one conductive element through the RDL. A second die may be attached to an outer surface of the RDL, and the second die is electrically coupled to the first die through the RDL.

Abstract: A package includes a device die having a substrate. A molding compound contacts a sidewall of the substrate. A metal pad is over the substrate. A passivation layer has a portion covering an edge portion of the metal pad. A metal pillar is over and contacting the metal pad. A dielectric layer is over the passivation layer. A package material formed of a molding compound or a polymer is over the dielectric layer. The dielectric layer includes a bottom portion between the passivation layer and the package material, and a sidewall portion between a sidewall of the metal pillar and a sidewall of the package material. A polymer layer is over the package material, the molding compound, and the metal pillar. A post-passivation interconnect (PPI) extends into the polymer layer. A solder ball is over the PPI, and is electrically coupled to the metal pad through the PPI.

Abstract: An assembly including a substrate, a metal wiring layer on the substrate, the metal wiring layer having an opening therein, a thermosetting resin layer on at least a portion of the substrate overlapping the opening of the metal wiring layer, and a device on the resin layer, the device positioned over the opening of the metal wiring layer and bonded to the substrate via the resin layer.

Abstract: A wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating layer, wherein parts of the first conductive vias are electrically connected with the first chip; forming a conductive pattern layer on the surface of the first insulating layer wherein the conductive pattern layer is electrically connected with the first conductive vias; forming a plurality of through holes penetrating the wafer; filling a second insulating layer in the through holes; and forming a plurality of second conductive vias in the second insulating layer, wherein the second conductive vias are electrically connected with the first conductive vias.

Abstract: An electronic device includes: a first electronic component; first members that are provided on a first surface of the first electronic component and that include outside surfaces configured to face diagonally upward with respect to the first surface; a second electronic component provided above the first surface; second members that are provided corresponding to the first members on a second surface of the second electronic component which faces the first surface and that include inside surfaces configured to face diagonally downward with respect to the second surface and configured to face the outside surfaces; and solder that is provided between the first surface and the second surface and that electrically connects the first electronic component and the second electronic component.

Abstract: A micro-wire electrode includes a substrate and an anisotropically conductive electrode extending in a length direction formed over the substrate. The electrode includes a plurality of electrically connected micro-wires formed in a micro-pattern over the substrate. The micro-pattern includes a plurality of substantially parallel and straight micro-wires extending substantially in the length direction and a plurality of angled micro-wires formed at a non-orthogonal angle to the straight micro-wires electrically connecting the straight micro-wires so that the anisotropically conductive electrode has a greater electrical conductivity in the length direction than in another conductive electrode direction.

Abstract: An electronic device may contain components such as flexible printed circuits and rigid printed circuits. Electrical contact pads on a flexible printed circuit may be coupled electrical contact pads on a rigid printed circuit using a coupling member. The coupling member may be configured to electrically couple contact pads on a top surface of the flexible circuit to contact pads on a top surface of the rigid circuit. The coupling member may be configured to bear against a top surface of the flexible circuit so that pads on a bottom surface of the flexible circuit rest against pads on a top surface of the rigid circuit. The coupling member may bear against the top surface of the flexible circuit. The coupling member may include protrusions that extend into openings in the rigid printed circuit. The protrusions may be engaged with engagement members in the openings.

Abstract: A device includes a wiring board, an element mounted on the wiring board, a spacer member intervening between the wiring board and the element to form a space therebetween, and an encapsulation body filling the space and encapsulating the element on the wiring board.

Abstract: A circuit board includes a dielectric layer and a signal routing layer on the dielectric layer. The signal routing layer includes chip traces, connector traces, and signal traces connected with the chip traces and the connector traces. The dielectric layer includes a signal trace area for arraying the signal traces, a chip trace area for arraying the chip traces, and a connector trace area for arraying the connector traces. The dielectric coefficient of the signal trace area is smaller than the dielectric coefficient of the chip trace area and greater than the dielectric coefficient of the connector trace area.

Abstract: A semiconductor package substrate suitable for supporting a damage-sensitive device, including a substrate core having a first and opposite surface; at least one pair of metal layers covering the first and opposite surfaces of the package substrate core, which define first and opposite metal layer groups, at least one of said layer groups including at least one metal support zone; one pair of solder mask layers covering the outermost metal layers of the at least one pair of metal layers; and a plurality of routing lines; wherein the at least one metal support zone is formed so that it lies beneath at least one side of the base of the damage-sensitive device and so as to occupy a substantial portion of the area beneath the damage-sensitive device which is free of said routing lines; a method for the production of such substrate is also described.

Abstract: A printed wiring board includes an outermost interlayer resin insulation layer, n outermost conductive layer formed on the outermost interlayer resin insulation layer and including multiple alignment marks, a connection wiring structure connecting the alignment marks, and a solder-resist layer formed on the outermost interlayer resin insulation layer and the outermost conductive layer. The solder-resist layer has openings exposing the alignment marks, respectively, and each of the alignment marks has an electroless plated film formed on each of the alignment marks.

Abstract: A substrate includes: a base; and a plurality of bonding terminals arranged on at least one surface of the base, wherein the plurality of bonding terminals include a first bonding terminal and a second bonding terminal, the first bonding terminal and the second bonding terminal include, in plan view of the base, a circle contacting portion extending along the circumference of a circle tangent to the first bonding terminal and the second bonding terminal, all of the plurality of bonding terminals are arranged so as not to protrude from an area including the circle and the inside thereof, and the circle contacting portion includes at least a first circle contacting portion disposed in the first bonding terminal and a second circle contacting portion disposed in the second bonding terminal.

Abstract: A method for manufacturing a multi-piece board having a frame section and a multiple piece sections connected to the frame section includes forming a frame section from a manufacturing panel for the frame section, sorting out multiple acceptable piece sections by inspecting quality of piece sections, forming notch portions in the frame section and the acceptable piece sections such that the notch portions allow the acceptable piece sections to be arranged with respect to the frame section, provisionally fixing the piece sections and the frame section in respective positions, injecting an adhesive agent into cavities formed by the notch portions when the frame section and the piece sections are provisionally fixed to each other, and joining the acceptable piece sections with the frame section by curing the adhesive agent injected into the cavities.

Abstract: An apparatus including a first printed wiring board section and a second printed wiring board section. The first printed wiring board section includes a first dielectric material layer. The first dielectric material layer has a first dissipation factor. The second printed wiring board section is directly attached with the first printed wiring board section to form a unitary printed wiring board structure. The second printed wiring board section includes a second dielectric material layer and an antenna on the second dielectric material layer. The second dielectric material layer has a different second dissipation factor.

Abstract: Embodiments relate to current sensors and methods. In an embodiment, a current sensor comprises a conductor portion having a first portion and a second portion; at least three slots formed in the conductor portion between the first and second portions, each of the at least three slots having a length and at least one tip portion; at least two bridge portions each having a width separating two of the at least three slots and a length coupling the first and second portions; a first contact region disposed relative to the first portion and a second contact region disposed relative to the second portion; and at least one pair of magnetic sensor elements, a first pair of magnetic sensor elements arranged relative to and spaced apart from a first of the at least two bridge portions.

Abstract: A first step of the method for assembling a wire element with an electronic chip comprises arranging the wire element in a groove of the chip delineated by a first element and a second element, joined by a link element comprising a plastically deformable material, and a second step then comprises clamping the first and second elements to deform the link element until the wire element is secured in the groove.

Abstract: A method for producing an arrangement of optoelectronic components (10) is specified, comprising the following steps: producing at least two fixing regions (2) on a first connection carrier (1); introducing solder material (3) into the fixing regions (2); applying a second connection carrier (4) to the fixing regions (2); and soldering the second connection carrier (4) onto the first connection carrier (1) with the solder material (3) in the fixing regions (2).

Abstract: A package structure comprises a substrate, a plurality of electronic components configured and structured on the substrate, a plurality of metal resilient units electrically connected to the substrate, and an encapsulation body encapsulating the plurality of electronic components and the plurality of resilient units together with the substrate. Part of each of the plurality of metal resilient units away from the substrate is exposed out of an exterior surface of the encapsulation body.

Abstract: Tamper secure circuitry including a first printed circuit board having mounted thereon circuit components and a slotted anti-tamper grid containing printed circuit board mounted onto the first printed circuit board defining at least one slot and arranged to overlie at least some of the circuit components, which are located in a volume defined by the at least one slot and the first printed circuit board.

Abstract: A high quality component-incorporated substrate achieves a sufficient connection between an in-plane electrode and an interlayer connection conductor at low cost. A method of forming a hole for an interlayer connection conductor of a resin substrate includes a step of forming an in-plane electrode in a core substrate, a step of forming a light reflective conductor for reflecting a laser beam applied on the in-plane electrode in a later step, a step of forming a resin layer so as to cover the core substrate, the in-plane electrode and the light reflective conductor, and a step of forming a hole for the interlayer connection conductor by removing the resin layer on the light reflective conductor through the use of a laser beam.

Abstract: An electronic device is disclosed for coupling to a target platform, which includes a multitude of pad contacts. The electronic device includes a substrate, a multitude of pad contacts on the substrate, and a multitude of contact regions in one of the of pad contacts on the substrate. Each of the multitude of pad contacts on the substrate electrically couples to a corresponding one of the multitude of pad contacts on the target platform when the substrate and the target platform are assembled. The multitude of contact regions corresponds to one of the multitude of pad contacts on the target platform when the substrate and the target platform are assembled.

Abstract: This publication discloses an electronics module and a method for manufacturing it. The electronic module includes at least one first embedded component (6), the contact terminals (7) of which face essentially towards the first surface of the insulating-material layer (1) and which is connected electrically by its contact terminals (7) to the conductor structures contained in the electronic module. According to the invention, a second embedded component (6?), the contact terminals (7?) of which face essentially towards the second surface of the insulating-material layer and which is connected electrically by its contact terminals (7?) to the conductor structures contained in the electronic module, is attached by means of glue or two-sided tape to the first component (6), and the contact terminals (7, 7?) are connected to the conductor structures with the aid of a conductive material, which is arranged in the insulating-material layer in holes (17) at the locations of the contact terminals (7, 7?).

Abstract: On a printed circuit or substrate board (10) designed to receive electronic components and having conductive tracks (12) printed on said board, one or more conductive bars (18) are provided that are mounted one after another between conductive link surfaces (140, 142, 144), the conductive bars (18) being electrically interconnected during a subsequent soldering process that is either a wave soldering process or a soldering process in a reflow oven.