With Specific Connection Material Patents (Class 361/779)
  • Patent number: 10769981
    Abstract: This invention provides an electro-optical module with reduced noise in driving voltage. The invention can include a power supply substrate that is arranged separately from the flexible substrate having a driver, so that the noise of the driving voltage supplied from the power supply substrate is reduced.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: September 8, 2020
    Assignee: 138 EAST LCD ADVANCEMENTS LIMITED
    Inventor: Tadashi Yamada
  • Patent number: 10643521
    Abstract: This invention provides an electro-optical module with reduced noise in driving voltage. The invention can include a power supply substrate that is arranged separately from the flexible substrate having a driver, so that the noise of the driving voltage supplied from the power supply substrate is reduced.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: May 5, 2020
    Assignee: 138 EAST LCD ADVANCEMENTS LIMITED
    Inventor: Tadashi Yamada
  • Patent number: 10615151
    Abstract: An integrated circuit multichip stacked packaging structure and method, including: first pins, provided at bottom surface of first chip; second pins, provided at top surface of second chip; circuit layers, provided at top surface of substrate, and/or circuit layers, provided at bottom surface of substrate, and/or circuit layers, provided within substrate; first chip, provided at top surface of substrate; second chip, provided at top surface of first chip; first pin is electrically connected at least to one of circuit layers provided with circuit pins, substrate is provided with connecting through hole, which is docked with circuit pin, first opening thereof is docked with first pin, second opening thereof is operating window, electrically-conductive layer is provided within connecting through hole, and electrically connects first pin to circuit pin; second pin is electrically connected at least to one of circuit layers; second pin is electrically connected to circuit layer via electrically-conductive layer.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: April 7, 2020
    Assignee: SHENZHEN XIUYUAN ELECTRONIC TECHNOLOGY CO., LTD
    Inventors: Chuan Hu, Junjun Liu, Yuejin Guo, Edward Rudolph Prack
  • Patent number: 10580746
    Abstract: Apparatuses and methods for providing thermal pathways from a substrate to a thermal bonding pad. The thermal pathways may be metal extensions of the thermal bonding pad that are disposed in channels formed in a backside passivation layer underneath the thermal bonding pad, and may be in direct contact with an underlying substrate. The thermal pathways may provide improved thermal dissipation from the substrate.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: March 3, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Jaspreet S. Gandhi, James M. Derderian, Sameer S. Vadhavkar, Jian Li
  • Patent number: 10008459
    Abstract: An embodiment ladder bump structure includes an under bump metallurgy (UBM) feature supported by a substrate, a copper pillar mounted on the UBM feature, the copper pillar having a tapering curved profile, which has a larger bottom critical dimension (CD) than a top critical dimension (CD) in an embodiment, a metal cap mounted on the copper pillar, and a solder feature mounted on the metal cap.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: June 26, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Pei-Chun Tsai, Yu-Jen Tseng, Tin-Hao Kuo, Chen-Shien Chen
  • Patent number: 9615461
    Abstract: A wiring substrate includes a resin substrate in which first and second through holes are formed, a metallic foil on one surface of the resin substrate coating the through holes and separated into first and second side metallic foils by a border, a first connecting portion formed by a plating film inside the first through hole, a second connecting portion formed by a plating film inside the second through hole, a first slit facing the border and penetrating through the metallic foil and the first connecting portion, a second slit facing the border and penetrating through the metallic foil and the second connecting portion, first and second plating layers on front surfaces of the first and second side metallic foils, bottom surfaces of the first and second connecting portions, and side surfaces inside the first and second slits of the first and second side metallic foils.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: April 4, 2017
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Atsushi Nakamura, Tsukasa Nakanishi, Takayuki Matsumoto
  • Patent number: 9370116
    Abstract: A display device includes: a display substrate in which a display for displaying an image is formed; an encapsulation substrate, which is assembled on the display substrate and has a first surface facing the display substrate and a second surface opposite to the first surface; and a circuit substrate for transferring an electrical signal to the display, where a plurality of pads, which are electrically connected to the display and connected to the circuit substrate, are formed on the first surface of the encapsulation substrate, and at least one connector is formed on surfaces of the display and the encapsulation substrate which face each other, the connector configured to provide a connection path between the display and the circuit board by being adhesively pressed in a vertical direction.
    Type: Grant
    Filed: May 16, 2013
    Date of Patent: June 14, 2016
    Assignee: Samsung Display Co., Ltd.
    Inventor: Jae-Uk Jo
  • Patent number: 9257396
    Abstract: A method of forming a semiconductor package includes providing a substrate having one or more conductive elements disposed therein. Each conductive element extends from a first surface of the substrate toward a second surface of the substrate extending beyond the second surface. The second surface comprises one or more substrate regions not occupied by a conductive element. A first die is attached within a substrate region, and the first die is coupled to at least one of the conductive elements. The first die may be coupled to at least one of the conductive elements by a wire bond connection. Alternatively, an RDL is formed over the second surface, and the first die is coupled to at least one conductive element through the RDL. A second die may be attached to an outer surface of the RDL, and the second die is electrically coupled to the first die through the RDL.
    Type: Grant
    Filed: May 22, 2014
    Date of Patent: February 9, 2016
    Assignee: Invensas Corporation
    Inventor: Cyprian Emeka Uzoh
  • Patent number: 9230902
    Abstract: A package includes a device die having a substrate. A molding compound contacts a sidewall of the substrate. A metal pad is over the substrate. A passivation layer has a portion covering an edge portion of the metal pad. A metal pillar is over and contacting the metal pad. A dielectric layer is over the passivation layer. A package material formed of a molding compound or a polymer is over the dielectric layer. The dielectric layer includes a bottom portion between the passivation layer and the package material, and a sidewall portion between a sidewall of the metal pillar and a sidewall of the package material. A polymer layer is over the package material, the molding compound, and the metal pillar. A post-passivation interconnect (PPI) extends into the polymer layer. A solder ball is over the PPI, and is electrically coupled to the metal pad through the PPI.
    Type: Grant
    Filed: July 31, 2014
    Date of Patent: January 5, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Jing-Cheng Lin, Nai-Wei Liu, Jui-Pin Hung, Shin-Puu Jeng
  • Patent number: 9119332
    Abstract: An assembly including a substrate, a metal wiring layer on the substrate, the metal wiring layer having an opening therein, a thermosetting resin layer on at least a portion of the substrate overlapping the opening of the metal wiring layer, and a device on the resin layer, the device positioned over the opening of the metal wiring layer and bonded to the substrate via the resin layer.
    Type: Grant
    Filed: April 11, 2011
    Date of Patent: August 25, 2015
    Assignee: SONY CORPORATION
    Inventor: Katsuhiro Tomoda
  • Patent number: 9059181
    Abstract: A wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating layer, wherein parts of the first conductive vias are electrically connected with the first chip; forming a conductive pattern layer on the surface of the first insulating layer wherein the conductive pattern layer is electrically connected with the first conductive vias; forming a plurality of through holes penetrating the wafer; filling a second insulating layer in the through holes; and forming a plurality of second conductive vias in the second insulating layer, wherein the second conductive vias are electrically connected with the first conductive vias.
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: June 16, 2015
    Assignee: Invensas Corporation
    Inventors: Shou-Lung Chen, Ching-Wen Hsaio, Yu-Hua Chen, Jeng-Dar Ko, Chih-Ming Tzeng, Jyh-Rong Lin, Shan-Pu Yu
  • Publication number: 20150049450
    Abstract: An electronic device includes: a first electronic component; first members that are provided on a first surface of the first electronic component and that include outside surfaces configured to face diagonally upward with respect to the first surface; a second electronic component provided above the first surface; second members that are provided corresponding to the first members on a second surface of the second electronic component which faces the first surface and that include inside surfaces configured to face diagonally downward with respect to the second surface and configured to face the outside surfaces; and solder that is provided between the first surface and the second surface and that electrically connects the first electronic component and the second electronic component.
    Type: Application
    Filed: August 8, 2014
    Publication date: February 19, 2015
    Applicant: FUJITSU LIMITED
    Inventors: Keishiro Okamoto, Seiki Sakuyama
  • Patent number: 8952263
    Abstract: A micro-wire electrode includes a substrate and an anisotropically conductive electrode extending in a length direction formed over the substrate. The electrode includes a plurality of electrically connected micro-wires formed in a micro-pattern over the substrate. The micro-pattern includes a plurality of substantially parallel and straight micro-wires extending substantially in the length direction and a plurality of angled micro-wires formed at a non-orthogonal angle to the straight micro-wires electrically connecting the straight micro-wires so that the anisotropically conductive electrode has a greater electrical conductivity in the length direction than in another conductive electrode direction.
    Type: Grant
    Filed: August 10, 2012
    Date of Patent: February 10, 2015
    Assignee: Eastman Kodak Company
    Inventor: Ronald Steven Cok
  • Patent number: 8923003
    Abstract: An electronic device may contain components such as flexible printed circuits and rigid printed circuits. Electrical contact pads on a flexible printed circuit may be coupled electrical contact pads on a rigid printed circuit using a coupling member. The coupling member may be configured to electrically couple contact pads on a top surface of the flexible circuit to contact pads on a top surface of the rigid circuit. The coupling member may be configured to bear against a top surface of the flexible circuit so that pads on a bottom surface of the flexible circuit rest against pads on a top surface of the rigid circuit. The coupling member may bear against the top surface of the flexible circuit. The coupling member may include protrusions that extend into openings in the rigid printed circuit. The protrusions may be engaged with engagement members in the openings.
    Type: Grant
    Filed: February 6, 2012
    Date of Patent: December 30, 2014
    Assignee: Apple Inc.
    Inventors: Alexander D. Schlaupitz, Joshua G. Wurzel
  • Patent number: 8873247
    Abstract: A device includes a wiring board, an element mounted on the wiring board, a spacer member intervening between the wiring board and the element to form a space therebetween, and an encapsulation body filling the space and encapsulating the element on the wiring board.
    Type: Grant
    Filed: July 12, 2011
    Date of Patent: October 28, 2014
    Assignee: PS4 Luxco S.A.R.L.
    Inventor: Koji Hosokawa
  • Patent number: 8859910
    Abstract: A circuit board includes a dielectric layer and a signal routing layer on the dielectric layer. The signal routing layer includes chip traces, connector traces, and signal traces connected with the chip traces and the connector traces. The dielectric layer includes a signal trace area for arraying the signal traces, a chip trace area for arraying the chip traces, and a connector trace area for arraying the connector traces. The dielectric coefficient of the signal trace area is smaller than the dielectric coefficient of the chip trace area and greater than the dielectric coefficient of the connector trace area.
    Type: Grant
    Filed: February 1, 2013
    Date of Patent: October 14, 2014
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventor: Kai-Wen Wu
  • Patent number: 8854830
    Abstract: A semiconductor package substrate suitable for supporting a damage-sensitive device, including a substrate core having a first and opposite surface; at least one pair of metal layers covering the first and opposite surfaces of the package substrate core, which define first and opposite metal layer groups, at least one of said layer groups including at least one metal support zone; one pair of solder mask layers covering the outermost metal layers of the at least one pair of metal layers; and a plurality of routing lines; wherein the at least one metal support zone is formed so that it lies beneath at least one side of the base of the damage-sensitive device and so as to occupy a substantial portion of the area beneath the damage-sensitive device which is free of said routing lines; a method for the production of such substrate is also described.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: October 7, 2014
    Assignee: STMicroelectronics S.r.l.
    Inventors: Federico Giovanni Ziglioli, Giovanni Graziosi, Mario Francesco Cortese
  • Patent number: 8847078
    Abstract: A printed wiring board includes an outermost interlayer resin insulation layer, n outermost conductive layer formed on the outermost interlayer resin insulation layer and including multiple alignment marks, a connection wiring structure connecting the alignment marks, and a solder-resist layer formed on the outermost interlayer resin insulation layer and the outermost conductive layer. The solder-resist layer has openings exposing the alignment marks, respectively, and each of the alignment marks has an electroless plated film formed on each of the alignment marks.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: September 30, 2014
    Assignee: Ibiden Co., Ltd.
    Inventors: Ryo Matsuno, Koichi Kondo, Satoru Kose
  • Patent number: 8797760
    Abstract: A substrate includes: a base; and a plurality of bonding terminals arranged on at least one surface of the base, wherein the plurality of bonding terminals include a first bonding terminal and a second bonding terminal, the first bonding terminal and the second bonding terminal include, in plan view of the base, a circle contacting portion extending along the circumference of a circle tangent to the first bonding terminal and the second bonding terminal, all of the plurality of bonding terminals are arranged so as not to protrude from an area including the circle and the inside thereof, and the circle contacting portion includes at least a first circle contacting portion disposed in the first bonding terminal and a second circle contacting portion disposed in the second bonding terminal.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: August 5, 2014
    Assignee: Seiko Epson Corporation
    Inventor: Kenji Sato
  • Patent number: 8741411
    Abstract: A method for manufacturing a multi-piece board having a frame section and a multiple piece sections connected to the frame section includes forming a frame section from a manufacturing panel for the frame section, sorting out multiple acceptable piece sections by inspecting quality of piece sections, forming notch portions in the frame section and the acceptable piece sections such that the notch portions allow the acceptable piece sections to be arranged with respect to the frame section, provisionally fixing the piece sections and the frame section in respective positions, injecting an adhesive agent into cavities formed by the notch portions when the frame section and the piece sections are provisionally fixed to each other, and joining the acceptable piece sections with the frame section by curing the adhesive agent injected into the cavities.
    Type: Grant
    Filed: January 29, 2010
    Date of Patent: June 3, 2014
    Assignee: Ibiden Co., Ltd.
    Inventor: Takahiro Yada
  • Patent number: 8716603
    Abstract: An apparatus including a first printed wiring board section and a second printed wiring board section. The first printed wiring board section includes a first dielectric material layer. The first dielectric material layer has a first dissipation factor. The second printed wiring board section is directly attached with the first printed wiring board section to form a unitary printed wiring board structure. The second printed wiring board section includes a second dielectric material layer and an antenna on the second dielectric material layer. The second dielectric material layer has a different second dissipation factor.
    Type: Grant
    Filed: November 24, 2010
    Date of Patent: May 6, 2014
    Assignee: Nokia Corporation
    Inventors: Ian Sakari Niemi, Ilkka Johannes Kartio, Kimmo Markus Perala, Kari Viljo Jalmari Virtanen, Hannu Vaino Kalevi Ventomaki
  • Patent number: 8717016
    Abstract: Embodiments relate to current sensors and methods. In an embodiment, a current sensor comprises a conductor portion having a first portion and a second portion; at least three slots formed in the conductor portion between the first and second portions, each of the at least three slots having a length and at least one tip portion; at least two bridge portions each having a width separating two of the at least three slots and a length coupling the first and second portions; a first contact region disposed relative to the first portion and a second contact region disposed relative to the second portion; and at least one pair of magnetic sensor elements, a first pair of magnetic sensor elements arranged relative to and spaced apart from a first of the at least two bridge portions.
    Type: Grant
    Filed: February 24, 2010
    Date of Patent: May 6, 2014
    Assignee: Infineon Technologies AG
    Inventors: Udo Ausserlechner, Mario Motz
  • Patent number: 8654540
    Abstract: A first step of the method for assembling a wire element with an electronic chip comprises arranging the wire element in a groove of the chip delineated by a first element and a second element, joined by a link element comprising a plastically deformable material, and a second step then comprises clamping the first and second elements to deform the link element until the wire element is secured in the groove.
    Type: Grant
    Filed: December 23, 2010
    Date of Patent: February 18, 2014
    Assignee: Commisariat a l'Energie Atomique et aux Energies Alternatives
    Inventors: Jean Brun, Dominique Vicard
  • Patent number: 8638565
    Abstract: A method for producing an arrangement of optoelectronic components (10) is specified, comprising the following steps: producing at least two fixing regions (2) on a first connection carrier (1); introducing solder material (3) into the fixing regions (2); applying a second connection carrier (4) to the fixing regions (2); and soldering the second connection carrier (4) onto the first connection carrier (1) with the solder material (3) in the fixing regions (2).
    Type: Grant
    Filed: September 21, 2007
    Date of Patent: January 28, 2014
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Rainer Sewald, Markus Kirsch
  • Patent number: 8625297
    Abstract: A package structure comprises a substrate, a plurality of electronic components configured and structured on the substrate, a plurality of metal resilient units electrically connected to the substrate, and an encapsulation body encapsulating the plurality of electronic components and the plurality of resilient units together with the substrate. Part of each of the plurality of metal resilient units away from the substrate is exposed out of an exterior surface of the encapsulation body.
    Type: Grant
    Filed: August 10, 2011
    Date of Patent: January 7, 2014
    Assignee: Ambit Microsystems (Zhongshan) Ltd.
    Inventor: Jun-Yi Xiao
  • Patent number: 8593824
    Abstract: Tamper secure circuitry including a first printed circuit board having mounted thereon circuit components and a slotted anti-tamper grid containing printed circuit board mounted onto the first printed circuit board defining at least one slot and arranged to overlie at least some of the circuit components, which are located in a volume defined by the at least one slot and the first printed circuit board.
    Type: Grant
    Filed: October 27, 2010
    Date of Patent: November 26, 2013
    Assignee: Verifone, Inc.
    Inventor: Ehud Kirmayer
  • Patent number: 8570763
    Abstract: A high quality component-incorporated substrate achieves a sufficient connection between an in-plane electrode and an interlayer connection conductor at low cost. A method of forming a hole for an interlayer connection conductor of a resin substrate includes a step of forming an in-plane electrode in a core substrate, a step of forming a light reflective conductor for reflecting a laser beam applied on the in-plane electrode in a later step, a step of forming a resin layer so as to cover the core substrate, the in-plane electrode and the light reflective conductor, and a step of forming a hole for the interlayer connection conductor by removing the resin layer on the light reflective conductor through the use of a laser beam.
    Type: Grant
    Filed: December 28, 2009
    Date of Patent: October 29, 2013
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Yasuyuki Sekimoto
  • Patent number: 8547701
    Abstract: This publication discloses an electronics module and a method for manufacturing it. The electronic module includes at least one first embedded component (6), the contact terminals (7) of which face essentially towards the first surface of the insulating-material layer (1) and which is connected electrically by its contact terminals (7) to the conductor structures contained in the electronic module. According to the invention, a second embedded component (6?), the contact terminals (7?) of which face essentially towards the second surface of the insulating-material layer and which is connected electrically by its contact terminals (7?) to the conductor structures contained in the electronic module, is attached by means of glue or two-sided tape to the first component (6), and the contact terminals (7, 7?) are connected to the conductor structures with the aid of a conductive material, which is arranged in the insulating-material layer in holes (17) at the locations of the contact terminals (7, 7?).
    Type: Grant
    Filed: November 24, 2005
    Date of Patent: October 1, 2013
    Assignee: Imbera Electronics Oy
    Inventors: Risto Tuominen, Antti Iihola
  • Patent number: 8547707
    Abstract: An electronic device is disclosed for coupling to a target platform, which includes a multitude of pad contacts. The electronic device includes a substrate, a multitude of pad contacts on the substrate, and a multitude of contact regions in one of the of pad contacts on the substrate. Each of the multitude of pad contacts on the substrate electrically couples to a corresponding one of the multitude of pad contacts on the target platform when the substrate and the target platform are assembled. The multitude of contact regions corresponds to one of the multitude of pad contacts on the target platform when the substrate and the target platform are assembled.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: October 1, 2013
    Assignee: Wintec Industries, Inc.
    Inventor: Kong-Chen Chen
  • Patent number: 8525043
    Abstract: On a printed circuit or substrate board (10) designed to receive electronic components and having conductive tracks (12) printed on said board, one or more conductive bars (18) are provided that are mounted one after another between conductive link surfaces (140, 142, 144), the conductive bars (18) being electrically interconnected during a subsequent soldering process that is either a wave soldering process or a soldering process in a reflow oven.
    Type: Grant
    Filed: November 13, 2007
    Date of Patent: September 3, 2013
    Assignee: AEG Power Solutions B.V., Dutch Company
    Inventor: Christian Delay
  • Patent number: 8493746
    Abstract: In one embodiment of the present invention, inert nano-sized particles having dimensions from 1 nm to 1,000 nm are added into a solder ball. The inert nano-sized particles may comprise metal oxides, metal nitrides, metal carbides, metal borides, etc. The inert nano-sized particles may be a single compound, or may be a metallic material having a coating of a different material. In another embodiment of the present invention, a small quantity of at least one elemental metal that forms stable high melting intermetallic compound with tin is added to a solder ball. The added at least one elemental metal forms precipitates of intermetallic compounds with tin, which are dispersed as fine particles in the solder.
    Type: Grant
    Filed: February 12, 2010
    Date of Patent: July 23, 2013
    Assignee: International Business Machines Corporation
    Inventors: Charles L. Arvin, Alexandre Blander, Peter J. Brofman, Donald W. Henderson, Gareth G. Hougham, Hsichang Liu, Eric D. Perfecto, Srinivasa S. N. Reddy, Krystyna W. Semkow, Kamalesh K. Srivastava, Brian R. Sundlof, Julien Sylvestre, Renee L. Weisman
  • Patent number: 8450621
    Abstract: A process for fabricating a wiring board is provided. In the process, a wiring carrying substrate including a carry substrate and a wiring layer is formed. Next, at least one blind via is formed in the wiring carrying substrate. Next, the wiring carrying substrate is laminated to another wiring carrying substrate via an insulation layer. The insulation layer is disposed between the wiring layers of the wiring carrying substrates and full fills the blind via. Next, parts of the carry substrates are removed to expose the insulation layer in the blind via. Next, a conductive pillar connected between the wiring layers is formed. Next, the rest carry substrates are removed.
    Type: Grant
    Filed: December 4, 2008
    Date of Patent: May 28, 2013
    Assignee: Unimicron Technology Corp.
    Inventors: Tsung-Yuan Chen, Chun-Chien Chen, Cheng-Po Yu
  • Patent number: 8436251
    Abstract: Articles and methods of manufacture are provided for using laser energy in an automated bonding machine to effect laser welding of ribbons to electronic components, particularly conductive ribbons comprising titanium for microelectronic circuits. Bonding and connection of microelectronic circuits with discrete heating avoids heat damage to peripheral microelectronic components. Bonding of flexible materials and low-resistance materials are possible, and are less dependant on substrate and terminal stability in comparison to other bonding methods. The ribbon-connections can forgo the use of blocks, bond pads, and bond pad arrays for attaching ribbon to a printed wiring board. Profile height of the ribbon-connection is decreased and the density of ribbons and bonding sites can be increased compared to ribbon-connections employing bonding pads.
    Type: Grant
    Filed: July 8, 2009
    Date of Patent: May 7, 2013
    Assignee: Medtronic, Inc.
    Inventor: Steven Boyd
  • Patent number: 8411457
    Abstract: A semiconductor package substrate suitable for supporting a damage-sensitive device, including a substrate core having a first and opposite surface; at least one pair of metal layers covering the first and opposite surfaces of the package substrate core, which define first and opposite metal layer groups, at least one of said layer groups including at least one metal support zone; one pair of solder mask layers covering the outermost metal layers of the at least one pair of metal layers; and a plurality of routing lines; wherein the at least one metal support zone is formed so that it lies beneath at least one side of the base of the damage-sensitive device and so as to occupy a substantial portion of the area beneath the damage-sensitive device which is free of said routing lines; a method for the production of such substrate is also described.
    Type: Grant
    Filed: November 10, 2009
    Date of Patent: April 2, 2013
    Assignee: STMIcroelectronics S.r.l.
    Inventors: Federico Ziglioli, Giovanni Graziosi, Mario Cortese
  • Patent number: 8400777
    Abstract: When silver oxide is reduced to silver, a large number of cores of metallic silver are formed inside the silver oxide. Then, the silver oxide is reduced in a manner of being hollowed out while its original outer configuration is being maintained. As a result, the curvature of the silver generated becomes larger. The utilization of this microscopic-particle implementation mechanism allows accomplishment of the bonding even if the silver oxide is supplied not in a particle-like configuration, but in a closely-packed layer-like configuration. In the present invention, there is provided an electronic member including an electrode for inputting/outputting an electrical signal, or a connection terminal for establishing a connection with the electrical signal, wherein the uppermost surface of the electrode or the connection terminal is a silver-oxide layer.
    Type: Grant
    Filed: January 29, 2010
    Date of Patent: March 19, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Eiichi Ide, Toshiaki Morita, Yusuke Yasuda
  • Patent number: 8395051
    Abstract: Methods of forming a microelectronic structure are described. Those methods include doping a lead free solder material with nickel, wherein the nickel comprises up to about 0.2 percent by weight of the solder material, and then applying the solder material to a substrate comprising a copper pad.
    Type: Grant
    Filed: December 23, 2008
    Date of Patent: March 12, 2013
    Assignee: Intel Corporation
    Inventors: Mengzhi Pang, Charan Gurumurthy
  • Patent number: 8391016
    Abstract: A carbon nanotube solder is formed on a substrate of an integrated circuit package. The carbon nanotube solder exhibits high heat and electrical conductivities. The carbon nanotube solder is used as a solder microcap on a metal bump for communication between an integrated circuit device and external structures.
    Type: Grant
    Filed: August 25, 2009
    Date of Patent: March 5, 2013
    Assignee: Intel Corporation
    Inventor: Chi-won Hwang
  • Patent number: 8315065
    Abstract: A multi-chip module (MCM) is described. This MCM includes at least two substrates that are remateably mechanically coupled by positive and negative features on facing surfaces of the substrates. These positive and negative features may mate and self-lock with each other. For example, the positive features on one of the surfaces may include pairs of counterposed micro-springs, and the negative features may include pits or grooves on the other surface. When the substrates are mechanically coupled, a given pair of positive features may provide a force in a plane of the other surface. Furthermore, by compressing the MCM so that the surfaces of the substrates are pushed toward each other, the mechanical coupling may be released.
    Type: Grant
    Filed: September 28, 2009
    Date of Patent: November 20, 2012
    Assignee: Oracle America, Inc.
    Inventors: Jing Shi, Hiren D. Thacker, Ashok V. Krishnamoorthy
  • Patent number: 8300420
    Abstract: A circuit substrate includes an electrically conductive layer having electrically conductive patterns formed therein, an insulating layer having a through hole, and a composite layer positioned between the electrically conductive layer and the insulating layer. The through hole is configured for having an electronic component mounted thereon. The composite layer includes a polymer matrix and at least one carbon nanotube bundle embedded in the polymer matrix. One end of the at least one carbon nanotube bundle contacts the electrically conductive patterns, and the other is exposed in the through hole of the insulation layer.
    Type: Grant
    Filed: May 24, 2009
    Date of Patent: October 30, 2012
    Assignee: Zhen Ding Technology Co., Ltd.
    Inventors: Chung-Jen Tsai, Hung-Yi Chang, Chia-Cheng Chen, Meng-Chieh Hsu, Cheng-Hsien Lin
  • Patent number: 8273994
    Abstract: A printed circuit board (PCB) includes a ball grid array (BGA). The PCB further includes a first BGA pad having a circular shape, and a first via having a circular shape, where the circular shape of the first via overlaps a portion of the circular shape of the first BGA pad and is rotated diagonally relative to a center of the first BGA pad. The PCB also includes a second BGA pad having a circular shape, and a second via having a circular shape, where the circular shape of the second via overlaps a portion of the circular shape of the second BGA pad and is rotated diagonally relative to a center of the second pad, and where a center of the second via is located at a first distance from the center of the first via and at a first angle relative to an axis that crosses a center of the first via.
    Type: Grant
    Filed: December 28, 2009
    Date of Patent: September 25, 2012
    Assignee: Juniper Networks, Inc.
    Inventors: Boris Reynov, Ping Yue, Shreeram Siddhaye, John Cleveland, Chebrolu Srinivas, Srinivas Venkataraman
  • Patent number: 8243464
    Abstract: Disclosed is a printed circuit board structure which is manufactured by providing a core board, forming an inner circuit layer on the core board surface, forming a bonding pad on the inner circuit, forming a ring-shaped anti-etching layer on the bonding pad, forming an anti-soldering insulation layer on the ring-shaped anti-etching layer and the bonding pad, and forming an opening to expose a part of the bonding pad, wherein the radius of the opening is shorter than the radius of the ring-shaped anti-etching layer, and the bonding pad surface is free of concave. The described structure may prevent the solder extending along the bottom void of the anti-soldering insulation layer to other regions.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: August 14, 2012
    Assignee: Nan Ya PCB Corp.
    Inventor: Hsien-Chieh Lin
  • Patent number: 8241760
    Abstract: A joint structure of the present invention includes a conductive member containing copper as a major component thereof, an electrode member containing copper as a major component thereof, and a joint portion formed by fusion welding the conductive member and the electrode member with a brazing material containing tin as a major component thereof and containing substantially no copper, wherein the amount of copper atoms contained in the alloy in the central part of the joint portion is higher than that in the outer circumference part.
    Type: Grant
    Filed: September 14, 2006
    Date of Patent: August 14, 2012
    Assignee: Sumitomo Bakelite Company, Ltd.
    Inventor: Toshiaki Chuma
  • Patent number: 8184443
    Abstract: A retention assembly for a SIM card incorporated in a portable electronic device having a main body, includes a receiving portion, a limiting sheet and a resilient pressing member. The receiving portion is defined in the main body to receive the SIM card. The receiving portion defines an entrance end. The limiting sheet extends from a side of the receiving portion to an opposite side of the receiving portion to resist the SIM card. The resilient pressing member includes a fixing portion fixed to the main body, a limiting portion resisting an end of the SIM card adjacent to the entrance end of the receiving portion, and a resilient portion interconnecting with the fixing portion and the limiting portion to press against the SIM card.
    Type: Grant
    Filed: July 30, 2009
    Date of Patent: May 22, 2012
    Assignee: Chi Mei Communication Systems, Inc.
    Inventor: Cheng-Lung Chang
  • Patent number: 8164917
    Abstract: A base mechanism for use in a multi-chip module (MCM) is described. This base mechanism includes a substrate having top and bottom surfaces. The bottom surface includes first electrical connectors that convey power, and through-substrate vias (TSVs) between the top and bottom surfaces are electrically coupled to these electrical connectors. Furthermore, a bridge chip is rigidly mechanically coupled to the top surface. This bridge chip includes proximity communication connectors that communicate information via proximity communication with one or more island chips in the MCM. Additionally, spacers are rigidly mechanically coupled to the top surface of the substrate. In conjunction with the bridge chip, the spacers define cavities on the top surface, which include second electrical connectors. These second electrical connectors are electrically coupled to the TSVs, and communicate additional information with and convey power to the one or more island chips.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: April 24, 2012
    Assignee: Oracle America, Inc.
    Inventors: Jing Shi, Nyles Nettleton, Bruce M. Guenin
  • Patent number: 8039753
    Abstract: A flexible printed circuit board includes a first substrate portion having at least one first terminal, a second substrate portion in communication with the first substrate portion and having at least one circuit device, a connection substrate portion in communication with the second substrate portion, the connection substrate portion extending away from the second substrate portion in a same direction as the first substrate portion, and a third substrate portion in communication with the connection substrate portion, the third substrate portion having at least one second terminal.
    Type: Grant
    Filed: June 25, 2007
    Date of Patent: October 18, 2011
    Assignee: Samsung Mobile Display Co., Ltd.
    Inventors: Jin-seok Jang, Jae-mo Chung, Jin-hee Sung, So-bo Chung, Jeong-su Kim, Dong-ho Lee, Tae-soo Kim
  • Patent number: 8021921
    Abstract: A copper pillar may be provided on a chip and a first tin-containing layer may be provided over the copper pillar. A second tin-containing layer may be provided on a substrate. The first tin-containing layer may be joined with the second tin-containing layer during a packaging process.
    Type: Grant
    Filed: May 29, 2008
    Date of Patent: September 20, 2011
    Assignee: Megica Corporation
    Inventors: Shih-Hsiung Lin, Mou-Shiung Lin
  • Patent number: 7982137
    Abstract: A die having a base formed of a first material is connected to a board having a base formed of a second material. An interposer having a coefficient of thermal expansion intermediate coefficients of thermal expansion of the first and second materials is positioned between the die and the board.
    Type: Grant
    Filed: June 27, 2007
    Date of Patent: July 19, 2011
    Assignee: Hamilton Sundstrand Corporation
    Inventors: Robert C. Cooney, Joseph M. Wilkinson
  • Patent number: 7966721
    Abstract: In order to mount an electronic component, a connection terminal of the electronic component is bonded to electrodes of a substrate. This is done by using solder paste which mixes solder particles in a thermosetting adhesive. The solder paste is supplied to the electrodes and a recess. Solder print parts are formed. The electronic component is mounted and the connection terminal and the main body of the electronic component are adhered to the solder print parts, and are heated in this state by reflow. As a result, the connection terminal and the electrodes are bonded by a solder junction.
    Type: Grant
    Filed: December 21, 2005
    Date of Patent: June 28, 2011
    Assignee: Panasonic Corporation
    Inventors: Yoshiyuki Wada, Tadahiko Sakai
  • Patent number: 7968372
    Abstract: A copper pillar may be provided on a chip and a first tin-containing layer may be provided over the copper pillar. A second tin-containing layer may be provided on a substrate. The first tin-containing layer may be joined with the second tin-containing layer during a packaging process.
    Type: Grant
    Filed: May 29, 2008
    Date of Patent: June 28, 2011
    Assignee: Megica Corporation
    Inventors: Shih-Hsiung Lin, Mou-Shiung Lin
  • Patent number: 7967454
    Abstract: An electro-optic apparatus includes an electro-optic panel, a wiring board, and an integrated circuit unit. The integrated circuit unit including a heat radiating member arranged so as to overlap at least partly with the integrated circuit unit.
    Type: Grant
    Filed: September 19, 2008
    Date of Patent: June 28, 2011
    Assignee: Seiko Epson Corporation
    Inventors: Hidekazu Hirabayashi, Tomoaki Miyashita