With Specific Connection Material Patents (Class 361/779)
  • Patent number: 8400777
    Abstract: When silver oxide is reduced to silver, a large number of cores of metallic silver are formed inside the silver oxide. Then, the silver oxide is reduced in a manner of being hollowed out while its original outer configuration is being maintained. As a result, the curvature of the silver generated becomes larger. The utilization of this microscopic-particle implementation mechanism allows accomplishment of the bonding even if the silver oxide is supplied not in a particle-like configuration, but in a closely-packed layer-like configuration. In the present invention, there is provided an electronic member including an electrode for inputting/outputting an electrical signal, or a connection terminal for establishing a connection with the electrical signal, wherein the uppermost surface of the electrode or the connection terminal is a silver-oxide layer.
    Type: Grant
    Filed: January 29, 2010
    Date of Patent: March 19, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Eiichi Ide, Toshiaki Morita, Yusuke Yasuda
  • Patent number: 8395051
    Abstract: Methods of forming a microelectronic structure are described. Those methods include doping a lead free solder material with nickel, wherein the nickel comprises up to about 0.2 percent by weight of the solder material, and then applying the solder material to a substrate comprising a copper pad.
    Type: Grant
    Filed: December 23, 2008
    Date of Patent: March 12, 2013
    Assignee: Intel Corporation
    Inventors: Mengzhi Pang, Charan Gurumurthy
  • Patent number: 8391016
    Abstract: A carbon nanotube solder is formed on a substrate of an integrated circuit package. The carbon nanotube solder exhibits high heat and electrical conductivities. The carbon nanotube solder is used as a solder microcap on a metal bump for communication between an integrated circuit device and external structures.
    Type: Grant
    Filed: August 25, 2009
    Date of Patent: March 5, 2013
    Assignee: Intel Corporation
    Inventor: Chi-won Hwang
  • Patent number: 8315065
    Abstract: A multi-chip module (MCM) is described. This MCM includes at least two substrates that are remateably mechanically coupled by positive and negative features on facing surfaces of the substrates. These positive and negative features may mate and self-lock with each other. For example, the positive features on one of the surfaces may include pairs of counterposed micro-springs, and the negative features may include pits or grooves on the other surface. When the substrates are mechanically coupled, a given pair of positive features may provide a force in a plane of the other surface. Furthermore, by compressing the MCM so that the surfaces of the substrates are pushed toward each other, the mechanical coupling may be released.
    Type: Grant
    Filed: September 28, 2009
    Date of Patent: November 20, 2012
    Assignee: Oracle America, Inc.
    Inventors: Jing Shi, Hiren D. Thacker, Ashok V. Krishnamoorthy
  • Patent number: 8300420
    Abstract: A circuit substrate includes an electrically conductive layer having electrically conductive patterns formed therein, an insulating layer having a through hole, and a composite layer positioned between the electrically conductive layer and the insulating layer. The through hole is configured for having an electronic component mounted thereon. The composite layer includes a polymer matrix and at least one carbon nanotube bundle embedded in the polymer matrix. One end of the at least one carbon nanotube bundle contacts the electrically conductive patterns, and the other is exposed in the through hole of the insulation layer.
    Type: Grant
    Filed: May 24, 2009
    Date of Patent: October 30, 2012
    Assignee: Zhen Ding Technology Co., Ltd.
    Inventors: Chung-Jen Tsai, Hung-Yi Chang, Chia-Cheng Chen, Meng-Chieh Hsu, Cheng-Hsien Lin
  • Patent number: 8273994
    Abstract: A printed circuit board (PCB) includes a ball grid array (BGA). The PCB further includes a first BGA pad having a circular shape, and a first via having a circular shape, where the circular shape of the first via overlaps a portion of the circular shape of the first BGA pad and is rotated diagonally relative to a center of the first BGA pad. The PCB also includes a second BGA pad having a circular shape, and a second via having a circular shape, where the circular shape of the second via overlaps a portion of the circular shape of the second BGA pad and is rotated diagonally relative to a center of the second pad, and where a center of the second via is located at a first distance from the center of the first via and at a first angle relative to an axis that crosses a center of the first via.
    Type: Grant
    Filed: December 28, 2009
    Date of Patent: September 25, 2012
    Assignee: Juniper Networks, Inc.
    Inventors: Boris Reynov, Ping Yue, Shreeram Siddhaye, John Cleveland, Chebrolu Srinivas, Srinivas Venkataraman
  • Patent number: 8243464
    Abstract: Disclosed is a printed circuit board structure which is manufactured by providing a core board, forming an inner circuit layer on the core board surface, forming a bonding pad on the inner circuit, forming a ring-shaped anti-etching layer on the bonding pad, forming an anti-soldering insulation layer on the ring-shaped anti-etching layer and the bonding pad, and forming an opening to expose a part of the bonding pad, wherein the radius of the opening is shorter than the radius of the ring-shaped anti-etching layer, and the bonding pad surface is free of concave. The described structure may prevent the solder extending along the bottom void of the anti-soldering insulation layer to other regions.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: August 14, 2012
    Assignee: Nan Ya PCB Corp.
    Inventor: Hsien-Chieh Lin
  • Patent number: 8241760
    Abstract: A joint structure of the present invention includes a conductive member containing copper as a major component thereof, an electrode member containing copper as a major component thereof, and a joint portion formed by fusion welding the conductive member and the electrode member with a brazing material containing tin as a major component thereof and containing substantially no copper, wherein the amount of copper atoms contained in the alloy in the central part of the joint portion is higher than that in the outer circumference part.
    Type: Grant
    Filed: September 14, 2006
    Date of Patent: August 14, 2012
    Assignee: Sumitomo Bakelite Company, Ltd.
    Inventor: Toshiaki Chuma
  • Patent number: 8184443
    Abstract: A retention assembly for a SIM card incorporated in a portable electronic device having a main body, includes a receiving portion, a limiting sheet and a resilient pressing member. The receiving portion is defined in the main body to receive the SIM card. The receiving portion defines an entrance end. The limiting sheet extends from a side of the receiving portion to an opposite side of the receiving portion to resist the SIM card. The resilient pressing member includes a fixing portion fixed to the main body, a limiting portion resisting an end of the SIM card adjacent to the entrance end of the receiving portion, and a resilient portion interconnecting with the fixing portion and the limiting portion to press against the SIM card.
    Type: Grant
    Filed: July 30, 2009
    Date of Patent: May 22, 2012
    Assignee: Chi Mei Communication Systems, Inc.
    Inventor: Cheng-Lung Chang
  • Patent number: 8164917
    Abstract: A base mechanism for use in a multi-chip module (MCM) is described. This base mechanism includes a substrate having top and bottom surfaces. The bottom surface includes first electrical connectors that convey power, and through-substrate vias (TSVs) between the top and bottom surfaces are electrically coupled to these electrical connectors. Furthermore, a bridge chip is rigidly mechanically coupled to the top surface. This bridge chip includes proximity communication connectors that communicate information via proximity communication with one or more island chips in the MCM. Additionally, spacers are rigidly mechanically coupled to the top surface of the substrate. In conjunction with the bridge chip, the spacers define cavities on the top surface, which include second electrical connectors. These second electrical connectors are electrically coupled to the TSVs, and communicate additional information with and convey power to the one or more island chips.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: April 24, 2012
    Assignee: Oracle America, Inc.
    Inventors: Jing Shi, Nyles Nettleton, Bruce M. Guenin
  • Patent number: 8039753
    Abstract: A flexible printed circuit board includes a first substrate portion having at least one first terminal, a second substrate portion in communication with the first substrate portion and having at least one circuit device, a connection substrate portion in communication with the second substrate portion, the connection substrate portion extending away from the second substrate portion in a same direction as the first substrate portion, and a third substrate portion in communication with the connection substrate portion, the third substrate portion having at least one second terminal.
    Type: Grant
    Filed: June 25, 2007
    Date of Patent: October 18, 2011
    Assignee: Samsung Mobile Display Co., Ltd.
    Inventors: Jin-seok Jang, Jae-mo Chung, Jin-hee Sung, So-bo Chung, Jeong-su Kim, Dong-ho Lee, Tae-soo Kim
  • Patent number: 8021921
    Abstract: A copper pillar may be provided on a chip and a first tin-containing layer may be provided over the copper pillar. A second tin-containing layer may be provided on a substrate. The first tin-containing layer may be joined with the second tin-containing layer during a packaging process.
    Type: Grant
    Filed: May 29, 2008
    Date of Patent: September 20, 2011
    Assignee: Megica Corporation
    Inventors: Shih-Hsiung Lin, Mou-Shiung Lin
  • Patent number: 7982137
    Abstract: A die having a base formed of a first material is connected to a board having a base formed of a second material. An interposer having a coefficient of thermal expansion intermediate coefficients of thermal expansion of the first and second materials is positioned between the die and the board.
    Type: Grant
    Filed: June 27, 2007
    Date of Patent: July 19, 2011
    Assignee: Hamilton Sundstrand Corporation
    Inventors: Robert C. Cooney, Joseph M. Wilkinson
  • Patent number: 7966721
    Abstract: In order to mount an electronic component, a connection terminal of the electronic component is bonded to electrodes of a substrate. This is done by using solder paste which mixes solder particles in a thermosetting adhesive. The solder paste is supplied to the electrodes and a recess. Solder print parts are formed. The electronic component is mounted and the connection terminal and the main body of the electronic component are adhered to the solder print parts, and are heated in this state by reflow. As a result, the connection terminal and the electrodes are bonded by a solder junction.
    Type: Grant
    Filed: December 21, 2005
    Date of Patent: June 28, 2011
    Assignee: Panasonic Corporation
    Inventors: Yoshiyuki Wada, Tadahiko Sakai
  • Patent number: 7967454
    Abstract: An electro-optic apparatus includes an electro-optic panel, a wiring board, and an integrated circuit unit. The integrated circuit unit including a heat radiating member arranged so as to overlap at least partly with the integrated circuit unit.
    Type: Grant
    Filed: September 19, 2008
    Date of Patent: June 28, 2011
    Assignee: Seiko Epson Corporation
    Inventors: Hidekazu Hirabayashi, Tomoaki Miyashita
  • Patent number: 7968372
    Abstract: A copper pillar may be provided on a chip and a first tin-containing layer may be provided over the copper pillar. A second tin-containing layer may be provided on a substrate. The first tin-containing layer may be joined with the second tin-containing layer during a packaging process.
    Type: Grant
    Filed: May 29, 2008
    Date of Patent: June 28, 2011
    Assignee: Megica Corporation
    Inventors: Shih-Hsiung Lin, Mou-Shiung Lin
  • Patent number: 7957156
    Abstract: An electrical connection assembly includes a substrate having first and second sides and a substrate aperture formed therein. The substrate is made of an electrically non-conductive material. A busbar is attached to the first side of the substrate. The busbar has a busbar aperture formed therein. A trace is formed on the second surface of the substrate. The busbar and trace are formed of an electrically conductive material. A pin is disposed in both the substrate aperture and the busbar aperture, wherein the pin is in electrical communication with the busbar and the trace.
    Type: Grant
    Filed: August 6, 2007
    Date of Patent: June 7, 2011
    Assignee: Lear Corporation
    Inventor: Antonio Palomo
  • Patent number: 7936569
    Abstract: In a hybrid integrated circuit device that is a circuit device of the present invention, a conductive pattern including pads is formed on a surface of a substrate. A first pad is formed to be relatively large since a heat sink is mounted thereon. A second pad is a small pad to which a chip component or a small signal transistor is fixed. In the present invention, a plated film made of nickel is formed on a surface of the first pad. Therefore, the first pad and a solder never come into contact with each other. Thus, a Cu/Sn alloy layer having poor soldering properties is not generated but a Ni/Sn alloy layer having excellent soldering properties is generated. Consequently, occurrence of sink in the melted solder is suppressed.
    Type: Grant
    Filed: January 30, 2006
    Date of Patent: May 3, 2011
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Sadamichi Takakusaki, Noriaki Sakamoto, Motoichi Nezu, Yusuke Igarashi
  • Patent number: 7876572
    Abstract: A wiring board of the present invention includes a dummy wiring in a semiconductor-chip mount area on which a semiconductor chip is to be mounted. The dummy wiring is arranged in a manner such that all wiring-lines included in the dummy wiring each have a free end within the semiconductor-chip mount area. This prevents a defect due to vaporization and expansion of moisture inside a semiconductor apparatus, with a simple structure and without raising costs.
    Type: Grant
    Filed: January 23, 2007
    Date of Patent: January 25, 2011
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Yoshiki Sota
  • Patent number: 7839135
    Abstract: A structure has a printed board carried by a metal chassis. A printed board carrying chassis analyzing system, a printed board carrying chassis analyzing method, a printed board carrying chassis structure, and a printed board carrying chassis analyzing program are provided to achieve a screw-fastened arrangement for predicting unnecessary radiation frequencies and for reducing unnecessary radiation. An equivalent circuit model including a printed board power and ground plane pair, a pair of confronting surfaces of a printed board and a chassis, and screw-fastened grounding posts is generated and analyzed to predict unnecessary radiation frequencies and unnecessary radiation reductions and to select a screw-fastened arrangement for reducing unnecessary radiation.
    Type: Grant
    Filed: April 24, 2007
    Date of Patent: November 23, 2010
    Assignee: NEC Corporation
    Inventors: Naoki Kobayashi, Ken Morishita, Takashi Harada
  • Patent number: 7652895
    Abstract: The invention relates to an electric insulating body (2) provided with a conductor pattern (1) and an electronic device (10) comprising such a body (2) and at least one electronic element (30). According to the invention, the body (2) has first and second faces (2A, 2B) in between of which an angle of less than 180 degrees is defined, wherein the conductor pattern (1) of the body (2) extends over both faces (2A, 2B), which body (2) carries both the conductor pattern (1) and the electronic element (30). The conductor pattern (1) comprises strip-shaped regions (1A) and regions (1B) with a larger width than the strip-shaped regions (1A), which regions (1B) are suitable for electrically contacting the electronic element (30). The electronic element (30) is, for example, a camera. The device (10) with such a camera is particularly suitable for use in a mobile communication apparatus.
    Type: Grant
    Filed: April 10, 2003
    Date of Patent: January 26, 2010
    Assignee: TPO Displays Corp.
    Inventors: Fransiscus Gerardus Coenradus Verweg, Johannus Wilhelmus Weekamp
  • Patent number: 7616451
    Abstract: A semiconductor package substrate suitable for supporting a damage-sensitive device, including a substrate core having a first and opposite surface; at least one pair of metal layers covering the first and opposite surfaces of the package substrate core, which define first and opposite metal layer groups, at least one of said layer groups including at least one metal support zone; one pair of solder mask layers covering the outermost metal layers of the at least one pair of metal layers; and a plurality of routing lines; wherein the at least one metal support zone is formed so that it lies beneath at least one side of the base of the damage-sensitive device and so as to occupy a substantial portion of the area beneath the damage-sensitive device which is free of said routing lines; a method for the production of such substrate is also described.
    Type: Grant
    Filed: October 13, 2006
    Date of Patent: November 10, 2009
    Assignee: STMicroelectronics S.r.l.
    Inventors: Federico Ziglioli, Giovanni Graziosi, Mario Cortese
  • Publication number: 20090202142
    Abstract: A circuit board according to the present invention comprises an insulating layer, a first electronic component mounted on the insulating layer, and a solder marker provided on the insulating layer. A first solder having a first melting point constitutes the solder marker. The first electronic component is mounted on the insulating layer via a second solder having a second melting point lower than the first melting point.
    Type: Application
    Filed: March 30, 2007
    Publication date: August 13, 2009
    Inventors: Yukihiro Ishimaru, Toshiyuki Kojima, Rikiya Okimoto
  • Patent number: 7549373
    Abstract: A detonator assembly according to one arrangement includes a capacitor discharge unit having a capacitor and a resistor formed on a surface of the capacitor. At least one side of the resistor is electrically connected to one electrode of the capacitor. In another arrangement, another type of energy source besides the capacitor is used.
    Type: Grant
    Filed: November 26, 2002
    Date of Patent: June 23, 2009
    Assignee: Schlumberger Technology Corporation
    Inventors: James E Brooks, Nolan C. Lerche, Frank A. Duva
  • Patent number: 7525816
    Abstract: The present invention provides a wiring board including a first board provided with a first wiring pattern and a second board provided with a second wiring pattern while the first wiring pattern and the second wiring pattern are electrically connected, wherein the first board includes: a board insertion opening in which the second board is inserted; and a first connection pattern provided inside the board insertion opening and electrically connected to the first wiring pattern, and the second board includes: an inserting portion to be inserted into the board insertion opening of the first board; and a second connection pattern provided at a position opposed to the first connection pattern and electrically connected to the second wiring pattern in the case where the inserting portion of the second board is inserted into the board insertion opening of the first board, and further comprising: solder or brazing filler metal applied at least to a surface of one of the first connection pattern and second connection
    Type: Grant
    Filed: December 1, 2006
    Date of Patent: April 28, 2009
    Assignee: Fujifilm Corporation
    Inventor: Youichi Sawachi
  • Publication number: 20080285246
    Abstract: A resist 7 of a predetermined thickness is formed on a printed circuit board 1 except electrode-opposing portions 1a (FIG. 1A), and a silk screen printed layer 9 of a predetermined thickness is formed on the resist 7 (FIG. 1B). Thereafter, a concave portion 2b of a film capacitor 2 is bonded to the silk screen printed layer 9 by an adhesive double coated tape 6 of a predetermined thickness in such a manner that electrode portions 2a of the film capacitor 2 are opposed respectively to the electrode-opposing portions 1a of the printed circuit board 1 (FIG. 1D). Here, the sum of the thicknesses of the resist 7, silk screen printed layer 9 and adhesive double coated tape 6 is not smaller than a concave-convex height difference L1 of the film capacitor 2, and with this arrangement the electrode portions 2a of the film capacitor 2 are prevented from interfering with the printed circuit board 1.
    Type: Application
    Filed: May 8, 2008
    Publication date: November 20, 2008
    Applicant: YAZAKI CORPORATION
    Inventor: Yoshihiro KAWAMURA
  • Publication number: 20080239684
    Abstract: A wiring board including, on a resin insulating layer, an Ni—Cu alloy bonding seed layer constituted by 20 to 75 wt % of Ni and Cu to be a residual part and a wiring layer constituted by Cu formed thereon is provided. It is possible to manufacture the wiring board by (A) forming the Ni—Cu alloy bonding seed layer through a one-time treatment and removing an unnecessary portion through one-time etching after wiring patterning, or (B) forming the Ni—Cu alloy bonding seed layer and a Cu layer thereon and patterning thereof in a lump by etching. A wiring board in which a wiring layer is formed by an Ni—Cu alloy constituted by 20 to 75 wt % of Ni and Cu to be a residual part over a whole thickness of the wiring layer is also provided.
    Type: Application
    Filed: March 31, 2008
    Publication date: October 2, 2008
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Tomoo Yamasaki
  • Patent number: 7377032
    Abstract: A printed wiring board for mounting electronic components includes an insulating layer and a wiring pattern formed on one surface of the insulating layer, wherein one end portion of a filled via 4 is connected with the wiring pattern and the other end portion is overlaid with a covering layer 9 obtained by applying a conductive paste to cover at least the boundary between the filled via 4 and the insulating layer 2; alternatively, a plating resist 7 is formed at the other end portion to cover at least the boundary between the filled via 4 and the insulating layer 2, and is removed after an end portion of the filled via 4 enclosed within the plating resist 7 is plated to produce a terminal layer, thereby preventing a wet processing liquid such as a tin plating solution from leaking in between the filled via 4 and the insulating layer 2.
    Type: Grant
    Filed: November 18, 2004
    Date of Patent: May 27, 2008
    Assignee: Mitsui Mining & Smelting Co., Ltd.
    Inventors: Shinichi Sumi, Yutaka Iguchi
  • Patent number: 7301779
    Abstract: A multiplicity of nanotubes are applied to at least one external chip metal contact of an electronic chip in order to make contact between the electronic chip and a further electronic chip.
    Type: Grant
    Filed: June 3, 2002
    Date of Patent: November 27, 2007
    Assignee: Infineon Technologies AG
    Inventors: Wolfgang Hönlein, Hyang-Sook Klose, legal representative, Franz Kreupl, Werner Simbürger, Helmut Klose, deceased
  • Patent number: 7268303
    Abstract: In a circuit board including a pad for mounting a ball grid array and a wiring, a mounting structure of the ball grid array, an electro-optic device, and an electronic device, the circuit board includes a pad for mounting the ball grid array, a wiring for connecting the pad and an external terminal, and a soldering resist having an opening portion exposing the pad and the wiring.
    Type: Grant
    Filed: October 9, 2003
    Date of Patent: September 11, 2007
    Assignee: Seiko Epson Corporation
    Inventor: Takeshi Ashida
  • Patent number: 7268438
    Abstract: A columnar bump formed of copper etc. is formed on a wiring film of a semiconductor chip through an interconnected film and an adhesive film in a wafer unit by electrolytic plating in which package formation is possible. An oxidation prevention film is formed of such as gold on an upper surface or a part of the upper surface and side surface. A wet prevention film of such as an oxide film is formed on the columnar bump side as needed. If this bump is soldered to the pad on a packaging substrate, solder gets wet in the whole region of the columnar bump upper surface and only a part of the side surface. Stabilized and reliable junction form can be thus formed. Moreover, since the columnar bump does not fuse, the distance between a semiconductor board and a packaging board is not be narrowed by solder.
    Type: Grant
    Filed: November 14, 2005
    Date of Patent: September 11, 2007
    Assignee: NEC Corporation
    Inventors: Tomohiro Nishiyama, Masamoto Tago
  • Patent number: 7259683
    Abstract: A rack has a plurality of LEDs arranged on the front surface thereof correspondingly to respective units. The rack is provided with an LED lighting circuit which lights these LEDs, on the back of a display section and an input section. The LED lighting circuit has an LED lighting control section and a memory. The LED lighting control section acquires correspondence relation information indicating correspondence between servers and apparatuses from the input section, and stores the information in the memory. When a server is selected, the LED lighting circuit lights some of the plurality of LEDs based on the correspondence relation information stored in the memory.
    Type: Grant
    Filed: November 20, 2003
    Date of Patent: August 21, 2007
    Assignee: NEC Corporation
    Inventor: Takashi Abe
  • Patent number: 7239524
    Abstract: A resistive element, a circuit board, and a circuit package, as well as a method of adding a resistive element to a circuit board are described. The resistive element includes a first contact point connected to a capacitor terminal, a second contact point connected to a circuit board plane, and resistive material connected to the first and second contact points. The invention may also include a circuit board with one or more resistive elements, as well as a circuit package, such as an integrated circuit or a discrete bypass capacitor, including one or more resistive elements, applied to an outside surface. The value of resistance for the resistive element can be selected by design to have a predetermined relationship with the equivalent resistance of an associated circuit board and connecting circuitry.
    Type: Grant
    Filed: October 12, 2001
    Date of Patent: July 3, 2007
    Assignee: Intel Corporation
    Inventors: Chee-Yee Chung, Robert L. Sankman, Alex Waizman
  • Patent number: 7120033
    Abstract: An electrically conducting bonding connection (B) is produced between an electronic circuit (S) arranged on an electrically conducting support plate (1) and the support plate (1) by providing a hole (4, 5), into which an electrically conducting bonding element (2) with a bondable surface (3) is pressed in such a way that the support plate (1) and the bonding element (2) enter into an electrically conducting and frictional connection; the bonding connection is subsequently produced with the bonding element (2).
    Type: Grant
    Filed: July 16, 2002
    Date of Patent: October 10, 2006
    Assignee: Siemens Aktiengesellschaft
    Inventors: Kurt Gross, Hans Rappl
  • Patent number: 7084351
    Abstract: A device comprising a circuit, a lead having a first end connected to the circuit and having a second end, and a deformable structure connected to the second end of the lead. The invention may be embodied on a circuit board, so that the circuit board includes a substrate and a deformable structure connected to said substrate.
    Type: Grant
    Filed: September 9, 2002
    Date of Patent: August 1, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Salman Akram, Warren M. Farnworth, Alan G. Wood, J. Michael Brooks, Eugene H. Cloud
  • Patent number: 7034231
    Abstract: A process is revealed whereby resistors can be manufactured integral with a printed circuit board by plating the resistors onto the insulative substrate. Uniformization of the insulative substrate through etching and oxidation of the plated resistor are discussed as techniques for improving the uniformity and consistency of the plated resistors. Trimming and baking are also disclosed as methods for adjusting and stabilizing the resistance of the plated resistors.
    Type: Grant
    Filed: April 21, 2003
    Date of Patent: April 25, 2006
    Inventors: Peter Kukanskis, Dennis Fritz, Frank Durso, Steven Castaldi, David Sawoska
  • Patent number: 6940023
    Abstract: The present invention provides a board ensuring no peel-off of a wall and a land, even if a part is soldered to the board with lead-free solder. The board 10 is comprised of N (N?3) layer patterns electrically insulated from one another, and is formed with a through-hole 14 into which an electrode 19 of an electronic part 18 is to be inserted. An external land 15 is formed on a surface of each of the first and N-th layer patterns. An electrically conductive layer 17 is formed on an inner wall of the through-hole 14 such that the electrically conductive layer is electrically connected to the external land 15 of each of the first and N-th layer patterns. The electronic part 18 is fixed in the through-hole 14 with lead-free solder 20 filled in the through-hole 14. At least one internal land 16 extending from the electrically conductive layer 17 is formed in the same layer as a M-th layer pattern (2?M?(N?1)). The internal land 16 is not electrically connected to the M-th layer pattern.
    Type: Grant
    Filed: July 16, 2004
    Date of Patent: September 6, 2005
    Assignee: NEC Corporation
    Inventors: Naomi Ishizuka, Eiichi Kono
  • Patent number: 6933449
    Abstract: A printed circuit board having at least one layer of conductive traces on an external surface has at least one preformed solder element placed on a conductive trace area of the printed circuit board requiring a greater than standard amount of solder. The at least one preformed solder element is reflowed to form a connection with the layer of printed solder.
    Type: Grant
    Filed: July 10, 2002
    Date of Patent: August 23, 2005
    Assignee: Intel Corporation
    Inventor: Dudi Amir
  • Patent number: 6914198
    Abstract: Disclosed is a device comprising a circuit having an active side and a non-active side, a package enclosing the active side of the circuit and not enclosing a portion of the non-active side of the circuit, and a lead having a first end connected to the active side of the circuit via a lead-over-chip connection, and having a second end extending from the package. Also disclosed is a device comprising a circuit and a lead formed from a flexible conductor, with the lead having a first end connected to the circuit.
    Type: Grant
    Filed: September 9, 2002
    Date of Patent: July 5, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Salman Akram, Warren M. Farnworth, Alan G. Wood, J. Michael Brooks, Eugene H. Cloud
  • Patent number: 6909055
    Abstract: A device comprising a circuit, a lead having a first end connected to the circuit and having a second end, and a deformable structure connected to the second end of the lead. The invention may be embodied on a circuit board, so that the circuit board includes a substrate and a deformable structure connected to said substrate.
    Type: Grant
    Filed: November 22, 2002
    Date of Patent: June 21, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Salman Akram, Warren M. Farnworth, Alan G. Wood, J. Michael Brooks, Eugene H. Cloud
  • Patent number: 6903938
    Abstract: The invention relates to a printed circuit board comprising capacitive and inductive elements. To arrange such a printed circuit board so that it has a smaller thickness and can be manufactured cost effectively, a printed circuit board is proposed having at least one dielectric layer, on the two side faces of which capacitor electrodes arranged opposite each other are positioned in a first area and two planar windings opposite each other are arranged in at least a second area next to the first area on the side faces of the electric layer.
    Type: Grant
    Filed: August 7, 2002
    Date of Patent: June 7, 2005
    Assignee: Koninklijke Philips Electronics N.V.
    Inventor: Eberhard Waffenschmidt
  • Patent number: 6878884
    Abstract: An electronic device is mounted on a wiring board, which includes: a substrate having through holes, and lands extending on surfaces of the substrate and adjacent to openings of the through holes. Further, at least one coating layer is provided, which coats at least one part of an outer peripheral region of the at least one land, in order to cause that the at least one part is separated from a lead-less solder, thereby preventing any peel of the land from the surface of the substrate.
    Type: Grant
    Filed: April 21, 2003
    Date of Patent: April 12, 2005
    Assignee: NEC Corporation
    Inventor: Yuki Momokawa
  • Patent number: 6851184
    Abstract: A printed circuit board (PCB) and method of forming same is performed without incoming lines for plating. The plating is preferably performed on ball pad areas and/or bonding pad areas being the top layer of a multi-layer PCB. A metal layer that later forms circuit patterns serves to supply a power for plating ball pads for solder-ball bonding and bonding pads for wire-bonding with gold (Au). Thus, the gold (Au)-plating is performed prior to forming the circuit patterns. A positive-type first photoresist is coated on the metal layer to form the ball pads and the bonding pads. The coated first photoresist is also used to form circuit patterns. The gold (Au)-plated metal layer of ball pad areas and the bonding pad areas are protected by a second photoresist, which is reactive with a larger quantity of light than the first photoresist. Both first and second photoresists can be concurrently developed.
    Type: Grant
    Filed: June 20, 2002
    Date of Patent: February 8, 2005
    Assignee: LG Electronics Inc.
    Inventors: Sung Gue Lee, Yong Il Kim, Yong Soon Jang
  • Patent number: 6853086
    Abstract: A method of manufacture of a semiconductor device comprises a step of providing an adhesive (30) between a semiconductor chip (20) and a substrate (10), a step of positioning electrodes (22) and leads (12) to oppose each other, and a step of applying pressure in the direction of making the gap between the semiconductor chip (20) and substrate (10) narrower, and on the substrate (10), in a region opposing the surface of the semiconductor chip (20) and avoiding the leads (12), a film (14) is formed with lower adhesion with the adhesive (30) than the substrate (10).
    Type: Grant
    Filed: October 28, 1999
    Date of Patent: February 8, 2005
    Assignee: Seiko Epson Corporation
    Inventor: Toshiyuki Nakayama
  • Patent number: 6828512
    Abstract: A substrate has at least one via-in-pad that includes a bond pad and a bore. In addition, the substrate has a plug coupled to the at least one via-in-pad, the plug has a first conductive material and adapted to couple with a solder ball having a second conductive material, the first conductive material having a higher reflow temperature than the second conductive material.
    Type: Grant
    Filed: October 8, 2002
    Date of Patent: December 7, 2004
    Assignee: Intel Corporation
    Inventors: C. Key Chung, Sook Chien Chan, Kum Foo Leong
  • Patent number: 6810814
    Abstract: A method and an apparatus for fabricating a pattern which makes it possible to obtain a wide pattern having edges of a preferable shape. The apparatus for fabricating a pattern ejects a liquid material as liquid droplets from an ejecting section, and dispose the liquid droplets on a substrate in a line-shaped pattern. A plurality of line-shaped patterns are formed on the substrate by disposing a plurality of liquid droplets on the substrate in the line-shaped patterns, and then another set of liquid droplets are disposed between the line-shaped patterns so as to integrate the line-shaped patterns with each other.
    Type: Grant
    Filed: April 9, 2003
    Date of Patent: November 2, 2004
    Assignee: Seiko Epson Corporation
    Inventor: Hironori Hasei
  • Patent number: 6809935
    Abstract: A new method is provided for mounting a semiconductor on the surface of a Printed Circuit Board. A layer of Elastomer is deposifed on the surface face of the PCB, this layer of Elastomer makes the PCB into a thermally compliant PCB such that the thermal mismatch between the PCB and the semiconductor die that is mounted on the PCB is sharply reduced. Openings are created in the layer of Elastomer and electrical interfaces are created such that the PCB can be connected to the semiconductor die that is mounted on the PCB.
    Type: Grant
    Filed: October 10, 2000
    Date of Patent: October 26, 2004
    Assignee: Megic Corporation
    Inventor: Jin-Yuan Lee
  • Patent number: 6804122
    Abstract: A terminal body for use in combination with a circuitboard having edge conductor pads and being formed from a stamped metal blank so as to provide a first main longitudinally extending spring contact which is curved back on itself and inwardly toward the center of the terminal and a pair of stabilizing contacts which oppose and straddle the main contact. All of the contacts are sufficiently resilient to permit the circuitboard of thickness T to be inserted between them, the stabilizing contacts ensuring a firm grip on the circuitboard and non-intermittent contact between the main terminal contact and the circuitboard pad.
    Type: Grant
    Filed: August 12, 2003
    Date of Patent: October 12, 2004
    Assignee: Yazaki North America, Inc.
    Inventors: Richard P. Wong, Shashidhar M. Kamath
  • Patent number: 6801437
    Abstract: A method of forming electrically conductive elements on a base layer of an electronic substrate without the use of solder mask. A layer of electrically conductive material is deposited on the base layer, and a first layer of photo imageable ink is applied over the electrically conductive material layer. The first layer of photo imageable ink is patterned to expose portions of the electrically conductive material layer, which are then etched to resolve traces in the electrically conductive material layer. The first layer of photo imageable ink is removed, and a second layer of photo imageable ink is applied over the traces and channels between the traces. The second layer of photo imageable ink is then patterned to expose the traces, and a third layer of photo imageable ink is applied over the traces and the second layer of photo imageable ink. The third layer of photo imageable ink is patterned to expose deposition sites on the traces, within which are formed electrically conductive fingers.
    Type: Grant
    Filed: January 21, 2003
    Date of Patent: October 5, 2004
    Assignee: LSI Logic Corporation
    Inventors: Maurice O. Othieno, Manickam Thavarajah, Severino A. Legaspi, Jr., Pradip D. Patel
  • Publication number: 20040177996
    Abstract: One embodiment of the present invention is a structure useful for testing circuits that includes: (a) a substrate having contactors on a first side and pads on a second side; (b) a card having pads on a first side; and (c) interconnectors that electrically connect the pads on the second side of the substrate with the pads on the card; wherein at least one of the interconnectors includes at least a portion that does not melt at temperatures in a range from about 183° C. to about 230° C., and the distance between the substrate and the card is determined by a dimension of the at least a portion.
    Type: Application
    Filed: April 16, 2003
    Publication date: September 16, 2004
    Applicant: Nexcleon, Inc.
    Inventors: Konstantine N. Karavakis, Tom T. Nguyen