With Specific Connection Material Patents (Class 361/779)
  • Patent number: 6134118
    Abstract: A method and apparatus for producing a multichip package comprising semiconductor chip and a substrate. The semiconductor chip includes conventional inner bond pads that are rerouted to other areas on the chip to facilitate connection with the substrate. The inner bonds are rerouted by covering the chip with a first insulation layer and opening the first insulation layer over the inner bond pads. A metal layer is then disposed over the first insulation layer in contact with the inner bond pads. A second insulation layer is disposed over the metal layer, and the second insulation layer is opened to expose selected portions of the metal layer to form external connection points. Electrically conductive epoxy is then disposed between the external connection points of the semiconductor chip and the terminals of the substrate, thereby electrically connecting the semiconductor chip to the substrate.
    Type: Grant
    Filed: April 3, 1997
    Date of Patent: October 17, 2000
    Assignee: Cubic Memory Inc.
    Inventors: David V. Pedersen, Michael G. Finley, Kenneth M. Sautter
  • Patent number: 6100475
    Abstract: The specification describes techniques for attaching double sided circuit boards having plated through holes to interconnection substrates using solder bump arrays. The through holes are filled with a high melting point solder which allows solder bumps to be located directly on the through hole thus saving board area and reducing the interconnection length.
    Type: Grant
    Filed: April 27, 1998
    Date of Patent: August 8, 2000
    Assignee: Lucent Technologies, Inc.
    Inventors: Yinon Degani, King Lien Tai
  • Patent number: 6088234
    Abstract: The connection structure of a circuit protection element for securely connecting at least two lead terminals of the circuit protection element to a circuit board includes terminal connection elongated holes each provided in the circuit board for connecting the lead terminals to the circuit board by soldering. The circuit board is positioned in such a way that the elongated direction of the elongated terminal connection hole is positioned in a downward direction. When an abnormal current is applied to the circuit, or when the circuit protection element fails to heat itself up to a high temperature, the solder melts. Thereby, the lead terminals easily disengage from the terminal connection holes so that the circuit protection element falls freely from the circuit board. Thus, the circuit is surely cut off easily.
    Type: Grant
    Filed: June 2, 1999
    Date of Patent: July 11, 2000
    Assignee: Yazaki Corporation
    Inventors: Satoshi Ishikawa, Osamu Soda
  • Patent number: 6087597
    Abstract: An electronic device assembly (and method for forming the same) including a first substrate having a first surface, a second surface, and a first pad on the first surface thereof; a second substrate having a first surface, a second surface, and a second pad on the second surface thereof, the first pad facing the second pad; a rigid spherical core interposed between the first and second pads; and solder connecting the first and second pads. The first substrate has a through-hole which is provided through the first substrate at a position of the first pad, at least a part of the solder is positioned in the through-hole and at least a part of the spherical core is received in the through-hole. The through-hole has an inner wall which is continuously tapered from the first surface of the first substrate to the second surface of the first substrate.
    Type: Grant
    Filed: July 24, 1995
    Date of Patent: July 11, 2000
    Assignee: NEC Corporation
    Inventors: Yuzo Shimada, Yoshimasa Tanaka, Shinichi Hasegawa, Takayuki Suyama
  • Patent number: 6088236
    Abstract: A semiconductor unit including a circuit board having terminal electrodes on a surface thereof and a semiconductor device having an electrode pad on a first surface, where the semiconductor device is mounted face down on the surface of the circuit board. The semiconductor device has a plurality of bumps formed on the electrode pad, for electrically connecting the electrode pad to the terminal electrodes of the circuit board. Each bump includes a first bump portion and a smaller second bump portion formed on the first bump portion, and each second bump portion has a plurality of irregularities having concave portions extending in various directions. The bonding layer is formed between the second bump portion and the terminal electrode, and includes conductive particles which along with a portion of the bonding layer enter the concave portions of the plurality of irregularities of the bumps.
    Type: Grant
    Filed: June 18, 1997
    Date of Patent: July 11, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshihiro Tomura, Yoshihiro Bessho
  • Patent number: 6038132
    Abstract: A memory module capable of changing the generation of semiconductor memory devices by changing the design of a unit board without changing the design of a mother board.The mother board has connection terminals having an ability of connecting with first and second generation type unit boards, so that even when a connection terminal location is changed as a result of the generation change of the semiconductor memory devices, the next unit board can be connected to the mother board by selecting an appropriate terminal from connection terminals on the mother board.
    Type: Grant
    Filed: May 7, 1997
    Date of Patent: March 14, 2000
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Muneharu Tokunaga, Takakazu Fukumoto
  • Patent number: 6011313
    Abstract: A device which utilizes flip chip technology to provide interconnection between printed circuit boards and integrated circuits is disclosed. The method involves metallization of the bond pad and multiple, novel bump compositions and coating compositions to provide an interconnection which is reliable and which withstands differences in the coefficient of thermal expansion between the silicon device and the bump material.
    Type: Grant
    Filed: February 1, 1999
    Date of Patent: January 4, 2000
    Assignee: Ford Motor Company
    Inventors: Dongkai Shangguan, Mohan Paruchuri, Achyuta Achari
  • Patent number: 5973932
    Abstract: A printed circuit assembly comprises a module with a component secured to a pad on a dielectric substrate using a tin-free metal composition. A terminal of the module is coupled to a second printed circuit board with a solder composition of at least approximately 40% tin. The tin-free solder composition may comprise approximately 90% lead and 10% antimony.
    Type: Grant
    Filed: February 14, 1997
    Date of Patent: October 26, 1999
    Assignee: Pulse Engineering, Inc.
    Inventor: Tuan D. Nguyen
  • Patent number: 5962815
    Abstract: A multilayered structure, such as a printed circuit board, includes a first conductive layer and a second conductive layer that are separated from each other by a dielectric layer. The dielectric layer is formed of a first material, such as a photoimagible polyimide and epoxy resin. The dielectric layer has a number of via holes that extend from the first conductive layer to the second conductive layer. The via holes are filled with a second material having a breakdown voltage less than a breakdown voltage of the first material included in the dielectric layer to form an antifuse. The second material in the via holes can be, for example, a conductive epoxy resin or a polymer loaded with conductive particles (also referred to as "conductive paste").
    Type: Grant
    Filed: January 18, 1995
    Date of Patent: October 5, 1999
    Assignee: Prolinx Labs Corporation
    Inventors: James J. D. Lan, Steve S. Chiang, William H. Shepherd, Paul Y. F. Wu
  • Patent number: 5943212
    Abstract: Thermal stress caused by a difference in the coefficient of thermal expansion between the mounting substrate and the ceramic substrate acts little on the junction portions of the external connection terminals when a semiconductor device is mounted avoiding such problems that the junction portions are broken or peeled off the mounting substrate.
    Type: Grant
    Filed: April 30, 1997
    Date of Patent: August 24, 1999
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Michio Horiuchi, Shigetsugu Muramatsu, Ryuichi Matsuki
  • Patent number: 5936848
    Abstract: An electronics package includes a substrate, a via and a solder ball. The substrate has first and second opposed surfaces. The via is located within the substrate and terminates at the first surface. The via defines an opening having first and second opposed walls. The solder ball is at least partially located over the opening. The solder ball has first and second opposed sides, the first side being adjacent the first wall and the second side being adjacent the second wall. The first side is nearer to the first wall than the second side is to the second wall.
    Type: Grant
    Filed: May 29, 1998
    Date of Patent: August 10, 1999
    Assignee: Intel Corporation
    Inventors: Behrooz Mehr, Tony Kean-Lee Lim, Agnes Seok-Tuan Lim, Michael Barrow
  • Patent number: 5925445
    Abstract: The present invention provides a printed wiring board on which a bear chip is bonded in face-down. The printed wiring board has wiring patterns extending over the printed wiring board, wherein a plurality of wirings are provided which extend radially and outwardly from a center area of the printed wiring board, and wherein each of the wirings comprises at least a bear chip mounting pad region for contacting bumps of the bear chip, at least an external wiring pad region for connecting to an external wiring, and at least a covered region being covered by at least an insulation layer and the covered region separating between the bear chip mounting pad region and the external wiring pad region and a sealing material is filled within a space defined between the printed wiring board and the bear chip.
    Type: Grant
    Filed: July 14, 1997
    Date of Patent: July 20, 1999
    Assignee: NEC Corporation
    Inventor: Motoji Suzuki
  • Patent number: 5923535
    Abstract: An electronic device assembly includes a rigid, first substrate and a second substrate. The first substrate has a first pad on the upper surface, and a through-hole at a position of the first pad. The second substrate has a second pad on the upper surface thereof. The first and second pads are connected via solder. At least a part of the solder is positioned in the through-hole of the first substrate. The first substrate may include a flexible substrate and a rigid plate. The through-hole is provided in the flexible substrate. The first pad is provided on the lower surface of the flexible substrate. The rigid plate is attached to the flexible substrate. The plate has a hole at a position of the through-hole to make the first pad reachable.
    Type: Grant
    Filed: October 28, 1997
    Date of Patent: July 13, 1999
    Assignee: NEC Corporation
    Inventors: Yuzo Shimada, Takayuki Suyama, Shinichi Hasegawa
  • Patent number: 5920464
    Abstract: A reworkable cold welded microelectronic multi-chip module contains cold welded microelectronic chips in which the chip's cold weld metal bonding pads (3) are constructed of a metal having one hardness and the corresponding cold weld metal bonding pads of the multi-chip module's substrate (5) are of a different greater hardness, which, despite the difference in hardness, cold weld to one another. Two forms of Indium preferably serve as the metals. If for any reason the chip must be removed from the module, it is found that the cold weld breaks at a predictable location. A new microelectronic chip may thereby be cold welded to the module substrate as a replacement. New rework and testing procedures are thereby made possible.
    Type: Grant
    Filed: September 22, 1997
    Date of Patent: July 6, 1999
    Assignee: TRW Inc.
    Inventors: Karen E. Yokoyama, Gershon Akerling
  • Patent number: 5917156
    Abstract: Copper electrodes are formed on a circuit board to be bonded with leads of a TAB driving liquid crystal. A pre-deposit solder receiver having solder printed thereon is also provided on the circuit board in alignment with and prior to an electrode to be first bonded with a lead, to form a sufficient solder pool between plural electrodes and a bottom wall of a soldering iron. Solder/bonding is accordingly realized efficiently even from a starting electrode E1. Also, an excessive solder receiver may be provided in alignment with and after an electrode to be last bonded with a lead.
    Type: Grant
    Filed: August 29, 1995
    Date of Patent: June 29, 1999
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kazuhiro Nobori, Kazuto Nishida, Norihito Tsukahara
  • Patent number: 5917707
    Abstract: An interconnection contact structure assembly including an electronic component having a surface and a conductive contact carried by the electronic component and accessible at the surface. The contact structure includes an internal flexible elongate member having first and second ends and with the first end forming a first intimate bond to the surface of said conductive contact terminal without the use of a separate bonding material. An electrically conductive shell is provided and is formed of at least one layer of a conductive material enveloping the elongate member and forming a second intimate bond with at least a portion of the conductive contact terminal immediately adjacent the first intimate bond.
    Type: Grant
    Filed: November 15, 1994
    Date of Patent: June 29, 1999
    Assignee: FormFactor, Inc.
    Inventors: Igor Y. Khandros, Gaetan L. Mathieu
  • Patent number: 5912507
    Abstract: A microelectronic assembly, such as a surface-mount device or a ball-grid array (BGA) package, has one or more integral resistors. The integral resistors are incorporated into one or more of the microelectronic assembly's electrical leads or connections. The integral resistors preferably terminate in a solderable pad. For example, the BGA package may include an IC chip and interposer. A terminal is located on a surface of the IC chip, on a surface of the interposer, or on the surface of the substrate to which the BGA is mounted. An electrically-resistive material overlies the terminal and electrically couples the terminal to a bond pad, thereby defining an integral resistor. The integral resistors reduce electrical resonances and reflections that may otherwise degrade the signal integrity and reliability of the electrical system employing the device; hence, reduce or eliminate the requirement for discrete resistors for the microelectronic assembly.
    Type: Grant
    Filed: February 4, 1998
    Date of Patent: June 15, 1999
    Assignee: Motorola, Inc.
    Inventors: Gregory J. Dunn, Lawrence E. Lach, Daniel R. Gamota
  • Patent number: 5889655
    Abstract: A substrate for an integrated circuit package. Located on a bottom surface of the substrate are a plurality of contact pads. Solder balls are attached to the contact pads and then reflowed to mount the package to a printed circuit board. The bottom surface of the substrate has a first layer of solder mask. The first layer has a plurality of first openings which expose at least a portion of each contact pad. Adjacent to the first layer of solder mask is a second layer of solder mask which has a plurality of second openings that also expose the contact pads. The diameter of each second opening is larger than the diameter of each first opening. The openings may be created by etching the layers of solder mask. The etching process typically creates in annular lips in the solder mask openings. The larger second openings reduce the stress risers of the solder balls created by the inner lips of the solder mask.
    Type: Grant
    Filed: November 26, 1997
    Date of Patent: March 30, 1999
    Assignee: Intel Corporation
    Inventor: Michael Barrow
  • Patent number: 5886878
    Abstract: The present application describes a through-hole component insulator and assembly process which has the advantages of preventing solder from contacting the metal case of a through-hole component without an addition step or additional material from the standard fabrication process for a printed circuit board. The printed circuit board of the present invention includes a printed ink spacer disposed beneath the through-hole component wherein the printed ink spacer is included with a standard silk-screen artwork layer in the printed circuit board design stage. The printed ink spacer raises the through-hole component from the printed circuit board surface to prevent solder from contacting the metal case of the through-hole component during the printed circuit board soldering stage. Using a silk-screen artwork layer which includes at least one printed ink spacer in the artwork, the printed ink spacer is deposited during deposition of a standard printed design on the printed circuit board fabrication.
    Type: Grant
    Filed: January 21, 1997
    Date of Patent: March 23, 1999
    Assignee: Dell USA, L.P.
    Inventors: Gita P. Khadem, Darrell J. Slupek
  • Patent number: 5870289
    Abstract: A structure for connecting an integrated circuit chip to a wiring substrate which implements high-density packaging, high-density connection, high-speed signal transmission, and low cost. An integrated circuit is connected to a wiring substrate by means of flip-chip die bonding using an adhesive film. A direct through-hole connection is formed directly below a connecting pad so as to pass through the adhesive film and the wiring substrate. This direct through-hole connection directly connects the connecting pad to the wire. As a result of reduced area and thickness of the chip, the chip is mounted in high density, and high-density inputs and outputs are implemented by means of minute two-dimensional connections. Short wire connections directly connected to the chip permit high speed signal transmission, and high reliability is ensured by the dispersion of stress. Low-cost packaging can be effected by simple processes and facilities.
    Type: Grant
    Filed: December 14, 1995
    Date of Patent: February 9, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Masahide Tokuda, Takeshi Kato, Hiroyuki Itoh, Masayoshi Yagyu, Yuuji Fujita, Mitsuo Usami
  • Patent number: 5847326
    Abstract: A low-temperature fired ceramic circuit substrate includes a plurality of laminated insulating layers each formed of a low-temperature fired ceramic fired at a temperature ranging between 800 and 1,000.degree. C., an inside layer wiring conductor formed of a conductive material of Ag system which is mainly composed of Ag, the inside layer wiring conductor being disposed in the inside insulating layer, a surface layer wiring conductor formed of a conductive material of Au system which is mainly composed of Au, the surface layer wiring conductor being disposed on the surface insulating layer, and an intermediate metal layer formed of a thick film paste of a conductive material of Au/Ag system which is mainly composed of Au/Ag, the intermediate metal layer being interposed between the inside layer wiring conductor and the surface layer wiring conductor.
    Type: Grant
    Filed: March 3, 1997
    Date of Patent: December 8, 1998
    Assignee: Sumitomo Metal Electronics Devices Inc.
    Inventors: Katsuya Kawakami, Junzo Fukuta
  • Patent number: 5847938
    Abstract: A shield including a cover and pins is inserted in a solder-free connection into an electronic substrate for shielding electronic components on the substrate in an electronic device. The shield has a conductive cover, preferably with an integrally formed roof and wall, which defines a cavity. The cavity is configured to receive an electronic component or components positioned therein. The shield also has a conductive mounting pins which extend from the cover. The cover and the pins are preferably formed as a single piece. The shield also preferably includes a conductive gasket connected in a groove in the cover between the cover and the electronic substrate. Methods of assembling the shield on an electronic substrate in forming an electronic package for an electronic device are also provided.
    Type: Grant
    Filed: December 20, 1996
    Date of Patent: December 8, 1998
    Assignee: Ericsson Inc.
    Inventor: John Weldon Gammon
  • Patent number: 5843567
    Abstract: There is disclosed an electrical component having an axial direction and two ends for making electrical contact with another component comprising a plurality of electrically conductive fibers in a matrix, the plurality of the fibers being oriented in the matrix in a direction substantially parallel in the axial direction of the component and being continuous from one end of the component to the other end to provide a plurality of electrical point contacts at each end of the component, wherein the component further includes magnetic particles.
    Type: Grant
    Filed: June 3, 1997
    Date of Patent: December 1, 1998
    Assignee: Xerox Corporation
    Inventors: Joseph A. Swift, Ronald F. Ziolo, Stanley J. Wallace
  • Patent number: 5844782
    Abstract: A printed wiring board and an electronic device using the same with which the formation of cracks in base portions of projecting external electrodes formed on lands on the printed wiring,board is certainly prevented. With respect to a printed wiring board 11 having lands 16 formed in a wiring pattern where external electrodes 13 are to be formed and a pattern-protecting film 17 having openings 17a where the external electrodes 13 are to be formed, the opening diameter D1 of the openings 17a in the pattern-protecting film 17 is set greater by a predetermined dimension than the external diameter D2 of the lands 16 and a gap is thereby provided between each of the external electrodes 13 and the pattern-protecting film 17 so that the external electrodes 13 and the pattern-protecting film 17 do not make contact with each other and as a result there is no cracking of the external electrodes 13 caused by differential thermal expansion of the external electrodes 13 and the pattern-protecting film 17.
    Type: Grant
    Filed: March 29, 1996
    Date of Patent: December 1, 1998
    Assignee: Sony Corporation
    Inventor: Hiroyuki Fukasawa
  • Patent number: 5839190
    Abstract: Methods for making a printed wiring device including a substrate having a metal-plateable member and an electrical component having a metal plateable lead connected with the metal-plateable member, the lead and the member being electrically interconnected by a metal layer plated on the lead and on the member and forming an electrically conductive path between the lead and the member.
    Type: Grant
    Filed: October 10, 1996
    Date of Patent: November 24, 1998
    Inventor: Kenneth W. Sullivan
  • Patent number: 5822191
    Abstract: There is provided a highly reliable panel assembly structure capable of performing fine-pitch high-density assembling at a high yield and a low cost. A flexible wiring board has a film-like substrate with flexibility, and an IC chip is mounted in an area. In the area is provided a through hole that has plane dimensions smaller than plane dimensions of the chip and penetrates the substrate. Portions that belong respectively to an output side wiring line and an input side wiring line provided on a substrate surface and are connected respectively to an output side electrode and an input side electrode of the chip via second connection materials and are supported by the substrate surface. An output terminal of the flexible wiring board is connected to an electrode terminal formed at a peripheral portion of a panel via a first connection material, while an input terminal of the flexible wiring board is connected to an electrode terminal of a circuit board via a third connection material.
    Type: Grant
    Filed: May 27, 1997
    Date of Patent: October 13, 1998
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yasunobu Tagusa, Shigeo Nakabu
  • Patent number: 5818697
    Abstract: An electronic package is provided that includes a flexible polyimide film carrier having electronic circuitry on both of its major surfaces and a plurality of solder interconnection pads on a first major surface; solder mask layers located on both major surfaces, provided that areas between subsequently to be applied individual circuit chips on the first major surface exist that are free from the solder mask; and a plurality of modules attached to the film carrier by the solder balls or bumps. Also provided is a method for fabricating the electronic package that includes reflow of the solder balls or bumps to achieve attachment of the modules.
    Type: Grant
    Filed: March 21, 1997
    Date of Patent: October 6, 1998
    Assignee: International Business Machines Corporation
    Inventors: Gregg Joseph Armezzani, Robert Nicholas Ives, Mark Vincent Pierson, Terry Alan Tull
  • Patent number: 5812379
    Abstract: A solder joint interface which includes a plurality of solder balls that attach an integrated circuit package to corresponding pads of a printed circuit board. The solder pads are on a 0.05 inch pitch and have a diameter of 0.02 inches so that two 0.006 inch routing traces can be routed between adjacent pads of the circuit board. The additional routing traces allow the solder pads to be arranged in a pattern that has five rows of solder pads. The solder balls have pre-assembled diameters of 0.030 inches and a final height of 0.02 inches. The relatively tall solder joints function as structural beams that undergo both shear and moment stresses when an external load is applied to the joints. The moment component produces lower solder stresses and improves the structural integrity of the solder joints.
    Type: Grant
    Filed: August 13, 1996
    Date of Patent: September 22, 1998
    Assignee: Intel Corporation
    Inventor: Michael Barrow
  • Patent number: 5808874
    Abstract: A microelectronic assembly including elements such as a semiconductor chip and substrate has electrical connections between the elements incorporating fusible conductive metal masses. The fusible masses are surrounded and contained by a compliant material such as an elastomer or gel. The fusible material may melt during operation or processing of the device to relieve thermal cycling stress in the electrical connections.
    Type: Grant
    Filed: May 2, 1996
    Date of Patent: September 15, 1998
    Assignee: Tessera, Inc.
    Inventor: John W. Smith
  • Patent number: 5796589
    Abstract: A ball grid array (BGA) integrated circuit package which has a plurality of vias located within the solder pads of a package substrate. The substrate supports an integrated circuit which is connected to the solder pads by the vias. Solder balls used to solder the package to an external printed circuit board are attached to the solder pads of the substrate. A solder mask plug is formed within the vias to prevent the solder balls from wicking into the vias. Locating the vias within the solder pads optimizes the routing space of the substrate and increases the routing density of the package.
    Type: Grant
    Filed: December 20, 1995
    Date of Patent: August 18, 1998
    Assignee: Intel Corporation
    Inventor: Michael Barrow
  • Patent number: 5796591
    Abstract: A structure and a method is disclosed for making a laminated circuit carrier card for the purpose of making a Direct Chip Attached Module (DCAM) with low cost and high reliability. The carrier is made using an organic or an inorganic laminated carrier having at least one surface available for direct chip mount. The chip has at least one solder ball with a cap of low melting point metal. The surface of the carrier has electrical features that are directly connected to the low melting point metal on the solder ball of the chip to form the eutectic and this way the chip is directly attached to the carrier.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: August 18, 1998
    Assignee: International Business Machines Corporation
    Inventors: Hormazdyar Minocher Dalal, Kenneth Michael Fallon
  • Patent number: 5796590
    Abstract: An apparatus and method for surface-mounting ball grid array integrated circuit (IC) devices to printed circuit boards. A thin single- or multi-layer sheet of nonconductive material having a plurality of apertures corresponding to the leads of the IC device to be mounted is interposed between the ball grid array and the circuit board prior to solder processing to facilitate solder application, device alignment, and solder retention. An assembly guide is located on the top surface of the aid to assist in the orientation and placement of the IC device during assembly. In a further aspect, the disclosed assembly aid helps compensate for non-planarity in the IC device array or circuit board, and maintains a minimum standoff distance between the IC package and the circuit board to preclude undue solder joint deformation. The assembly aid also allows for reworking of the surface mount by facilitating localized placement of the solder prior to reflow processing without masking or other additional processing steps.
    Type: Grant
    Filed: November 5, 1996
    Date of Patent: August 18, 1998
    Assignee: Micron Electronics, Inc.
    Inventor: Dean A. Klein
  • Patent number: 5790384
    Abstract: A chip package includes a substrate formed from a first die and its attendant wiring interconnections, having a first thermal coefficient of expansion. The first die includes primary input/output (I/O) interconnections for the chip package. Also provided is a second die that includes escape wiring formed on that die and coupled to the primary I/O interconnections through the first die. The second die has a second thermal coefficient of expansion similar to the first thermal coefficient of expansion. The chip package also includes connectors that couple the primary I/O interconnections of the first die to a second level package. An interposer may be provided to couple the primary I/O interconnections to the second level package. The second die is smaller than the first die. The peripheral area of the first die is left exposed when the second die is coupled to the first die so that sufficient I/O interconnections may be formed for the primary I/O interconnections on the first die.
    Type: Grant
    Filed: June 26, 1997
    Date of Patent: August 4, 1998
    Assignee: International Business Machines Corporation
    Inventors: Umar M. Ahmad, Eugene R. Atwood
  • Patent number: 5777851
    Abstract: A circuit board including a resin layer and a wiring structure buried in the resin layer for forming an electric circuit. In the circuit board, the wiring structure is provided with a connecting part for soldering a first electrical part. The wiring structure is provided with a connecting hole for connecting a second electrical part by inserting a fastening member, and the connecting part is positioned on a surface of the resin layer.
    Type: Grant
    Filed: January 3, 1996
    Date of Patent: July 7, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Osamu Yamamoto
  • Patent number: 5774341
    Abstract: A solderless electrical interconnection is made using electrically conductive hook fasteners (15) that are embedded in a substrate (12). The upper part (20) of the fastener is exposed on the top side of the substrate, the central part (22) is embedded within the substrate itself, and the lower or hook portion (17) of the fastener protrudes from the bottom side of the substrate. Electrically conductive pathways (30), defined on the top side of the substrate, make contact with the exposed upper part of the hook fastener. The electrically conductive runners on the top side have a continuous signal path through the substrate to the bottom side of the substrate via the electrically conductive hook fastener. The hook fastener (15) is engaged to electrically conductive loop fasteners (60) on a second substrate (70) in order to create a solderless electrical interconnection and mechanical interlocking between the two substrates.
    Type: Grant
    Filed: December 20, 1995
    Date of Patent: June 30, 1998
    Assignee: Motorola, Inc.
    Inventors: Glenn F. Urbish, Robert W. Pennisi, William Boone Mullen, III, Dale W. Dorinski
  • Patent number: 5771157
    Abstract: A printed circuit board carries a microcircuit package electrically connected to bare copper connector pads on the printed circuit board microcircuit package by aluminum wires. The copper connection pads are encapsulated by a material such as low stress liquid encapsulant having a thermal expansion coefficient approximately equal to that of the printed circuit board substrate material. Preferably the printed circuit board laminate comprises cellulose epoxy mat such as CEM-1.
    Type: Grant
    Filed: March 8, 1996
    Date of Patent: June 23, 1998
    Assignee: Honeywell, Inc.
    Inventor: Robert L. Zak
  • Patent number: 5764488
    Abstract: A printed circuit board having a footprint that is capable of receiving one of two electronic components having differing pin configurations. The footprint includes a first and a second common pin receptor arranged about a first axis. The first and second common pin receptors are configured to receive a first and a second pin on either of the electronic components. The footprint also includes a third pin receptor that is positioned along the first axis so as to be interposed between the first and the second common pin receptors and is configured to receive a third pin receptor of the first electronic component. The footprint also includes a fourth pin receptor that is positioned along a second axis, that is orthogonal to and intersects the first axis at the location of the third pin receptor. The fourth pin receptor is configured to receive a third pin of the second electronic component.
    Type: Grant
    Filed: June 11, 1996
    Date of Patent: June 9, 1998
    Assignee: AST Research, Inc.
    Inventors: David J. Silva, Mitchell G. Dorfmeyer
  • Patent number: 5748450
    Abstract: In a BGA package having electrically connected active balls and electrically disconnected dummy balls, the active balls are positioned in a radial direction at intervals of 90.degree. around the dummy balls. When a defect occurs in a solder joint, the package can be easily repaired by finding defective active ball; forming a repair hole by using a cutting means at a predetermined portion of the printed circuit board corresponding to a central position between the dummy ball and the defectively soldered active ball; inserting a solder paste injector into the repair hole to inject solder thereinto; and mutually connecting pad extensions of the dummy ball and the defective active ball with the injected solder. Therefore, the overall process can be simplified and its reliability can be improved.
    Type: Grant
    Filed: April 23, 1996
    Date of Patent: May 5, 1998
    Assignee: LG Semicon Co., Ltd.
    Inventors: Young-Gon Kim, Dong-You Kim
  • Patent number: 5742483
    Abstract: Where an electrical connection is needed between an electric circuit on a substrate and a component with very finely spaced leads, pads are formed on the substrate at points where such connections to the circuit are to be made. A solder paste is deposited using a particular, described stencil having a thickness and apertures with specific tolerances. The component is positioned so that its leads to be attached are contiguous with corresponding pads, and the electrical connections are completed by reflowing the solder paste forming consistent and reliable electrical joints of solder alloy.
    Type: Grant
    Filed: April 10, 1996
    Date of Patent: April 21, 1998
    Assignee: International Business Machines Corporation
    Inventors: Bao-Tong Ma, Amit Kumar Sarkhel, Ping Kwong Seto
  • Patent number: 5737191
    Abstract: A semiconductor chip mount structure includes a substrate having a base surface on which base side connectors are formed; a semiconductor chip mounted on the base surface, the semiconductor chip having chip side connectors on a first surface thereof facing the base surface, the chip side connectors being electrically connected to the base side connectors; an insulating resin layer covering the chip side connectors and the base side connectors; a metal layer, made of a metal having a melting point lower than a temperature at which the electrical components of the semiconductor chip may be thermally destroyed, for covering the semiconductor chip and the insulating resin layer; and a wetting characteristic improving layer such as a metal powder or foil layer, formed along a contact surface between the metal layer and the insulation resin layer.
    Type: Grant
    Filed: April 5, 1996
    Date of Patent: April 7, 1998
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Michio Horiuchi, Yoichi Harayama
  • Patent number: 5729437
    Abstract: A leadless package type electronic part, the cost and the size of which can be reduced and which exhibits excellent reliability, and an electronic part material for manufacturing the electronic parts. The electronic part of a leadless package type includes a rectangular substrate having a plurality of external electrodes in the periphery thereof, an element part placed on the surface of the substrate while being electrically connected to the external electrodes, and molding resin for molding the element part onto the surface of the substrate, wherein the surface of the molding resin is formed to be flat, and each side surface of the molding resin is flush, or aligned, with a respective side surface of the substrate.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: March 17, 1998
    Assignee: Seiko Epson Corporation
    Inventor: Nobuaki Hashimoto
  • Patent number: 5729440
    Abstract: The method for soldering a chip to a substrate to form a module and then soldering the module to a circuit board includes selecting a three level hierarchy of solders by the temperature required to melt. By this method, a module can be soldered to and de-soldered from a circuit board without affecting adversely the solder between the chip and the substrate. The package formed by this method is free of faults that are caused frequently during both manufacture and service.
    Type: Grant
    Filed: January 16, 1997
    Date of Patent: March 17, 1998
    Assignee: International Business Machines Corporation
    Inventors: Miguel Angel Jimarez, Amit Kumar Sarkhel, Lawrence Harold White
  • Patent number: 5726861
    Abstract: A method and structure for controlling solder height of a surface mount device on a substrate uses electrical connection pads (105, 105') disposed onto a substrate (101). A height control pad (111) is also disposed onto the substrate (101) positioned apart from the electrical connection pads (105, 105'). Solder fillets (107, 107', 113) are disposed onto both the electrical connection pads (105, 105') and the height control pad (111). A component (103) having an electrical termination portion (109, 109') in contact with the solder fillets (107, 107') associated with the electrical connection pads (105, 105 ') and a body portion (115) in contact with the solder fillet (113) associated with the height control pad (111).
    Type: Grant
    Filed: January 3, 1995
    Date of Patent: March 10, 1998
    Inventor: Fred E. Ostrem
  • Patent number: 5714252
    Abstract: The present invention relates to a deformable substrate assembly for microelectronic components which includes an array of ductile metal circuit traces on a surface thereof. When an electronic component is adhesively bonded to the substrate assembly, and bonding elements from the component contact the traces, the substrate has material properties which allow individual bonding elements to locally deform the traces until the traces penetrate into the substrate surface.
    Type: Grant
    Filed: January 2, 1997
    Date of Patent: February 3, 1998
    Assignee: Minnesota Mining and Manufacturing Company
    Inventors: Peter B. Hogerton, Kenneth E. Carlson
  • Patent number: 5699609
    Abstract: A fixture is provided for facilitating the fabrication of a motor controller of the type including a power substrate module and a control circuit board mounted to and electrically coupled to the power substrate module via a plurality of conductors. The fixture is preferably a ring-like structure made of epoxy-fiberglass laminate. Apertures for engaging and holding the conductors are provided in the fixture at locations corresponding to conducting pads on the power substrate module. For fabrication, the power substrate module and the fixture are preformed and solder is disposed on the conducting pads of the module. During fabrication, the conductors are inserted into the apertures in the fixture and the fixture and conductors are positioned over the preformed power substrate module to bring the conductors into contact with the conducting pads. The fixture and power substrate module are then passed through a reflow oven to melt the solder and complete the connection of the conductors to the module.
    Type: Grant
    Filed: April 12, 1995
    Date of Patent: December 23, 1997
    Assignee: Allen-Bradley Company, Inc.
    Inventor: Christopher J. Wieloch
  • Patent number: 5700987
    Abstract: A method for aligning and soldering a first device (11) to a substrate (16) comprises the steps of providing a plurality of solder elements (17) between the first device and the substrate, aligning the first device, and then reflowing and cooling the solder elements to bond the first device to the substrate. The improvement comprises, first, reflowing only a first group of solder elements and then cooling the elements of the first group, thereby to tack the first device to the substrate. Thereafter, we reflow only a second group of the plurality of solder elements and cool the second group, thereby to provide a more secure bond between the device and the substrate without interfering with the alignment of the first device. This method reduces the amount of energy needed for each fellow step, thereby reducing stresses and maintaining better alignment.
    Type: Grant
    Filed: March 15, 1996
    Date of Patent: December 23, 1997
    Assignee: Lucent Technologies Inc.
    Inventor: Nagesh Ramamoorthy Basavanhally
  • Patent number: 5668700
    Abstract: There is provided a highly reliable panel assembly structure capable of performing fine-pitch high-density assembling at a high yield and a low cost. A flexible wiring board has a film-like substrate with flexibility, and an IC chip is mounted in an area. In the area is provided a through hole that has plane dimensions smaller than plane dimensions of the chip and penetrates the substrate. Portions that belong respectively to an output side wiring line and an input side wiring line provided on a substrate surface and are connected respectively to an output side electrode and an input side electrode of the chip via second connection materials and are supported by the substrate surface. An output terminal of the flexible wiring board is connected to an electrode terminal formed at a peripheral portion of a panel via a first connection material, while an input terminal of the flexible wiring board is connected to an electrode terminal of a circuit board via a third connection material.
    Type: Grant
    Filed: July 24, 1995
    Date of Patent: September 16, 1997
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yasunobu Tagusa, Shigeo Nakabu
  • Patent number: 5657208
    Abstract: A hybrid printed circuit board comprising two substrates having different thermal coefficients of expansion can be manufactured using automated surface mount techniques. A daughterboard is configured with a number of contact pads on the bottom. A motherboard is configured with an aligned set of contact pads on the top with solder compound stenciled on them. The daughterboard is attached to the motherboard using standard automated surface mount techniques.
    Type: Grant
    Filed: July 28, 1995
    Date of Patent: August 12, 1997
    Assignee: Hewlett-Packard Company
    Inventors: Terry Noe, Leonard Weber
  • Patent number: 5657206
    Abstract: A method and apparatus for producing a multichip package comprising semiconductor chip and a substrate. The semiconductor chip includes conventional inner bond pads that are rerouted to other areas on the chip to facilitate connection with the substrate. The inner bonds are rerouted by covering the chip with a first insulation layer and opening the first insulation layer over the inner bond pads. A metal layer is then disposed over the first insulation layer in contact with the inner bond pads. A second insulation layer is disposed over the metal layer, and the second insulation layer is opened to expose selected portions of the metal layer to form external connection points. Electrically conductive epoxy is then disposed between the external connection points of the semiconductor chip and the terminals of the substrate, thereby electrically connecting the semiconductor chip to the substrate.
    Type: Grant
    Filed: January 19, 1995
    Date of Patent: August 12, 1997
    Assignee: Cubic Memory, Inc.
    Inventors: David V. Pedersen, Michael G. Finley, Kenneth M. Sautter
  • Patent number: 5650919
    Abstract: An apparatus, comprising a first member, including two conductive paths, a conductive adhesive, a second member, including two conductive paths, each of the two conductive paths of the second member being connected to a corresponding one of the two conductive paths of the first member via the conductive adhesive, to form two electrical connections, and a peak-shaped dielectric dam, formed on the second member between the two electrical connections.
    Type: Grant
    Filed: February 21, 1996
    Date of Patent: July 22, 1997
    Assignees: Zymet, Inc., Samsung Display Devices Co., Ltd.
    Inventors: Karl I. Loh, Chang Hoon Lee