Abstract: A one time programming (OTP) memory cell includes a first transistor and a second transistor. The first transistor has a first drain, a first source, a first gate, and a first normal operational voltage value higher that a second normal operational voltage value of the second transistor. The second transistor has a second drain, a second source, and a second gate. The first source is coupled to the second drain. The second source is configured to detect data stored in the OTP memory cell.

Abstract: Disclosed are a unit cell capable of improving a reliability by enhancing a data sensing margin in a read operation, and a nonvolatile memory device with the same. The unit cell of a nonvolatile memory device includes: an antifuse having a first terminal between an input terminal and an output terminal; and a first switching unit coupled between a second terminal of the antifuse and a ground voltage terminal.

Abstract: In a semiconductor device including a memory cell array formed of memory cells using a storage element by a variable resistor and a select transistor, a buffer cell is arranged between a sense amplifier and the memory cell array and between a word driver and the memory cell array. The resistive storage element in the memory cell is connected to a bit-line via a contact formed above the resistive storage element. Meanwhile, in the buffer cell, the contact is not formed above the resistive storage element, and a state of being covered with an insulator is kept upon processing the contact in the memory cell. By such a processing method, exposure and sublimation of a chalcogenide film used in the resistive storage element can be avoided.

Abstract: Embodiments provide improved memory bitcells, memory arrays, and memory architectures. In an embodiment, a memory cell comprises a transistor having drain, source, and gate terminals; and a plurality of program nodes, with each of the program nodes charged to a pre-determined voltage and coupled to a respective one of a plurality of bit lines.

Abstract: An object is reduction in power consumption of a semiconductor device including a memory circuit. In the semiconductor device including a memory circuit, the memory circuit includes a memory cell including a semiconductor element and a memory cell that does not include a semiconductor element in a region defined by a word line and a bit line which intersect with each other. A transistor formed using an oxide semiconductor so as to have extremely low off-state current is used as the semiconductor element, so that the reading precision is improved and thus low voltage operation can be performed. The memory cells store data high or data low. The memory cell comprising a semiconductor element stores minor data of high and low, and the memory cell that does not comprise the semiconductor element stores major data of high and low.

Abstract: Various circuits include MOS transistors that have a bulk voltage terminal for receiving a bulk voltage that is different from a supply voltage and ground. The bulk voltage may be selectively set so that some MOS transistors have a bulk voltage set to the supply voltage or ground and other MOS transistors have a bulk voltage that is different. The bulk voltage may be set to forward or reverse bias pn junctions in the MOS transistor. The various circuits include comparators, operational amplifiers, sensing circuits, decoding circuits and the other circuits. The circuits may be included in a memory system.

Abstract: A semiconductor device comprises a memory cell including a capacitor and a select transistor with a floating body structure, a bit line connected to the select transistor, a bit line control circuit, and a sense amplifier amplifying a signal read out from the memory cell. The bit line control circuit sets the bit line to a first potential during a non-access period of the memory cell, and thereafter sets the bit line to a second potential during an access period of the memory cell. Thereby, the data retention time can be prolonged by reducing leak current at a data storage node of the memory cell so that an average consumption current for the data retention can be reduced.

Abstract: In one embodiment, a bit-line interface is disclosed. The bit-line interface has a multiplexer having a plurality of bit-line outputs, and a write path coupled to a multiplexer signal input. The bit-line interface also has a read path coupled to the multiplexer signal input, wherein the read path and the write path share at least one component.

Abstract: To provide a semiconductor memory device including an oxide semiconductor that can deal with instability of a threshold characteristic, in which writing is possible by a simple method. The semiconductor memory device functions by utilizing a characteristic that a threshold shifts when a thin film transistor including an oxide semiconductor is irradiated with ultraviolet light. Readout can be performed by setting a readout voltage between the threshold before the ultraviolet light irradiation and the threshold after irradiation. The threshold characteristic of an initial characteristic can be controlled by providing a back gate or by using two thin film transistors.

Abstract: A circuit includes a fuse and a sensing and control circuit. The fuse is coupled between a MOS transistor and a current source node. The sensing and control circuit is configured to receive a programming pulse and output a modified programming signal to the gate of the MOS transistor for programming the fuse. The modified programming signal has a pulse width based on a magnitude of a current through the first fuse.

Abstract: A method of generating a ROM bit cell array layout including the steps of: inputting a predetermined memory architecture having a predetermined positioning of bit lines and virtual ground lines, the memory architecture including a plurality of columns of memory cells, each column of memory cells being located between associated bit lines and virtual ground lines. Adjacent memory cells in each column of memory cells share a common connection to either the associated bit line or the associated virtual ground line. The further steps of evaluating the width of active area of each of said columns of memory cells, in dependence on said predetermined positioning of bit lines and virtual ground lines; selecting a final width of active area in dependence on at least one performance characteristic associated with said final width of active area; and generating the layout according to said final width of active area.

Abstract: According to one exemplary embodiment, a one-time programmable memory cell includes an access transistor coupled to a shiftable threshold voltage transistor between a bitline and a ground, where the access transistor has a gate coupled to a wordline. The shiftable threshold voltage transistor has a drain and a gate shorted together. A programming operation causes a permanent shift in a threshold voltage of the shiftable threshold voltage transistor to occur in response to a programming voltage on the bitline and the wordline. In one embodiment, the access transistor is an NFET while the shiftable threshold voltage transistor is a PFET. In another embodiment, the access transistor is an NFET and the shiftable threshold voltage transistor is also an NFET. The programming voltage can cause an absolute value of the threshold voltage to permanently increase by at least 50.0 millivolts.

Abstract: A semiconductor device with OTP memory cell includes a first switching unit for transferring a first bias voltage, a first MOS transistor having a first gate coupled to a first gate signal and a first terminal coupled to the first bias voltage by the first switching unit, and a second switching unit for coupling a second terminal of the first MOS transistor to a first bit line.

Abstract: A semiconductor device includes a one-time programmable (OTP) memory cell includes a first MOS transistor having a gate coupled to a bit line, a first switching device, coupled to one side of a source/drain of the first MOS transistor, configured to provide a current path for a current supplied to the gate of the first MOS transistor, and a second switching device configured to provide a bias voltage at the other side of the source/drain of the first MOS transistor.

Abstract: Embodiments provide improved memory bitcells, memory arrays, and memory architectures. In an embodiment, a memory cell comprises a transistor having drain, source, and gate terminals; and a plurality of program nodes, with each of the program nodes charged to a pre-determined voltage and coupled to a respective one of a plurality of bit lines.

Abstract: An electronic device can include a nonvolatile memory cell, wherein the nonvolatile memory cell can include an antifuse component, a switch, and a read transistor having a control electrode. Within the nonvolatile memory cell, the switch can be coupled to the antifuse component, and the control electrode of the read transistor can be coupled to the antifuse component. The nonvolatile memory cell can be programmed by flowing current through the antifuse component and the switch and bypassing the current away the read transistor. Thus, programming can be performed without flowing current through the read transistor decreasing the likelihood of the read transistor sustaining damage during programming. Further, the antifuse component may not be connected in series with the current electrodes of the read transistor, and thus, during read operations, read current differences between programmed and unprogrammed nonvolatile memory cells can be more readily determined.

Abstract: Techniques and circuitry are disclosed for efficiently implementing programmable memory array circuit architectures, such as PROM, OTPROM, and other such programmable non-volatile memories. The circuitry employs an antifuse scheme that includes an array of memory bitcells, each containing a program device and an antifuse element configured with current path isolation well and for storing the memory cell state. The bitcell configuration, which can be used in conjunction with column/row select circuitry, power selector circuitry, and/or readout circuitry, allows for high-density memory array circuit designs and layouts.

Abstract: According to one embodiment, a one-time programmable (OTP) device comprises a memory FinFET in parallel with a sensing FinFET. The memory FinFET and the sensing FinFET share a common source region, a common drain region, and a common channel region. The memory FinFET is programmed by having a ruptured gate dielectric, resulting in the sensing FinFET having an altered threshold voltage and an altered drain current. A method for utilizing such an OTP device comprises applying a programming voltage for rupturing the gate dielectric of the memory FinFET thereby achieving a programmed state of the memory FinFET, and detecting by the sensing FinFET the altered threshold voltage and the altered drain current due to the programmed state of the memory FinFET.

Abstract: An apparatus includes a bit cell of a programmable memory circuit. The bit cell includes a programmable device. The bit cell includes a first device having a first type. The first device is configured to conduct a first current between a first node and a second node in response to a first value of a signal on the word line and a signal on a bit line. The programmable device is configured to be programmed in response to a first level of the first current. The bit cell includes a circuit coupled to the second node. The circuit is configured to reduce a leakage current through the first device in response to a second value of the signal on the word line and based on a feedback signal. In at least one embodiment of the apparatus, the feedback signal is based on a signal on the bit line.

Abstract: Memory devices and methods of operation are provided. A memory device includes first and second cross-coupled inverters and first and second access transistors coupled to an input node of the second inverter. The memory device also includes a control circuit for providing a first reference voltage at a first ground node of the first inverter and a second reference voltage at a second ground node of the second inverter. The first access transistor is configured to conduct current from a first bit line to the input node and to provide substantially no current conduction from the input node to the first bit line. The second access transistor is configured to conduct current from the input node to one of the first bit line and a second bit line and to provide substantially no current conduction from the input node to the one of first and second bit lines.

Abstract: A differential read only memory array includes a differential sense amplifier coupled to first and second bit lines. A first bit cell is coupled to a first word line and to the first and second bit lines. The at least one bit cell includes a first transistor having a gate coupled to the first word line, a drain coupled to the first bit line, and a source coupled to a first power supply line. A second transistor has a gate coupled to the first word line. A source and a drain of the second transistor are either both connected to the second bit line or both unconnected to the second bit line.

Abstract: According to one exemplary embodiment, a one-time programmable memory cell includes an access transistor coupled to a shiftable threshold voltage transistor between a bitline and a ground, where the access transistor has a gate coupled to a wordline. The shiftable threshold voltage transistor has a drain and a gate shorted together. A programming operation causes a permanent shift in a threshold voltage of the shiftable threshold voltage transistor to occur in response to a programming voltage on the bitline and the wordline. In one embodiment, the access transistor is an NFET while the shiftable threshold voltage transistor is a PFET. In another embodiment, the access transistor is an NFET and the shiftable threshold voltage transistor is also an NFET. The programming voltage can cause an absolute value of the threshold voltage to permanently increase by at least 50.0 millivolts.

Abstract: A semiconductor device includes a sub word line driver. A first sub word line and a second sub word line transmit an operation signal to a memory cell. A main word line optionally sends the operation signal to the first sub word line and the second sub word line. A switching transistor is disposed between the first sub word line and the second sub word line. A gate of the switching transistor is connected the main word line.

Abstract: An antifuse according to an embodiment of the invention herein can include a depletion mode metal oxide semiconductor field effect transistor (“MOSFET”) having a conduction channel and a metal gate overlying the conduction channel. A cathode and an anode of the antifuse can be electrically coupled to the gate and spaced apart from one another in a direction the gate extends, such that the antifuse is programmable by driving a programming current between the cathode and the anode to cause material of the metal gate to migrate away. The gate may be configured such that, under appropriate biasing conditions, when the antifuse is unprogrammed, the conduction channel is turned on unless a voltage above a first threshold voltage is applied to the gate to turn off the conduction channel. The gate can be configured such that when the antifuse has been programmed, the conduction channel remains turned on even if a voltage above the first threshold voltage is applied between the gate and a source region of the MOSFET.

Abstract: A circuit with leakage and data retention control includes at least one memory cell in a first memory array. The at least one memory cell is coupled to a first power supply voltage and a virtual ground. The circuit includes a current source and an NMOS transistor. The drain of the NMOS transistor is coupled to the virtual ground and the gate of the NMOS transistor is coupled to the current source.

Abstract: A one-time-programmable memory device comprises a one-time-programmable memory cell array, a voltage pumping circuit, and a programming verification circuit. The one-time-programmable memory cell array comprises a plurality of memory cells. Each memory cell is arranged at an intersection of a bit line and a word line. The voltage pumping circuit comprises a plurality of local voltage boost circuits. Each local voltage boost circuit is shared by a corresponding memory cell of the plurality of memory cells. The programming verification circuit is coupled to the one-time-programmable memory cell array for verifying that conduction current of programmed memory cells of the plurality of memory cells is greater than a predetermined current level after programming. Each local boost circuit isolates leakage current of a corresponding programmed memory cell, and prevents programming voltage failure due to current overloading at a corresponding voltage pumping circuit.

Abstract: A write-once memory can be written only once to each memory cell; therefore, a defective bit cannot be detected by an actual inspection of writing. Accordingly, as described above, the measures, in which a redundant circuit is provided and the defective bit is modified before shipping, cannot be taken; thus, it is difficult to provide a memory with few defects. It is an object of the present invention to provide a write-once memory where the probability of a defect is reduced considerably. A nonvolatile memory that can be written only once includes a redundant memory cell, a first circuit which allocates an address to the redundant memory cell, a second circuit which outputs a determination signal that expresses whether writing is performed normally or not, and a third circuit, to which the determination signal is inputted, which controls the first circuit and the second circuit.

Abstract: Provided is a memory device in which the circuit structure is simplified while the functions of a memory including an OTP memory and a memory including a pseudo-MTP memory are maintained. A memory device includes a plurality of memory sets each including a mark bit storage area for storing a mark bit, which indicates that an object is deleted data, and a data bit storage area for storing data to be stored, the memory device being built from a one time programmable (OTP) memory including an OTP memory block and a pseudo-MTP memory block, the OTP memory block containing a given number of memory sets selected out of the plurality of memory sets to operate as an OTP memory, the pseudo-MTP memory block containing the rest of the plurality of memory sets which remains after the memory sets of the OTP memory block are excluded and operates as a pseudo-MTP memory. The mark bit is written in advance in the mark bit storage area of the OTP memory block.

Abstract: An antifuse can include an insulated gate field effect transistor (“IGFET”) having an active semiconductor region including a body and first regions, i.e., at least one source region and at least one drain region separated from one another by the body. A gate may overlie the body and a body contact is electrically connected with the body. The first regions have opposite conductivity (i.e., n-type or p-type) from the body. The IGFET can be configured such that a programming current through at least one of the first regions and the body contact causes heating sufficient to drive dopant diffusion from the at least one first region into the body and cause an edge of the at least one first region to move closer to an adjacent edge of at least one other of the first regions. In such way, the programming current can permanently reduce electrical resistance by one or more orders of magnitude between the at least one first region and the at least one other first region.

Abstract: Embodiments relate to a semiconductor device, including a channel area; a gate line extending along the channel area so that the channel area can be set into a conductive state by activating the gate line; a plurality of terminals including an electrical connection to the channel area, so that the plurality of terminals is connectable to a predetermined voltage by activating the gate line.

Abstract: A memory circuit includes a plurality of bit lines. A first memory cell and a second memory cell are coupled in series. Each of the first memory cell and the second memory cell is capable of storing a first type datum. The first memory cell and the second memory cell share a first common source/drain (S/D) region. The first common S/D region is electrically isolated from all of the bit lines.

Abstract: A first terminal and a second terminal of a FinFET transistor are used as two terminals of an anti-fuse. To program the anti-fuse, a gate of the FinFET transistor is controlled, and a voltage having a predetermined amplitude and a predetermined duration is applied to the first terminal to cause the first terminal to be electrically shorted to the second terminal.

Abstract: It is an object of the present invention to provide a volatile organic memory in which data can be written other than during manufacturing and falsification by rewriting can be prevented, and to provide a semiconductor device including such an organic memory. It is a feature of the invention that a semiconductor device includes a plurality of bit lines extending in a first direction; a plurality of word lines extending in a second direction different from the first direction; a memory cell array including a plurality of memory cells each provided at one of intersections of the bit lines and the word lines; and memory elements provided in the memory cells, wherein the memory elements include bit lines, an organic compound layer, and the word lines, and the organic compound layer includes a layer in which an inorganic compound and an organic compound are mixed.

Abstract: A non-volatile memory (NVM) cell comprises an NMOS control transistor having commonly-connected source, drain and bulk region electrodes and a gate electrode connected to a storage node; a PMOS erase transistor having commonly-connected source, drain and bulk region electrodes and a gate electrode connected to the storage node; an NMOS data transistor having source, drain and bulk region electrodes and a gate electrode connected to the storage node, the bulk region electrode being connected to a common bulk node; the first NMOS pass gate transistor having a source electrode connected to the drain electrode of the NMOS data transistor, a drain electrode, a bulk region electrode connected to the common bulk node, and a gate electrode; and a second NMOS pass gate transistor having a drain electrode connected to the source electrode of the NMOS data transistor, a source electrode, a bulk region electrode connected to the common bulk node, and a gate electrode.

Abstract: An alternative electrical fuse structure, which may be similar to or identical with an insulated gate field effect transistor (“IGFET”) of advanced CMOS technology, can be very area efficient and programmable at relatively low voltages, e.g., programming voltages between 1.5 V and 2.5 V. A method is provided for programming an electrical fuse having the structure of an IGFET to permanently electrically isolate the drain of the IGFET from its source. In this way, the step of programming the IGFET fuse can increase a resistance between the source and the drain of the IGFET from a pre-programming value to a post-programming value by two or more orders of magnitude when any given gate-source voltage value and any given drain-source voltage value within normal operational ranges of the IGFET are applied thereto.

Abstract: In a semiconductor memory device in which each memory cell is constituted by one transistor, in a memory cell pattern, two adjacent bits form one diffusion pattern, two adjacent transistors share a source region, and two drain regions are separated from each other. A plurality of arrays in each of which at least a column of the diffusion patterns is disposed include bit lines, and the bit lines of the first array are independent of the bit lines of the second array. In an interface between the arrays, ends at one side of the bit lines of each of the arrays are located on an associated one of two drain regions which are separated from each other with the source region which is shared on one diffusion pattern sandwiched therebetween. This configuration can provide a sufficient bit-line separation width, and reduce the area.

Abstract: An apparatus includes a bit cell of a programmable memory circuit. The bit cell includes a programmable device. The bit cell includes a first device having a first type. The first device is configured to conduct a first current between a first node and a second node in response to a first value of a signal on the word line and a signal on a bit line. The programmable device is configured to be programmed in response to a first level of the first current. The bit cell includes a circuit coupled to the second node. The circuit is configured to reduce a leakage current through the first device in response to a second value of the signal on the word line and based on a feedback signal. In at least one embodiment of the apparatus, the feedback signal is based on a signal on the bit line.

Abstract: A memory cell includes a control gate and a transistor having a gate, a source junction, and a drain junction. The gate is coupled to the control gate, and the source junction and the drain junction are asymmetrical. For example, a channel doping associated with the source junction may be different than a channel doping associated with the drain junction. The memory cell also includes a write line coupled to the control gate, a source line coupled to the source junction of the transistor, and a bit line coupled to the drain junction of the transistor. The control gate could represent a second transistor, where the gates of the transistors are coupled together to form a floating gate. The memory cell could be programmed to store a single-bit value or a multiple-bit value, such as by storing the appropriate charge on the floating gate.

Abstract: A one time programming (OTP) memory cell includes a first transistor and a second transistor. The first transistor has a first drain, a first source, a first gate, and a first normal operational voltage value higher that a second normal operational voltage value of the second transistor. The second transistor has a second drain, a second source, and a second gate. The first source is coupled to the second drain. The second source is configured to detect data stored in the OTP memory cell.

Abstract: Embodiments relate to a manufacturing method of a one time programmable (OTP) memory device including: forming a common source in a linear configuration on a semiconductor substrate; forming a gate dielectric layer on the semiconductor substrate at both sides of the source; forming a gate over the gate dielectric layer; forming a spacer between the gates and at both side walls of the gate; and forming a drain on the semiconductor substrate at both sides of the spacer. With embodiments, the OTP memory device can be formed together with the logic part using the logic process and can increase the storage capacity of the OTP memory device by improving density of memory arrays.

Abstract: Disclosed herein are memory devices and related methods and techniques. A cell in the memory device may be associated with an intervening transistor, the intervening transistor being configured to isolate the cell from adjacent cells under a first operating condition and to provide a current to a bit line associated with the cell under a second operating condition.

Abstract: According to one embodiment, a ROM generator includes a ROM-data acquiring unit that acquires ROM data; a cell-data storing unit that stores a plurality of cell data respectively having different connection places of a connection path with respect to same ROM data; a cell-data selecting unit that selects the cell data stored in the cell data storing unit with respect to the same ROM data acquired by the ROM-data acquiring unit; and a cell-data arranging unit that arranges the cell data selected by the cell-data selecting unit to correspond to cell regions.

Abstract: Methods, systems, and apparatus, including computer program products for programming memory. In one aspect, a program circuit includes a first transistive element; a second transistive element coupled to a first end of the first transistive element; a burn subcircuit, the burn subcircuit including a third transistive element coupled to a fourth transistive element, where the drain of the third transistive element is coupled to a second end of the first transistive element, and the source of the third transistive element is coupled to the drain of the fourth transistive element; and a fifth transistive element coupled in parallel to the fourth transistive element. Control logic coupled to the first transistive element, the burn subcircuit, and the fourth transistive element selectively enables the second transistive element, selectively enables the fourth transistive element, and selectively enables the fifth transistive element to enable a read mode or a program mode.

Abstract: A logic device implementing configurations for ROM based logic uses arrays of memory cells to provide outputs based on inputs received at the logic device. The logic device stores values in the memory cells that are accessed when an input is received. The memory cells are transistors that provide values of ‘1’ or ‘0.’ Various configurations reduce the number of transistors while implementing the memory block by utilizing a single bitline or a dynamic precharge implementation.

Abstract: A method and system for improving reliability of OTP memories, and in particular anti-fuse memories, by storing one bit of data in at least two OTP memory cells. Therefore each bit of data is read out by accessing the at least two OTP memory cells at the same time in a multi-cell per bit mode. By storing one bit of data in at least two OTP memory cells, defective cells or weakly programmable cells are compensated for since the additional cell or cells provide inherent redundancy. Program reliability is ensured by programming the data one bit at a time, and verifying all programmed bits in a single-ended read mode, prior to normal operation where the data is read out in the multi-cell per bit mode. Programming and verification is achieved at high speed and with minimal power consumption using a novel program/verify algorithm for anti-fuse memory. In addition to improved reliability, read margin and read speed are improved over single cell per bit memories.

Abstract: A read only memory cell circuit is provided. The memory cell circuit includes at least one memory cell. A pair of bit lines associated with each memory cell is provided which form a complementary output. The at least one memory cell is configured to be coupled to first or second of the bit line pair.

Abstract: A complementary read-only memory (ROM) cell includes a transistor; and a bit line and a complementary bit line adjacent to the transistor; wherein a drain terminal of the transistor is connected to one of the bit line and the complementary bit line based on data programmed in the ROM cell.

Abstract: A nonvolatile memory device including one-time programmable (OTP) unit cell is provided. The nonvolatile memory device includes: a unit cell; a detecting unit configured to detect data from the unit cell; and a read voltage varying unit configured to vary an input voltage and supply a varied read voltage to the unit cell.

Abstract: A One-Time Programmable (OTP) unit cell and a nonvolatile memory device having the same are disclosed. A unit cell of a nonvolatile memory device includes: an anti-fuse connected between an output terminal and a ground voltage terminal; a first switching unit connected to the output terminal to transfer a write voltage to the output terminal; and a second switching unit connected to the output terminal to transfer a read voltage to the output terminal.

Abstract: According to one embodiment, a semiconductor storage device includes a first memory cell, a second memory cell and a third memory cell. The first memory cell forms a connection path used for storage of data. The second memory cell varies a connection place from a connection place of the connection path formed in the first memory cell, and stores data different from the data stored in the first memory cell is stored. The third memory cell varies a connection place from the connection place of the connection path formed in the second memory cell, and stores data same as the data stored in the first memory cell is stored.