Abstract: Provided is a thin film transistor wherein the shape of a protrusion formed on the interface between an oxide semiconductor layer and a protection film is suitably controlled, and stable characteristics are achieved. This thin film transistor is characterized in that: the thin film transistor has an oxide semiconductor layer formed of an oxide containing at least In, Zn and Sn as metal elements, and a protection film directly in contact with the oxide semiconductor layer; and the maximum height of a protrusion formed on the oxide semiconductor layer surface directly in contact with the protection film is less than 5 nm.

Abstract: An OTP memory array includes a plurality of differential P-channel metal oxide semiconductor (PMOS) OTP memory cells programmable and readable in predetermined states of program and read operations, and is capable of providing sufficient margins against global process variations and temperature variations while being compatible with standard logic fin-shaped field effect transistor (FinFET) processes to obviate the need for additional masks and costs associated with additional masks.

Abstract: The memory cell of a memory device comprises a MOS capacitor having a n-type gate and a n-type well, a first switch to temporarily apply a breakthrough voltage across the n-type gate and the n-type well to generate a permanent conductive breakthrough structure between the n-type gate and the n-type well.

Abstract: A data storage device includes a memory including a plurality of storage elements configured to store data. The plurality of storage elements includes a first group of storage elements and a second group of storage elements. The data storage device further includes a selection module configured to retrieve first bit line defect information affecting the first group of storage elements and to retrieve second bit line defect information affecting the second group of storage elements.

Abstract: A mask-programmed read-only memory (MROM) has a plurality of column line pairs, each having a bit line and a complement bit line. The MROM includes a plurality of memory cells corresponding to a plurality of intersections between the column line pairs and a plurality of word lines. Each memory cell includes a high Vt transistor and a low Vt transistor.

Abstract: A semiconductor circuit can include a plurality of arrays of transistors having differing characteristics and operating at low voltages and currents. A drain line drive signal may provide a potential to a drain line to which a selected transistor is connected. A row of drain mux circuits can provide reduced leakage current on the drain line drive signal so that more accurate current measurements may be made. A gate line drive signal may provide a potential to a gate line to which the selected transistor is connected. A column of gate line mux circuits can provide a gate line low drive signal to unselected transistors to reduce leakage current in unselected transistors so that more accurate drain current measurements may be made to the selected transistor.

Abstract: The present disclosure includes methods, devices, and systems for error detection or correction of stored signals in memory devices. An example method includes determining whether to perform error correction operations on contents of a non-volatile memory array. Determining whether to correct can include determining whether a level of errors in pre-programmed signals in the non-volatile memory array exceeds a bit error rate threshold, where the pre-programmed signals are different from the contents of the non-volatile memory array, and performing error correction on the contents of the non-volatile memory array if the level of errors exceeds the bit error rate threshold.

Abstract: The rows of a cache are generally maintained in a low power state. In response to a memory access operation, the data processor predicts a plurality of cache rows that may be targeted by the operation, and transitions each of the plurality of cache rows to an active state to prepare them for access. The plurality of cache rows are predicted based on speculatively decoding a portion of a base address and a corresponding portion of an offset without performing a full addition of the portions. Because a full addition is not performed, the speculative decoding can be performed at sufficient speed to allow the set of rows to be transitioned to the active state before full decoding of the memory address is completed. The cache row associated with the memory address is therefore ready for access when decoding is complete, maintaining low latency for cache accesses.

Abstract: A memory cell includes a programming selection transistor, a following gate transistor, an antifuse element, and a reading circuit. A charging current formed by the antifuse element may trigger the reading circuit to form a stable read current during a reading operation of the memory cell so that the time for reading data from the memory cell can be shortened. A discharging process may be operated in the beginning of the reading operation of the memory cell so that the window of time for reading data from the memory cell can be widened.

Abstract: Methods for down converting a modulated carrier signal to a demodulated baseband signal are described herein. The method requires that a first portion of energy is transferred from the modulated carrier signal, and stored at a first storage device when a first switch is on. At least some of the energy stored in the first storage device is discharged when the first switch is off. The method further comprises transferring a second portion of energy from the modulated carrier signal, storing at a second storage device the second portion of transferred energy when a second switch is on, and discharging at least some of the energy stored in the second storage device when the second switch is off.

Abstract: A method of generating a default state in an embedded Multi-Time-Programmable-Read-Only-Memory for a high-performance logic technology consisting of a plurality of memory cells featuring a charge trap, each having a first and a second NMOS transistor. The first and second NMOS transistors use a different mask having different threshold voltages. The second NMOS threshold voltage is adjusted to a middle point of the threshold voltage of the first NMOS with or without trapping the charge. When the charge is not trapped by the first NMOS, the NMOS threshold is lowered to the second NMOS, thereby generating a default state. When the charge is trapped to the first NMOS, the NMOS threshold is higher than the second NMOS, generating a second state. Moreover, a reference voltage generation can use two arrays, each consisting of memory cells and reference memory cells such that a default state can be generated for a single transistor per memory cell.

Abstract: A transistor cell is provided that includes a dummy gate overlaying a continuous oxide definition (OD) region. A first portion of the OD region adjacent a first side of the dummy forms the drain. The cell includes a local interconnect structure that couples the dummy gate and a portion of the OD region adjacent a second opposing side of the dummy gate to a source voltage.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a plurality of dummy gate lines parallel to each other in a first direction and extending in a second direction that is orthogonal to the first direction; a plurality of first dummy filling patterns between the plurality of dummy gate lines, the first dummy filling patterns parallel to each other in the first direction, and arranged apart from each other in the second direction; a plurality of first dummy vias on the plurality of first dummy filling patterns; and a plurality of first dummy wiring lines connected to the plurality of first dummy vias, the first dummy vias extending in the second direction, and parallel to each other in the first direction.

Abstract: A 6T static random access memory cell, array, and memory thereof are provided, in which the memory cell includes a first inverter, a second inverter, a first access transistor, and a second access transistor. A first high supply voltage and a low supply voltage are coupled to the first inverter. A second high supply voltage and the low supply voltage are coupled to the second inverter. The first access transistor has a gate terminal coupled to a first word line. The first access transistor has a source terminal coupled to the first node. The second access transistor has a gate terminal coupled to a second word line, and the second access transistor has a source terminal coupled to the second node. The first word line provides ON signals to turn on the first access transistor, and the second high supply voltage provides a first differential voltage simultaneously.

Abstract: A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is provided with dummy bit lines which are arranged collaterally with a proper bit line, and column direction load circuits which are sequentially coupled to the dummy bit lines. Each column direction load circuit is provided with plural NMOS transistors fixed to an off state, predetermined ones of which have the source and the drain suitably coupled to any of the dummy bit lines. Load capacitance accompanying diffusion layer capacitance of the predetermined NMOS transistors is added to the dummy bit lines, and corresponding to the load capacitance, the delay time from a decode activation signal to a dummy bit line signal is set up. The dummy bit line signal is employed when setting the start-up timing of a sense amplifier.

Abstract: A semiconductor structure has a MOSFET and a substrate to accommodate the MOSFET. The MOSFET has a gate, a source, and a drain in the substrate. A first substrate region surrounding the MOSFET is doped with a stress enhancer, wherein the stress enhancer is configured to generate a tensile stress in the MOSFET's channel and the tensile stress is along the channel's widthwise direction.

Abstract: A semiconductor memory includes: a first switching transistor, wherein the first switching transistor has a first terminal, a second terminal, and a third terminal, and the second terminal is coupled to a first word-line; a first differential bit-line pair possessing a non-inverted bit-line and an inverted bit-line, wherein the non-inverted bit-line and the inverted bit-line thereof are mutually-exclusively coupled to the first terminal of the first switching transistor for storing first information; and a second differential bit-line pair possessing a non-inverted bit-line and an inverted bit-line, wherein the non-inverted bit-line and the inverted bit-line thereof are mutually-exclusively coupled to the third terminal of the first switching transistor for storing second information.

Abstract: A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is provided with dummy bit lines which are arranged collaterally with a proper bit line, and column direction load circuits which are sequentially coupled to the dummy bit lines. Each column direction load circuit is provided with plural NMOS transistors fixed to an off state, predetermined ones of which have the source and the drain suitably coupled to any of the dummy bit lines. Load capacitance accompanying diffusion layer capacitance of the predetermined NMOS transistors is added to the dummy bit lines, and corresponding to the load capacitance, the delay time from a decode activation signal to a dummy bit line signal is set up. The dummy bit line signal is employed when setting the start-up timing of a sense amplifier.

Abstract: A complementary read-only memory (ROM) cell includes a transistor; and a bit line and a complementary bit line adjacent to the transistor; wherein a drain terminal of the transistor is connected to one of the bit line and the complementary bit line based on data programmed in the ROM cell.

Abstract: A memory includes an array of memory cells including rows and columns. The memory includes circuitry coupled to the word lines applying a first bias voltage to a first set of spaced-apart locations on a word line or word lines in the array, while applying a second bias voltage different than the first bias voltage, to a second set of spaced-apart locations on the word line or word lines, locations in the first set of spaced-apart locations being interleaved among locations in the second set of spaced-apart locations, whereby current flow is induced between locations in the first and second sets of locations that cause heating of the word line or word lines.

Abstract: A method and apparatus for reducing space and pixel circuit complexity by using a 4-way shared vertically aligned pixels in a same column. The at least four pixels in the pixel circuit share a reset transistor and a source follower transistor, can have a plurality of same colored pixels and a plurality of colors, but do not include a row select transistor.

Abstract: A memory system includes a controller suitable for providing a data to be written on a memory cell array and a control data for indicating whether or not the data has a preset data pattern and a memory device suitable for selectively writing an patterned data or the data provided by the controller on the memory cell array in response to the control data, wherein the patterned data is stored in the memory device and has the preset data pattern.

Abstract: A semiconductor device includes a transistor including a plurality of transistor cells in a semiconductor body, each transistor cell including a control terminal and first and second load terminals. The semiconductor device further includes a first electrical connection electrically connecting the first load terminals. The semiconductor device further includes a second electrical connection electrically connecting the second load terminals. The transistor further includes a phase change material exhibiting a solid-solid phase change at a phase transition temperature Tc between 150° C. and 400° C.

Abstract: A control circuit includes a data driver, a charge circuit, and a first data line coupled with the data driver and the charge circuit. The charge circuit is configured to charge the first data line when the first data line is selected for accessing a memory cell corresponding to the first data line and to not charge the first data line when the first data line is not selected for accessing the memory cell. The data driver, based on a first control signal, is configured to transfer a signal on the first data line to an output of the data driver.

Abstract: A process and device are provided for a high-k gate-dielectric operating as a built-in e-fuse. Embodiments include: providing first and second active regions of a transistor, separated by a gate region of the transistor, on a substrate; forming an interfacial layer on the gate region; minimizing the interfacial layer; forming a high-k gate dielectric layer on the interfacial layer to operate as an e-fuse element, the high-k gate dielectric layer and interfacial layer having a combined breakdown voltage less than three times a circuit operating voltage associated with the transistor; and forming a metal gate on the high-k gate dielectric layer.

Abstract: Wordline decoder circuits for an embedded Multi-Time-Read-Only-Memory that includes a plurality of NMOS memory cells coupled to a plurality of wordlines in each row. The wordline decoder circuits control the charge trap behavior of the target NMOS memory array by the mode-dependent wordline high voltage (VWLH) and wordline low voltage (VWLL) trapping the charge in a programming mode by applying an elevated wordline voltage (EWLH) to one of the plurality of WLs, while de-trapping the charge in a reset mode by applying a negative wordline voltage (NWLL) to the entire array. The mode dependent voltage control is realized by switching to couple EWLH to VWLH in a programming mode, otherwise VDD to VWLH, while coupling NWLL to VWLL in a reset mode, otherwise, GND to VWLL. The switch includes plural gated diodes from VWLH with the wordline high protection voltage of VWLH_PR generated by lowering VWLH determined by gated diodes times threshold voltage.

Abstract: A non-volatile memory includes a memory unit. The memory unit includes a first word line, a second word line, a control line, a logic circuit, a bit line, a first cell, and a second cell. The logic circuit has a first input terminal connected to the first word line, a second input terminal connected to the second word line, and an output terminal connected to the control line. The first cell has a control terminal connected to the first word line, a first terminal connected to the control line, and a second terminal selectively connected to the bit line. The second cell has a control terminal connected to the second word line, a first terminal connected to the control line, and a second terminal selectively connected to the bit line.

Abstract: A bitline circuit for embedded Multi-Time-Read-Only-Memory including a plurality of NMOS memory cells coupled to a plurality of wordlines in each row, bitlines in each column, and a source-line. More specifically, the bitline circuit controls a charge trap behavior of the target NMOS memory array by mode-dependent bitline pull-down circuit, thereby discharging the bitline strongly to GND to trap the charge effectively in a Programming mode, and discharge the bitline weakly to GND to develop a bitline voltage to detect the charge trap state. The mode dependent circuit is realized by using at least two NMOS to switch the device strength, using a pulsed gate control in a Read mode, or using analog voltage to limit the bitline current. The proposed method further includes a protection device, allowing all bitline control circuit using thin oxide devices.

Abstract: A one-time programmable (OTP) memory includes an OTP cell array including a plurality of OTP cells that each include a programming transistor configured to change irreversibly when programmed; a temperature compensation reference voltage generating unit configured to sense a temperature of the OTP cell memory and generate a reference voltage such that as the sensed temperature changes, the reference voltage generated by the temperature compensation reference voltage generating unit changes in a manner that is inversely proportional the change in the sensed temperature; and a temperature compensation operating voltage generating unit configured to receive the reference voltage to generate an operating voltage that is proportional to the reference voltage and is applied to the OTP cell array.

Abstract: According to an embodiment, a semiconductor memory includes word lines, a plurality of sets of a pair of bit lines, memory cells, a writing/reading circuit, and a word line selection circuit. In a state where inverted data of program data has been written to the memory cells, a stress is applied and the program data is programmed to the memory cells. The writing/reading circuit writes the inverted data of the same program data to a unit memory cell group made of memory cells connected to a set of a pair of bit lines at a time of programming, and reads data from the unit memory cell group by detecting a signal level of the pair of bit lines at a time of reading. The word line selection circuit simultaneously selects and drives two or more word lines of the word lines connected to the unit memory cell group.

Abstract: An anti-fuse circuit in which anti-fuse program data may be monitored outside of the anti-fuse circuit and a semiconductor device including the anti-fuse circuit are disclosed. The anti-fuse circuit includes an anti-fuse array, a data storage circuit, and a first selecting circuit. The anti-fuse array includes one or more anti-fuse blocks including a first anti-fuse block having a plurality of anti-fuse cells and the anti-fuse array is configured to store anti-fuse program data. The data storage circuit is configured to receive and store the anti-fuse program data from the anti-fuse array through one or more data buses. The first selecting circuit is configured to output anti-fuse program data of a selected anti-fuse block of the one or more anti-fuse blocks in response to a first selection signal.

Abstract: According to one embodiment, a method of operating a semiconductor memory device is disclosed. The method can include storing read-only data in at least one selected from a memory cell of an uppermost layer and a memory cell of a lowermost layer of a plurality of memory cells connected in series via a channel body. The channel body extends upward from a substrate to intersect a plurality of electrode layers stacked on the substrate. The method can include prohibiting a data erase operation of the read-only memory cell having the read-only data stored in the read-only memory cell.

Abstract: Provided is an OTP memory cell including a first antifuse unit, a second antifuse unit, a select transistor, and a well region. The first and the second antifuse unit respectively include an antifuse layer and an antifuse gate disposed on a substrate in sequence. The select transistor includes a select gate, a gate dielectric layer, a first doped region, and a second doped region. The select gate is disposed on the substrate. The gate dielectric layer is disposed between the select gate and the substrate. The first and the second doped region are respectively disposed in the substrate at two sides of the select gate, wherein the second doped region is disposed in the substrate at the periphery of the first and the second antifuse unit. The well region is disposed in the substrate below the first and the second antifuse unit and is connected to the second doped region.

Abstract: A two-bit read-only-memory (ROM) cell and method of sensing its data state. Each ROM cell in an array includes a single n-channel metal-oxide-semiconductor (MOS) transistor with a source biased to a reference voltage, and its drain connected by a contact or via to one or none of first, second, and third bit lines associated with its column in the array. Each row in the array is associated with a word line serving as the transistor gates for the cells in that row. In response to a column address, a column select circuit selects one pair of the three bit lines to be applied to a sense line in wired-NOR fashion for sensing.

Abstract: Provided is a semiconductor non-volatile memory device capable of improving the accuracy of trimming by creating a written state before data is written into a non-volatile memory element. The semiconductor non-volatile memory device includes: a written data transmission circuit for transmitting written data to a non-volatile memory element; a first switch connected between the non-volatile memory element and a data output terminal; a third switch connected to an output terminal of the written data transmission circuit; and a control circuit for controlling the respective switches. When a test mode signal is input, the control circuit turns on only the first switch and the third switch so as to control the written data to be output to the data output terminal before data is written into the non-volatile memory element.

Abstract: A semiconductor device having a memory cell including a capacitor and a select transistor with a floating body structure, a bit line connected to the select transistor, a bit line control circuit, and a sense amplifier amplifying a signal read out from the memory cell. The bit line control circuit sets the bit line to a first potential during a non-access period of the memory cell, and thereafter sets the bit line to a second potential during an access period of the memory cell, so that the data retention time can be prolonged by reducing leak current at a data storage node of the memory cell so that an average consumption current for the data retention can be reduced.

Abstract: A method and system for storing and retrieving data using flash memory devices. One example system includes an apparatus within a flash memory configuration. The flash memory configuration includes a plurality of memory cells, where each memory cell has a charge storage capacity for use in implementing digital storage. The apparatus includes a processing arrangement configured to access each of the memory cells in a write operation and a read operation. The apparatus also includes an instruction set for instructing the processor to impose target charge levels for defining a plurality of data values for each of the memory cells. The target charge levels are programmably movable with respect to the charge storage capacity.

Abstract: A semiconductor memory includes an array of volatile memory cells, wherein one of the volatile memory cells has transistors connected in a first memory cell circuit, and at least one non-volatile memory cell having transistors connected in a second memory cell circuit, wherein the transistors in the first memory cell circuit are at least one more than the transistors in the second memory cell circuit.

Abstract: A one-time programmable memory includes a first one-time programmable memory cell including a fuse core having an input terminal for receiving a trim signal, an output terminal for providing a sense signal, and a fuse. The fuse core conducts current through the fuse in response to the trim signal. The one-time programmable memory cell also includes a sense circuit having an input terminal coupled to the output terminal of the fuse core, and an output terminal for providing a termination signal, and a logic circuit having a first input terminal for receiving a program enable signal, a second input terminal for receiving a data signal, a third input terminal coupled to the output terminal of the sense circuit for receiving the termination signal, and an output terminal coupled to the input terminal of the fuse core for providing the trim signal.

Abstract: A semiconductor memory device according to an embodiment includes a memory cell array including memory cells each formed from a transistor formed over an active area of a well and disposed at intersections of a word line and a bit line group, the memory cell having different connection states including a state in which a source or a drain of the transistor is not electrically connected to any one of bit lines belonging to the bit line group and states in which the source or the drain is electrically connected only to a specific one of the bit lines, and an active area serving as a gate of the transistor being continuously formed in arrangement areas of the bit lines of the bit line group and spaces between the bit lines.

Abstract: A mask-programmed read-only memory (MROM) has a plurality of column line pairs, each having a bit line and a complement bit line. The MROM includes a plurality of memory cells corresponding to a plurality of intersections between the column line pairs and a plurality of word liens. Each memory cell includes a high Vt transistor and a low Vt transistor.

Abstract: The present disclosure provides a reference one time programmable (OTP) cell, wherein the reference OTP cell can generate a reference bias current in at least a programmed-on configuration; a current mirror coupled to an output of the OTP cell, wherein the current mirror includes at least two gate-coupled field effect transistors (FETs); wherein a current gain of a second of the two FETS is a fraction less than one of a first of the at least two gate-coupled FETs; a programmable OTP memory bit element (OTPMBE) coupled to an input of the current mirror; and a comparator having an input coupled to a node between the OTPMBE and the current mirror.

Abstract: The present invention provides a one time programmable (OTP) memory cell including a select gate transistor, a following gate transistor, and an antifuse varactor. The select gate transistor has a first gate terminal, a first drain terminal, a first source terminal, and two first source/drain extension areas respectively coupled to the first drain terminal and the first source terminal. The following gate transistor has a second gate terminal, a second drain terminal, a second source terminal coupled to the first drain terminal, and two second source/drain extension areas respectively coupled to the second drain terminal and the second source terminal. The antifuse varactor has a third gate terminal, a third drain terminal, a third source terminal coupled to the second drain terminal, and a third source/drain extension area coupled with the third drain terminal and the third source terminal for shorting the third drain terminal and the third source terminal.

Abstract: A Read Only Memory (ROM) bitline cell apparatus and programming method therefore. The programming methodology ensures a ROM structure having open state and/or breaks in the diffusion and/or dummy wordline rows to provide bitline load balancing. The ROM bitline cell apparatus and programming method exhibits improved load balancing for any combination of 1's or all 0's on the bitline. The programming methodology identifies groups of consecutive ‘1’s on the bitline and instead of connecting the ‘1’ devices between BL/BL or GND/GND, those ‘1’ devices can be connected between BL/OPEN, OPEN/BL, GND/OPEN, OPEN/GND or OPEN/OPEN. With little or no variation in bitline loading, timing can be optimized for that single case of bitline loading.

Abstract: A novel mask read-only memory is provided. After the mask read-only memory leaves the factory, the mask read-only memory has two types of cell structures. The first type cell structure records a first storing state (e.g. the logic state “1”), and the second type cell structure records a second storing state (the logic state “0”).

Abstract: Methods and apparatus for the encoding of an input sequence of digit data into a sequence of storage cells of a ROM device are disclosed. The input sequence is divided into a first kind of groups and a second kind of groups. A first kind of group comprises a plurality of consecutive first digits, two first kind of groups are separated by a second kind of group, the second kind of group comprises consecutive digits without any consecutive first digits, and the second kind of group has a starting digit which is the second digit. A starting storage cell is programmed to the active state to store the starting digit of the second kind of group. The rest digits of the second kind of group are programmed one digit at a time, based on a shared terminal which has been programmed for the proceeding storage cell.

Abstract: A semiconductor storage device has a great number of logic circuits and fuse blocks with its space-saving design. In the semiconductor storage device, a plurality of fuse blocks is arranged in a line or row in the vicinity of a gate array. Each fuse block includes a plurality of fuse pieces arranged in a juxtaposed manner and exposed to the exterior through a fuse window. A power-supply wire and a ground wire extend along the juxtaposed direction of the fuse pieces. Spacing in the vicinity of the gate array is used for arrangement of the fuse blocks.

Abstract: An encoded ROM array structure couples a first one of a first set of bitlines to a second one of a second set of bitlines through a transistor when the wordline connected to the gate terminal of that transistor is asserted. This encoded arrangement can be extended to any number of encoded bitlines, e.g., 2, 4, 8, 16, and so on. Each of the first plurality and second sets of bit lines are coupled to circuits for charging and discharging the bitlines. To read data from the first set of bit lines, the second set of bitlines is discharged, and vice versa.

Abstract: A Read Only Memory (ROM) bitline cell apparatus and programming method therefore. The programming methodology ensures a ROM structure having open state and/or breaks in the diffusion and/or dummy wordline rows to provide bitline load balancing. The ROM bitline cell apparatus and programming method exhibits improved load balancing for any combination of 1's or all 0's on the bitline. The programming methodology identifies groups of consecutive ‘1’s on the bitline and instead of connecting the ‘1’ devices between BL/BL or GND/GND, those ‘1’ devices can be connected between BL/OPEN, OPEN/BL, GND/OPEN, OPEN/GND or OPEN/OPEN. With little or no variation in bitline loading, timing can be optimized for that single case of bitline loading.

Abstract: Among other things, an n-bit ROM cell, such as a twin-bit ROM cell, and techniques for addressing one or more ROM cell portions of the n-bit ROM cell are provided. A twin-bit ROM cell comprises a first ROM cell portion adjacent to or substantially contiguous with a second ROM cell portion. The first ROM cell portion is associated with a first data bit value. The second ROM cell portion is associated with a second data bit value distinct from the first data bit value. Because the first ROM cell portion is adjacent to the second ROM cell portion, OD-to-OD spacing between the twin-bit ROM cell and an adjacent twin-bit ROM cell is increased to provide, for example, improved isolation, cell current, ROM speed, and VCCmin performance in comparison with single-bit ROM cells, while maintaining a substantially similar to pitch as the single-bit ROM cells.