Abstract: A semiconductor read-only memory configuration in which two intermediate cell halves are directly adjacent to one another perpendicularly to the longitudinal direction of a word line and are periodically repeated in the longitudinal direction of the word line. In a first intermediate cell half, the polycrystalline silicon of the word lines is ruptured and a substrate contact is set, and in a second intermediate cell half, the polycrystalline silicon is refreshed. These intermediate cell halves are adjacent to one another, and the first and the second intermediate cell halves are alternately interchanged. Instead of requiring two intermediate cells, the semiconductor read-only memory configuration requires just one intermediate cell that includes the two intermediate cell halves which are used in an alternately mirrored manner.

Abstract: A secure one-time programmable (OTP) salicided poly fuse array (2×8) cells with a power-on or on-reset hardware security feature is proposed. The secure OTP which is based on a primitive building cell that includes a salicided poly fuse and a MOS switch, utilize the same building block of the un-secure larger OTP array. This includes an enhanced multistage track & latch sense amp, or comparator, primitive memory cells, decoders for write and read mechanism, and a similar control block.

Abstract: The present invention provides a Via Code Mask read-only memory comprising an array of transistors, and a plurality of bit lines and word lines, wherein the transistors in each row of the array are connected in series by connection of a drain/source of one transistor with a drain/source of another transistor. Both ends of the series of the transistors in each row of the array are connected to a supply voltage together. Each one of the bit lines is selectively connected to drain(s)/source(s) of one or more transistors in one corresponding column. Each one of the word lines connects together gates of the transistors in one corresponding row.

Abstract: A high-speed, ultra-dense, via contact programmable ROM based on multiplexor cells is presented. High density is achieved by fully encoding n-bits of address space and programming the core with 2n bits of information per contact through the use of higher order logic techniques. Subfunction encoding is used to make substantial improvement to the area required for ROM structures. The programming is accomplished using via contacts between the top two metal layers. No transistors are used in the programmed core for the ROM, reducing the bit line load and helping to maintain a high level of performance.

Abstract: A circuit and method of implementing a digital read-only memory (ROM) utilizes a means for selectively driving one of two complementary logic state signal lines to a voltage reference upon a readout signal for an addressable bit becoming active. Each complementary logic state signal line represents one of two logic states. The logic state of the addressed bit is determined by which of the two complementary logic state signal lines is driven. The logic level of each complementary logic state signal line is then inverted and driven onto the other so that both signal lines will be driven to their proper logic state, thereby allowing either signal line to be used in ascertaining the logic state of the bit being addressed.

Abstract: A flat memory cell read only memory is disclosed. A flat cell ROM array is formed on a substrate. This array is formed by a plurality of sub-arrays. In each sub-array, a plurality of first buried diffusion regions are planted into the substrate. A insulating layer covers on the substrate. A plurality of wordlines and metal bitlines are formed on the insulating layer. The wordlines are vertically buried to the diffusion region. A flat FET array is installed in a section between the lower sides of two adjacent buried diffusion regions and word lines. Four block selecting lines are used to control the selection of the memory cell selecting transistors for reading a selecting memory cell. Commonly used metal bitlines and transistors of a minimum number are used to read data. Therefore, it has the advantages of rapidly reading, small size, high density and lower power consumption.

Abstract: An integrated device comprises at least one circuit element and a plurality of trimming elements which can be connected selectively to the at least one circuit element in order to achieve a predetermined tolerance of a characteristic parameter of the at least one circuit element; the integrated device includes a plurality of electronic switches, each of which can be switched between a first state and a second state in which it activates and deactivates a corresponding one of the trimming elements, respectively, and a memory for storing an indication of the states of the electronic switches and for operating each electronic switch in the first state or in the second state according to the indication stored.

Abstract: A system for storing data in read-only memory is disclosed that comprises bit level conductors, transistors, and sets of reference level conductors. Each reference level conductor has a reference value. A selected reference level conductor transmits a selected reference value to one of the transistors. The transistor transmits the selected reference value to a selected bit level conductor having a selected bit value. The bit level conductors, the transistors and the reference level conductors store data by encoding data as a combination comprising the selected bit value and the selected reference value. A method for storing data in read-only memory is disclosed. Bit level conductors having bit values, transistors, and sets of reference level conductors having reference values are provided. A selected bit value of a selected bit level conductor and a selected reference value of a selected reference level conductor are selected.

Abstract: A read only memory (ROM) capable of eliminating effects of off leak current of non-selected memory cells so as to prevent read errors in a large scale ROM. The ROM comprises word lines WL1−n activated in response to an address signal, sense lines CL1−m intersected with the word lines WL1−n and selected in response to a selection signal SL1−m,r, a reference sense line CLr intersected with the word lines WL1−n, memory cells 1m,n storing data therein, reference memory cells 51−n connected to the reference sense line CLr, a sense amplifier 9 for comparing currents flowing on the selected one of the sense lines CL1−n and on the reference sense line CLr. The ROM further comprises a correction current supply circuit 40 connected to the sense lines CL1−n and the reference sense line CLr.

Abstract: The present invention is directed to a circuit for equilibrating a bitline and a plateline of a dynamic plate sensing memory device. The circuit includes a first device for driving the plateline toward a predetermined voltage in response to a first control signal, a second device for driving the bitline toward the predetermined voltage in response to a second control signal, and a third device for connecting the plateline to the bitline in response to a third control signal. A method for equilibrating a plateline and a bitline of a dynamic plate sensing memory device is also disclosed.

Abstract: A memory device including a first set of memory cells, a second set of memory cells having preprogrammed states, and a circuit configured to access data included in a first segment of memory cells. When data is read from the second set of memory cells the circuit includes an enable signal to determine whether the data outputted by the second set of memory cells is preprogrammed data or data stored during normal operation. For one embodiment, data read into or retrieved from the memory cells is performed in a consistent fashion between the first set of memory cells and the second set of memory cells.

Abstract: The present invention provides a ROM having a plurality of memory cell blocks each composed of a main bit line, a ground bit line, and a plurality of memory cells for storing information, which comprises: a plurality of up select transistors for selecting a memory cell block connected to the main bit line from a plurality of the memory cell blocks; and a plurality of down select transistors for selecting a memory cell block connected to the ground line from a plurality of the memory cell blocks, said up select transistors and down select transistors being arranged alternately with the memory cell block in between, wherein the layout pattern of said up select transistors and down select transistors being rotated 90 degrees. Under this kind of new layout pattern, the main bit lines and the ground bit lines will not be affected by the performing of ion implantation process, therefore, the junction leakage current will not be increased.

Abstract: A method for thermal driven placement begins by first computing thermal response functions for individual components for several locations on a placement surface as a preprocessing step to placement. The thermal response functions can then be used to compute junction temperatures of components quickly and accurately during placement of the components in a layout. For a given component location, the component's junction temperature is computed by summing the contributions of neighboring components with the component's own contribution. The difference between predefined junction temperatures for the components and the calculated junction temperatures can then be used to assess the merits of the placement.

Abstract: A flash memory having over-erased cells eliminated and comprising adjustable erase and program conditions. The maximum and minimum threshold voltages of the cells are measured during the whole erase and program operations. The over-erased cells are shut down by applying a word line voltage lower than the minimum threshold voltage measured previously. Pre-program and repair operations for the over-erased cell are eliminated. Low read voltage is achieved. The erase and program conditions for the gate, source, drain voltage, width of a pulse, and number of pulses are adjustable in accordance with the threshold voltage to optimize the performance. A lookup table stores the relevant gate, source, drain voltage, width of a pulse, and number of pulses with respect to the threshold voltage for the adjustable conditions. The benefits achieved by the operation of the flash memory include high efficiency, long endurance, narrow threshold voltage distribution, low power consumption, and low process-sensitivity.

Abstract: A semiconductor memory device capable of reading out data at a higher speed and occupying a decreased chip-area is provided. The device includes a bit line selection circuit including a plurality of first transistors for selecting a plurality of bit lines according to a plurality of column selection signals generated based on address signals, a bit line charging circuit including a plurality of second transistors for charging the plurality of bit lines, respectively, and a bit line grounding circuit including a plurality of third transistors for connecting the plurality of bit lines with a ground potential. This enables the decrease in a charging time during a bit line precharging operation and a discharging time during data reading-out operation.

Abstract: A ROM including memory cells, the programmed cells being formed of a transistor connected between a bit line and a supply potential, the cells being organized in sets of at least one column coupled to one sense amplifier per set. The cell programming is inverted with respect to a desired programming only in specific sets where the desired programming would result in a number of programmed cells greater than the number of unprogrammed cells, the logic state provided by the sense amplifiers associated with the specific sets being inverted.

Abstract: A semiconductor memory device is provided with a memory cell array, a sense circuit which activates main bit lines in the memory cell array, a buffer which generates an activating signal which activates the sense circuit from a control signal, an address designating section which selects a memory cell indicated by an address signal among a plurality of memory cells in the memory cell array, and a delay circuit which delays the activating signal and outputting it to the sense circuit. The address designating section activates a word line to which a memory cell indicated by the address signal is connected after some delay from the activation of a chip enable signal.

Abstract: A semiconductor storage device of the present invention comprises a plurality of alternately arranged select lines and bit lines, a plurality of word lines arranged substantially orthogonal to the select lines and bit lines, a plurality of MOS transistors, having first electrodes connected to the select lines, second electrodes connected to the bit lines and control electrodes connected to the word lines, forming a plurality of memory cells, a first voltage supply circuit connected to the select lines for supplying a first voltage to the first electrodes, and a second voltage supply circuit connected to the bit lines and the select lines for supplying a second voltage, varying in compliance with variation in the first voltage, to the second electrodes.

Abstract: A semiconductor storage device of the present invention comprises a plurality of alternately arranged select lines and bit lines, a plurality of word lines arranged substantially orthogonal to the select lines and bit lines, a plurality of MOS transistors, having first electrodes connected to the select lines, second electrodes connected to the bit lines and control electrodes connected to the word lines, forming a plurality of memory cells, a first voltage supply circuit connected to the select lines for supplying a first voltage to the first electrodes, and a second voltage supply circuit connected to the bit lines and the select lines for supplying a second voltage, varying in compliance with variation in the first voltage, to the second electrodes.

Abstract: An improved memory architecture is described. The memory architecture includes separately controlled refresh and sense amplifiers to enable a memory access and refresh cycle simultaneously.

Abstract: A semiconductor storage device with high integration is capable of performing high speed access. The semiconductor storage device is constituted in such a way that it causes one contact to be connected with a primary bit-line, further it causes four sub bit-lines to be connected through four bank selection transistor, furthermore, it causes one contact to be connected to a virtual GND line, moreover, it causes two sub bit-lines to be connected through two bank selection transistors. The respective sub bit-lines are arranged in parallel to signal inputted to six bank selection lines, and in parallel to primary bit-line. Two virtual GND lines which are arranged at right and left of the primary bit-line. The memory cell transistor is capable of being selected according to combination of level of the two virtual GND lines. This causes bank selection lines to be reduced, further it causes cell array to be shortened in bit direction, furthermore, it causes cell array area to be reduced.

Abstract: A semiconductor memory cell device exhibiting superior cell reliability comprising a dual layer floating gate wherein the thin upper layer of the floating gate overlaps the edges of surrounding field insulating regions and has rounded edges to minimize leakage concerns. The tunnel dielectric separating the dual layer floating gate from the substrate comprises a layer of uniform thickness which is grown prior to the formation of the field insulating regions. The Fowler-Nordheim tunneling mechanism is used for programming and erasing the inventive cells in a programming process flow which comprises flash programming all cells on a word line, sensing current on a selected cell, and selectively erasing the charge on the cell by applying a higher voltage on the intersecting bit line than is applied to the word line, until the sensed current is as desired.

Abstract: A non-volatile, random access memory cell comprises first and second inverters each having an output node cross-coupled by cross-coupling means to an input node of the other inverter for forming a MOS RAM cell. The output node of each inverter is selectively connected via the conductor paths of separate access transistors to respective bit lines. The control electrodes of the access transistors are connected to a common word line. In particular, both RAM and programmable Read-Only operation of said memory cell are provided. Thereto, the cross-coupling comprises capacitors (C1, C2) each in series with a control electrode of a respective p-type transistor of the first and second inverters. This renders both interconnecting nodes between a capacitor and the gate electrode of its associated p-channel transistor floating. Isolators around these nodes render the cell data-retentive. The nodes are transiently and electrically programmable through signals on the bit and word lines of the cell.

Abstract: A semiconductor device has a plurality of basic units formed on a semiconductor substrate, each including a memory element and a logic element and having the same or bilateral symmetry structure. Each basic unit has a DRAM cell formed in a first active region, serially connected transistors of a logic element formed in a second active region and having second and third gate electrodes and source/drain regions with silicide layers, first and second signal lines connected to the source/drain regions of the transistor pair, a third signal line connected to the second gate electrode, and a conductive connection terminal formed under the storage electrode of a DRAM capacitor for connecting the storage electrode and third gate electrode. A semiconductor device is provided which has a plurality of basic units each including a memory cell and a logic cell formed on the same semiconductor substrate, the device being easy to manufacture and capable of high integration.

Abstract: A semiconductor memory device includes a plurality of bit lines; a plurality of virtual GND lines; and a plurality of memory cell transistors arranged in an array. The plurality of bit lines includes a selected bit line directly connected to a memory cell transistor to be read among the plurality of memory cell transistors and a non-selected bit line. The plurality of virtual GND lines includes a selected virtual GND line directly connected to the memory cell transistor to be read and a non-selected virtual GND line. The non-selected bit lines include a charge non-selected bit line to be charged and a non-selected dummy bit line to be grounded. The non-selected virtual GND lines include a charge non-selected virtual GND line to be charged. The non-selected dummy bit line is connected between the selected virtual GND line and one of the charge non-selected bit line and the charge non-selected virtual GND line.

Abstract: A read only memory integrated semiconductor device includes at least one memory cell. The memory cell includes a storage transistor made within a semiconductor substrate and whose source is connected to ground. A word line is connected to the gate of the transistor. Only one of several bit lines may be connected to the drain of the transistor at a time.

Abstract: The present invention provides a Via Code Mask read-only memory comprising an array of transistors, and a plurality of bit lines and word lines, wherein the transistors in each row of the array are connected in series by connection of a drain/source of one transistor with a drain/source of another transistor. Both ends of the series of the transistors in each row of the array are connected to a supply voltage together. Each one of the bit lines is selectively connected to drain(s)/source(s) of one or more transistors in one corresponding column. Each one of the word lines connects together gates of the transistors in one corresponding row.

Abstract: A semiconductor memory device includes an erase line, a common line, and a first transistor coupled between the conductive line and the common line. The memory device includes a plurality of memory cells and bit lines, each memory cell including a program line, a memory transistor, and a tunneling capacitor having a first node coupled to the floating gate. A second transistor is coupled between the program line and another node of the tunneling capacitor. An access transistor is coupled to the memory transistor and the bit line. The second transistor may be a depletion-type transistor, as may be the first transistor that is coupled to the erase line. The memory cell may also be implemented as a single-polysilicon memory structure.

Abstract: A ROM including columns of memory cells connected by columns to respective bit lines; a reference bit line; charge transistors controllable by a common charge line and respectively connecting the bit lines and the reference bit line to a high supply potential. The reference bit line is associated with a column of unprogrammed cells, and the memory includes means for activating the charge line before activation of a word line, the duration between the activation of the charge line and the activation of the word line, and the features of the charge transistors, being chosen so that the level variation of the bit lines is low as compared to the level of the high supply potential.

Abstract: In a semiconductor memory device, the drain of a transistor for pre-charging is connected to a data line via the Y switch. Lower level bit signals are input into an X decoder for selecting the word line in a memory cell array; and higher level bit signals are input into a Y decoder for selecting the Y switch control signal lines. The addresses in the memory cell array are arranged sequentially in the direction of the data lines.

Abstract: A read-only memory includes a semiconductor substrate; a memory cell matrix which is formed on the semiconductor substrate; and word and bit lines which define the locations of the memory cell matrix. The memory cell matrix includes field effect transistors, each of which turns off when accessed or addressed; and conducting regions, which keep conductive state all the time. Binary data stored in the memory cell matrix are determined by detecting current flowing through the selected bit line.

Abstract: An integrated circuit memory comprises an array of non-volatile memory cells arranged in rows and columns, and including a plurality of banks. There are a plurality of word lines along the plurality of rows in the array, and a plurality of array bit lines arranged along the plurality of columns. The array bit lines extend across the array, and include sense lines and ground lines. A plurality of bank bit lines is arranged along the plurality of columns. The bank bit lines extend across corresponding banks in the plurality of banks and are coupled to memory cells in the corresponding banks. A plurality of connection terminals are coupled to the array bit lines. For each array bit line there is at least one connection terminal per bank in the plurality of banks for which the array bit line will be used. A plurality of bank select transistors is provided to act as bank select circuitry.

Abstract: Mask ROMS with fixed code implantation and associated integrated circuits are described. An integrated circuit has a Mask ROM including: an array of memory cells including a first bank of memory cells and a second bank of memory cells, and the first bank of memory cells separated from the second bank of memory cell by a set of select lines, and the first bank of memory cells and the second bank of memory cells includes at least one fixed code implanted memory cell column. The use of fixed code implantation results in a single current path during the reading of a given memory cell and permits the size of the corresponding device to be reduced and have better topography.

Abstract: A read only memory (ROM) which is made up of an array and a current sensing circuit. The array is made up of a number of cells each cell being adapted for storing N bits. Each cell has an operative element which is of one of 2N sizes representative of a combination of N bits. The current sensing circuit is connected to the array and senses the size of the operative elements of the array. The current sensing circuit thus differentiates between the 2N sizes of the operative elements to determine the values of each bit of the N bits in each cell. N is an integer greater than 1.

Abstract: A method and apparatus for programmable read only memory with high speed differential sensing at low operating voltage. In one embodiment, a programmable memory cell is comprised of word line, a bitline, and a transistor. The transistor, representing a single binary digit (bit), has a gate coupled to a word line, a drain coupled to a bitline, and a source capable of being programmed to provide a logic level of 0 and a logic level of 1. By programming the source of the transistor, the bitline approximately equal capacitance for both logic level 0 and logic level 1 states.

Abstract: A multivalued mask ROM is configured by arranging cell transistors in a matrix form, which is defined by wiring word lines and ground lines in rows and by wiring bit lines in columns. Each of the cell transistors is encompassed by a word line, a ground line and at least two bit lines. Herein, gates of the cell transistors which align in a same row are connected with a same word line, while sources and drains of the cell transistors are adequately connected or disconnected with the ground line and bit lines. In an integrated circuit, contacts are formed between n+ regions, first-layer metal and second-layer metal on a well region to establish connections by which the source and drain of the cell transistor are adequately connected with the ground line and/or bit lines. That is, ROM codes are formed using the contacts. A circuitry is provided for the multivalued mask ROM to read out stored information of the cell transistors in synchronization with a clock signal.

Abstract: A non-volatile semiconductor memory decreases a parasitic current as much as possible without using an electric separation means. This nonvolatile semiconductor storage apparatus has multiple memory cells rows having multiple memory cell transistors M1, M2 . . . whose gates are connected to word lines WL1, WL2 . . . , respectively, and whose sources and drains are serially connected. This non-volatile semiconductor storage apparatus also has multiple column lines SBL0, SVL0, SVL1, SBL1 . . . which connect the connection nodes between the sources and drains of the memory cell transistors M1, M2 . . .

Abstract: A non-volatile memory cell comprising a metal oxide semiconductor field effect transistor (MOSFET) fabricated to read back a logic level “one” state and programmable by a gate to drain fusing to read back to a logic level “zero” state. The drain is patterned to enhance the formation of a localized hot spot during device lateral NPN transistor snapback for a controlled meltdown of gate oxide and the creation of an ohmic gate to drain path. A metal oxide semiconductor (MOS) integrated circuit typically includes a plurality of memory cells composing a programmable array. The drains of each memory cell are tied together in parallel and connected to a high-level programming voltage, and the sources are tied to ground.

Abstract: The disclosed is a read only memory having a plurality of memory blocks each associated with main bit lines and sub-bit lines, and a plurality of memory cells for storing information, and sense amplifiers for reading the information stored in the memory cells through the main bit lines. The memory also has a block selection part disposed between the blocks and having a plurality of block selection transistors connecting the main bit lines to the sub-bit lines. The sub-bit lines elongate to at least an adjacent block and alternatively connected to the main bit lines through the block selection part.

Abstract: This semiconductor memory device is provided with a plurality of main bit lines; a main bit line controller for controlling whether to impress a specific voltage on the main bit lines, connect the main bit lines to a sense amplifier, or place the main bit lines in the OPEN state, based on an address signal; a plurality of virtual main grounding lines; and a virtual main grounding line controller for controlling whether to impress a specific voltage on the virtual main grounding lines, impress a grounding voltage on the virtual main grounding lines, or place the virtual main grounding lines in the OPEN state, based on an address signal.

Abstract: A reading circuit for a multibit memory cell in a memory array, the memory cell having a threshold gate voltage within a range of one of a first, second, third and fourth predetermined threshold voltages corresponding respectively to one of four states of two bits stored in the memory cell. The reading circuit includes a circuit to provide a gate voltage to the multibit memory cell during a read cycle, the gate voltage having a first level between the second and third predetermined threshold voltages during a first time interval of the read cycle and a second level between the third and fourth predetermined threshold voltages during a second time interval of the read cycle.

Abstract: The present invention provides a method of writing a set of binary codes into a ROM. The method is performed by forming a first photo mask and a second photo mask according to an original first code pattern, an original second code pattern, and a set of binary codes to be written into the ROM. Final first and second code patterns are formed by coupling the binary codes to be written with the original first and second code patterns by using a Boolean logical OR operation. The first and second photo masks are formed according to the final first and second code patterns. The first photolithographic process is performed using the first photo mask, and the first ion implantation process is performed; the second photolithographic process is performed using the second photo mask, and the second ion implantation process is performed. Thus the set of binary codes is written into the ROM completely and correctly.

Abstract: A reading circuit for a multibit memory cell in a memory array, the memory cell having a threshold gate voltage within a range of one of a first, second, third and fourth predetermined threshold voltages corresponding respectively to one of four states of two bits stored in the memory cell.

Abstract: In an EEPROM including a plurality of NAND memory cells each constituted by connecting memory cells each having a floating gate and a control gate in series with each other, first selection transistors respectively coupled between the same bit line and terminals, on one side, of each pair constituted by two NAND memory cells of the plurality of memory cells, and second selection transistors respectively coupled between terminals on the other side and source lines (SL), the first or second selection transistors are constituted by an enhancement transistor and a depletion transistor which are coupled in series with each other, and the arrangements of the depletion transistor and enhancement transistor of the first selection transistors are reversed to those of the second selection transistors in the same NAND memory cells.

Abstract: A method and apparatus for programmable read only memory with high speed differential sensing at low operating voltage. In one embodiment, a programmable memory cell is comprised of word line, a bitline, and a transistor. The transistor, representing a single binary digit (bit), has a gate coupled to a word line, a drain coupled to a bitline, and a source capable of being programmed to provide a logic level of 0 and a logic level of 1. By programming the source of the transistor, the bitline approximately equal capacitance for both logic level 0 and logic level 1 states.

Abstract: A memory circuit which uses multiple storage mechanisms in each of its memory cells. In one embodiment, the memory circuit includes an array of cells in which each cell has multiple storage elements. At least one of the storage elements performs its function in a different way than the rest of the storage elements. This use of multiple storage mechanisms allows for a greater freedom in memory cell design and allows for the simultaneous storage of multiple states in a single memory cell. Broadly speaking, the present invention contemplates a memory core comprising an address decoder, an array of cells, and a sense amplifier. The address decoder is configured to receive an address and responsively assert a selected word line. The array of cells includes a selected cell coupled to the selected word line, and each cell in the array of cells includes at least two storage elements.

Abstract: In a semiconductor memory device including memory cells, first and second decoders generate first and second selection signals, and a driver circuit generates a drive signal for driving the memory cells. The driver circuit includes a transfer gate, controlled by the first selection signal, thus passing the second selection signal to generate the drive signal.

Abstract: A dynamic random access memory solves long-existing tight pitch layout problems using a multiple-dimensional bit line structure. Improvement in decoder design further reduces total area of this memory. A novel memory access procedure provides the capability to make internal memory refresh completely invisible to external users. By use of such memory architecture, higher performance DRAM can be realized without degrading memory density. The requirements for system support are also simplified significantly.

Abstract: An enhanced word line driver circuit suitable for use on integrated circuits such as flash memory devices with voltage boosting includes a load reduction circuit. In response to a boosted voltage, the load reduction circuit decouples a gate capacitance load of deselected enhanced word line drivers from the boost voltage generator. The reduction of capacitive loading decreases power consumption and shortens the voltage boost time of the memory device.

Abstract: A static RAM memory cell (30) uses cross-coupled enhancement mode, N-channel MOS drive transistors (36) to form a bistable flip-flop. A load circuit (34) couples between I/O ports (40) of the drive transistors (36) and Vcc. For each drive transistor (36), the load circuit includes a depletion mode, N-channel MOS load transistor (54) and a forward biased tunnel diode (32). The drain and gate of the load transistor (54) couple across the anode and cathode of the tunnel diode (32) so that the forward voltage (V.sub.f) of the tunnel diode (32) controls the V.sub.gs transfer curve (56) of the load transistor.