Abstract: As a specific application of a new memory architecture, an array of non-volatile dual floating gate memory cells is arranged on a semiconductor substrate with global bit lines extending in a column direction that are either permanently connected, or connectable through transistor switches, to short source and drain diffusions that are oriented in the row direction between the global bit lines. Multiple columns of memory cells are positioned between the global bit lines. Bit selection lines oriented in the column direction are connected to the gates of select transistors within the memory cells. Word lines individually extend over one or two rows of floating gates. This arrangement provides a very small array that allows for future scaling. It also enables the use of metal lines strapped to the global bit line diffusions, and to polysilicon word lines to reduce their resistance, without imposing their larger pitch on other array elements.

Abstract: A read-only memory device having a NOR structure is provided. The memory device comprises a memory cell array having a plurality of memory cells, each memory cell storing data, a plurality of first bit lines coupled to the array, and a plurality of second bit lines coupled to the array. A first selection circuit are coupled to the plurality of first bit lines for selecting at least two adjacent first bit lines. A second selection circuit coupled to the plurality of second bit lines for selecting at least two adjacent second bit lines. A sense amplification circuit detect a cell state of a selected memory cell by biasing the selected first bit lines and one of the selected second bit lines with a same potential. The second selection circuit grounds another of the selected second bit lines. The first selection circuit grounds unselected first bit lines and wherein the second selection circuit grounds unselected second bit lines.

Abstract: A flat-cell ROM array reduces the number of transistors utilized to read a memory cell, allows for the layout of straight metal lines, while sharing the metal lines between even and odd cells, and achieves very high density and high performance. Parallel buried diffusion regions are implanted in the substrate. A gate oxide is laid over the substrate. A plurality of polysilicon word lines are laid over the gate oxide perpendicular to the buried diffusion regions, so that the areas between respective pairs of buried diffusion regions and under the polysilicon word lines, form columns of flat cell field effect transistors. An insulating layer is laid over the polysilicon word lines and a plurality of metal bit lines and virtual ground lines are formed. These metal lines are shared by even and odd columns of field effect transistors. Access to metal lines is made through a plurality of block select transistors connected to every other buried diffusion bit line.

Abstract: A compact read-only memory (ROM) system with low current consumption and having a plurality of data lines and a word line, includes a first ROM cell having a gate connected to the word line and a source-drain path connected between a first data line and a second data line, a second ROM cell having a gate connected to the word line and a source-drain path connected between the second data line and a third data line, a third ROM cell having a gate connected to the word line and a source-drain path connected between the third data line and a fourth data line, and a sense amplifier for amplifying data from one of the ROM cells. The first data line is connected to a voltage source and the second data line is connected to the sense amplifier when data from the first ROM cell is read, and the third and fourth data lines are charged to a predetermined voltage.

Abstract: A semiconductor multivalued read only memory device stores multivalued data in a memory cell array and multivalued reference data in reference cell arrays, and stepwise changes word lines and reference word lines to different active levels for reading out the multivalued data and the corresponding multivalued reference data at different timings so as to determine the value of each multivalued datum by comparing it to the multivalued reference data without undesirable influence of deviated threshold and unintentionally deviated active level.

Abstract: The disclosure is a read only memory having a memory cell array formed of a plurality of memory cells coupled to wordlines and bitlines, the bitlines being alternately connected to main bitlines and ground lines. The invented read only memory include an address transition detection signal source. It also includes a first delay circuit for receiving the address transition detection signal and for generating a first discharge signal for driving the ground lines. It also includes a second delay circuit for receiving the address transition detection signal and for generating a second discharge signal for driving the main bitlines. It also includes a first pulse circuit for receiving the first discharge signal and for generating a first precharge signal for driving the ground lines. Finally, it includes a second pulse circuit for receiving the second discharge signal and for generating a second precharge signal for driving the main bitlines.

Abstract: A memory device including a first set of memory cells, a second set of memory cells having preprogrammed states, and a circuit configured to access data included in a first segment of memory cells. When data is read from the second set of memory cells the circuit includes an enable signal to determine whether the data outputted by the second set of memory cells is preprogrammed data or data stored during normal operation. For one embodiment, data written into or retrieved from the memory cells is performed in a consistent fashion between the first set of memory cells and the second set of memory cells.

Abstract: A manufacturing method and a structure for ROM component having a silicon controlled rectifier as the basic memory instead of a channel transistor in a conventional ROM, and using a formation of contact windows for coding a ROM instead of performing an ion implantation process. Also, since a silicon controlled rectifier occupies a smaller component surface area, the level of integration is correspondingly increased. Furthermore, due to interposition of an insulating layer between two bit lines, short circuiting between the adjacent bit lines is prevented. The component of this invention operates by applying a suitable voltage to the word line electrode and the bit line electrode respectively to select a particular memory unit, and as a result, a current will flow in a vertical direction through the memory unit, exit through the common electrode depending on the ON/OFF state of the memory, and be detected there.

Abstract: A non-volatile memory cell is provided that includes a low voltage CMOS storage transistor having a source region and a drain region that are commonly connected to ground. The low voltage storage transistor is programmed by applying a high programming voltage to its gate, thereby rupturing the gate oxide of the storage transistor. The high programming voltage is applied to the low voltage storage transistor through a high voltage p-channel transistor. The high voltage p-channel transistor has a thicker gate oxide than the storage transistor, thereby enabling the p-channel transistor to withstand higher voltages. The high voltage p-channel transistor also has a higher breakdown voltage than a high voltage n-channel transistor of the same size. Both the low voltage storage transistor and the high voltage p-channel transistor are fabricated in accordance with a standard sub 0.35 micron process.

Abstract: Memory cells are organized in cell fields in word lines and bit lines in the manner of a matrix. The bit lines are actuated by a bit decoder for loading with a mass potential, and by a blocking decoder for loading the bit lines with a blocking potential. The word lines are actuated by a word decoder for loading the word lines with a programming voltage or a protective voltage. The information value to be programmed is prestored in the cell field.

Abstract: The present invention, generally speaking, provides compact ROM layouts for trace or via-programmable (e.g., metal programmable) using transistor stacks. A number of field effect transistors (for example, eight) are coupled in series. For a particular transistor, a logic zero is programmed by forming a metal trace between the source and drain of the transistor. To read out the value of a particular bit, a logic zero is applied to the gate of the corresponding transistor. Logic ones are applied to the gates of the remaining transistors in the stack. A logic one precharge signal is applied to the top and bottom of the stack. A logic zero is then applied to the bottom of the stack. The logic zero reaches a sense amplifier coupled to the top of the transistor stack only if there is a short circuit across the transistor being read, indicating a logic zero bit value. Otherwise, the precharged logic one condition remains.

Abstract: A mask ROM of the invention discharges bit lines selectively before a bit line precharge operation in response to an externally applied command. A column decoder selects one of bit lines in response to column select signals. A discharge control circuit generates a first discharge control signal in response to the command. A discharge predecoder generates a plurality of second discharge control signals by logically combining the first discharge control signal with the column select signals. A bit line discharge circuit selectively discharges the bit lines in response to the second discharge control signals. The mask ROM is free from bit line coupling due to the selection of particular memory cells, the cell selection sequence and the programmed states of the selected cells, leading to an improvement in read speed.

Abstract: A reference voltage generator may include an input for receiving a first voltage for input to a sense amp. The reference voltage generator may also include an output for outputting a second voltage for input to the sense amp. The second voltage is influenced by the first voltage. Alternatively, a reference voltage generator may include a first input for receiving a first voltage on a first bitline. The reference voltage generator may also include a first output for outputting a second voltage on a second bitline. The second voltage is influenced by the first voltage. Alternatively, a reference voltage generator may include a first input for receiving a first voltage on a first transmission busline. The voltage generator may also include a first output for outputting a second voltage on a second transmission busline. The second voltage is influenced by the first voltage.

Abstract: A column of read-only-memory (ROM) cells is programmed to store two or more bits of information in each cell by forming a plurality of coding (bit) lines adjacent to the column of cells, and selectively connecting the cells to the plurality of coding lines so that the different logic conditions defined by the two or more bits are represented by the coding lines that are connected to a memory cell.

Abstract: A method of permanently programming selected cells of dynamic random access memory cell array. First selected cell is programmed to a Logic 1 by grounding a first capacitor plate of the first cell, and applying a programming voltage to a second capacitor plate common to the cells of the array. A dielectric disposed between the first capacitor plate and the second capacitor plate breaks down, thereby shorting the first and second capacitor plates. A second selected cell is programmed to store a Logic 1 by allowing a first capacitor of the second cell to float during a period when the programming voltage is applied to the second capacitor plate.

Abstract: A read-only memory (ROM) device of the type including an array of diode-based memory cells for permanent storage of binary-coded data. The ROM device is partitioned into a memory division and an output division. The memory cells are formed over an insulating layer in the memory division. The insulating layer separates the memory cells from the underlying substrate such that the leakage current that can otherwise occur therebetween can be prevented. Moreover, the coding process is performing by forming contact windows at selected locations rather than by performing ion-implantation as in conventional methods. The fabrication process is thus easy to perform. Since the memory cells are diode-based rather than MOSFET-based, the punch-through effect that usually occurs in MOSFET-based memory cells can be prevented. The diode-based structure also allows the packing density of the memory cells on the ROM device to be dependent on the line width of the polysilicon layers in the ROM device.

Abstract: To realize a type of mask ROM which can minimize the increase in the area while shortening the manufacturing cycle time. Multiple ROM memory cells with memory data stored in them corresponding to the presence/absence of via contacts are set in a matrix configuration between different metal wiring layers; the memory cells of the same row are connected to the same word line, the memory cells of the same column are connected to the same bit line; in addition, on each memory cell row, the gates are connected to the word line corresponding to that row, and the diffusion layer is connected to the diffusion layer of the adjacent diffusion transistor.

Abstract: A ROM memory array comprises a doped silicon substrate having a surface with a first array of parallel bitlines formed in the substrate at the surface with an array of channel regions between the bitlines. A dielectric layer is formed on the substrate with a wordline array composed of transversely disposed parallel conductors formed on the dielectric layer, with the bitlines and the channel regions and the wordline array forming an array of field effect transistors. A gate oxide layer is formed over the wordlines. A thin film polysilicon storage plane is formed over the gate oxide layer with a second array of alternating parallel bitlines and channel regions formed in the thin film polysilicon storage plane. The second array of bitlines and channel regions is orthogonally disposed relative to the wordline array and the second array of bitlines is formed in a storage plane over an interpolysilicon oxide dielectric isolation layer.

Abstract: A stacked ROM device utilizes the same conductivity type for the ROM cells in both the top and the bottom ROM cell matrixes. The stacked ROM device comprises a first ROM cell matrix which comprises conductively doped source and drain lines having a first conductivity type in a semiconductor substrate having a second conductivity type. For example, the source and drain lines are implemented with n-type doping in a p-type substrate. A second ROM cell matrix comprises conductively doped source and drain lines having the first conductivity type in a semiconductor layer which overlies and is isolated from the semiconductor substrate. A plurality of shared wordlines is disposed between the first and second ROM cell matrixes. A plurality of bit lines is isolated from and overlies the semiconductor layer.

Abstract: A DRAM cell is provided which includes a read bit line capable of being precharged to a first voltage level, a write bit line capable of carrying data, a read word line capable of being asserted at a second voltage level, and a write word line capable of being asserted at about the first voltage level. A first switching device having an enable input is coupled between the read bit line and the word read line. A second switching device having an enable input coupled to the write word line is coupled between the write bit line and the enable input of the first switching device.

Abstract: In a semiconductor memory device including a plurality of memory cells, in which when an address of any one of the memory cells is input, data is read out from the memory cell corresponding to the address so as to be output, the semiconductor memory device includes null addresses having no corresponding memory cells; and predetermined data is output in response to input of the null addresses.

Abstract: A static, in-circuit programmable memory device is provided where the storage element employed is a bi-layer programmable resistor. A specialized programming and readout circuit is provided for each storage element, allowing a known word-line/bit-line memory architecture (commonly used with fuse type memories) to be adapted to a memory element that conducts in both of two different states. The programming and readout circuit may take the form of a merged bipolar/FET device. A bipolar transistor is used for programming and also provides a diode action to prevent sneak path currents from flowing when a storage element is not selected. The bipolar transistor may be a parasitic bipolar transistor. An FET is used for readout. Storage elements are paired, one storage element of each pair functioning as a reference element.

Abstract: A programming or function-setting cell for a field programmable gate array utilizes ferroelectric capacitors connected to the nodes of a latch circuit to retain charge representing the state of the cell so that, following a power loss or a specific event upset, the programming information held by the latch circuit may be reinstated. The latch circuit comprises a pair of inverters having their inputs and outputs cross-coupled by way of respective switching transistors, and the capacitors are connected between the nodes and a common plate conductor normally held at a potential intermediate the supply potentials for the inverters.

Abstract: A memory device including a first block of random access memory (RAM) cells having preprogrammed states, a second block of random access memory cells, and a select circuit configured to reset the first block of RAM cells to their preprogrammed states. When the first block of memory cells are reset to their preprogrammed states, the first block of memory cells may function as ROM memory cells that may be accessed at RAM speeds. The first block of RAM cells may not require additional nonvolatile circuitry in order to perform the ROM function; rather, the first block of RAM cells may each be configured to operate as both a volatile and nonvolatile memory cell using the same cell structure. For one embodiment, the select circuit alters the power applied to the first block of RAM cells to cause these RAM cells to perform a ROM function.

Abstract: A nonvolatile memory cell (600) has a read device (510), program device (515), and tunnel diode (535). A write control line (WC) is directly coupled to the tunnel diode (535). The memory cell (500) may be used to form compact arrays of memory cells to store logical data. During programming of a selected memory cell, half-select voltages are used on the write control (WC) and control gate lines (CG) for unselected memory cells to prevent disturb and minimize oxide stress.

Abstract: A memory cell architecture utilizing a dual access gate and dual wordlines is disclosed. The cell is comprised of a first transistor connected between a digitline and a cellplate. The transistor is responsive to a read wordline to enable the cell to be read. An active device, such as a second transistor, is provided for modifying at least one conductive characteristic of the first transistor according to the state of a signal on the digitline. The conductive characteristic that is modified may be, for example, the threshold voltage or the transistor's channel resistance. Modification of the first transistor's characteristics is representative of writing information to the memory cell. A circuit structure for implementing the circuit architecture is also disclosed together with a method of operating a memory cell.

Abstract: A microcomputer includes dedicated output transistors for driving a bus for access to an external memory. The output transistors are smaller in size than transistors for other input/output ports. The microcomputer and the external memory are interconnected through a double-sided printed-circuit board forming a multi-chip module (MCM). The module has pin assignments substantially the same as those of a single-chip microcomputer. Selector circuits are included in the module to test specifically the external memory connected to the selectors.

Abstract: Low power consuming circuitry for amplifying sensed signals in memory devices is disclosed. The low power circuitry includes a amplifier circuit having a data bus line for receiving a data signal from a selected column of a memory array. The data bus line being coupled to a first pre-charger transistor for limiting a data bus voltage swing, and a virtual ground control line for controlling a virtual ground application to a selected column of the memory array. The virtual ground application configured to provide a path to ground for the selected column, and the virtual ground control line being coupled to a second pre-charger transistor for limiting a virtual ground voltage swing. Further included is a gain transistor configured to receive the data signal from the data bus line and provide an amplified data signal to a pull down node located at an input of an inverter. And, a digital data output node located at an output of the inverter.

Abstract: A memory device includes a random access memory (RAM) cell accessible through a RAM wordline and coupled between first and second bitlines; a read only memory (ROM) cell accessible through a ROM wordline and having an output coupled to the first bitline and an input configured to receive a first voltage signal; and a reference voltage generator having a first input coupled to the first bitline, a second input configured to receive the first voltage signal, and an output coupled to the second bitline. The memory device may further include a bitline load having an output coupled to the first bitline. A virtual ground driver configured to produce the first voltage signal may be coupled to the input of the read only memory cell. Further, column select pass gates configured to be under the control of a logic signal and having a first input coupled to the first bitline, a second input coupled to the second bitline, a first output and a second output may be provided.

Abstract: A column of an integrated memory circuit includes two bit lines each with a right half and a left half and a plurality of similar memory cells connected to each half of each bit line. One of the memory cells connected to each line is used as a reference and the other cells are used for data storage. Each half of each bit line is connected to a sense node of a sense amplifier latch through an independently controlled transistor switch. To read the data from the first half of the first bit line, the transistors connecting the first half of the first bit line to the sense node is turned on and the transistor connecting the second half of the first bit line to the sense node is turned off. Both transistor switches connecting respective halves of the other bit line to the other sense node are turned on. Each half of each bit line includes approximately the same effective load. The load applied to the first sense node is thus about half of the load applied to the second sense node.

Abstract: An improved storage circuit that allows multiple bits to be encoded and stored using a single storage element. The encoded information is defined by a coupling made between a transistor as the storage element and any one of several bit lines associated with the transistor. When the coupled bit line is discharged in response to a wordline signal, the stored information can be captured by an encoder. The circuit is particularly useful for efficiently storing information in a gate array integrated circuit, because the gate array has more space around each transistor to add bit lines than a conventional, densely packed, ROM.

Abstract: A memory precharge voltage, VPC, is provided which tracks changes in the high voltage supply, VDD, according to a measured degree, which maintains a precharge voltage notwithstanding transient loads which may tend to draw the precharge voltage down, and which maintains the precharge voltage at the operating level notwithstanding the fact that the precharge generator is substantially turned off during a power down condition. The precharge voltage, VPC, is then used as the controlling input signal to a circuit which it generates and an internal control voltage, MLC, used to drive small pull-up current FETs coupled to the bit lines in the ROM core. The internal control signal MLC is generated to track the discharge current in a bit line within the memory core, to track VPC, and to be maintained at its operating voltage level even when the MLC current is substantially turned off during a power down condition.

Abstract: A nonvolatile memory cell which is highly scalable includes a cell formed in a triple well. A select transistor can have a source which also acts as the emitter of a lateral bipolar transistor. The lateral bipolar transistor operates as a charge injector. The charge injector provides electrons for substrate hot electron injection of electrons onto the floating gate for programming. The cell depletion/inversion region may be extended by forming a capacitor as an extension of the control gate over the substrate between the source and channel of said sense transistor.

Abstract: A memory accessible in read mode only comprises storage elements designed to contain a bit that can assume two levels. Each memory cell comprises a transistor. The transistor of the storage element may include an associated circuit portion to prompt a short circuit between the drain and the source of the transistor if the storage element has to contain one bit at one of the two levels. Furthermore, the use of an unbalanced differential amplifier permits an improvement of the access time of the memory.

Abstract: The semiconductor memory device of the invention includes: a semiconductor substrate; a first block; a second block adjacent to the first block; a main bitline; a first auxiliary conductive region; a first select transistor; and a first select line.

Abstract: A mask ROM is so configured as to read out information through the utilization of a cumulative time delay involved when a read-out signal applied to memory elements making connection between a word line WL1 and bit lines BL1 crossing the word line is passed through delay elements R1 to R7, that is, as to read out stored information on a time base, in which the conductions of switching transistors T1 to T8 are controlled by the outputs of the delay elements R1 to R7 and the information appearing at the bit line BL1 is sequentially read out at a predetermined time corresponding to a time delay resulting from the delay elements R1 to R7.

Abstract: A semiconductor memory device with a contactless array structure has bit-lines formed in a semiconductor substrate by diffusion of an impurity. Word-lines (control gates) are formed on the substrate so as to intersect the bit-lines. Floating gates are disposed in intersecting regions between the bit- and word-lines. Regions of higher resistance extend in parallel to the bit-lines located on both sides of a floating gates and located in an offset manner relative to the floating gate. A thick dielectric film is formed between the regions of higher resistance and word-lines. In this semiconductor memory device, a source side injection method with higher efficiency can be utilized for electron injection to a floating gate (programming) and thereby a lower programming voltage, less power consumption, and higher degree of integration are achieved.

Abstract: A flat NOR type mask ROM includes a plurality of bit-lines that are parallel to each other, a plurality of memory cells provided between adjacent bit-lines and a plurality of word-lines that are parallel to each other and orthogonal to the bit-lines, each word-line being connected to a plurality of the memory cells. The memory cells provided every predetermined number of bit-lines are OFF-cells which are always in an OFF state regardless of a potential level of the respective word-line.

Abstract: A matrix memory with improved virtual ground architecture and evaluation circuit from which the informational content of two neighboring memory cells can be simultaneously read at a bit line during a read event. The memory cells with information "0" are realized, for example, by a respective field effect transistor with low threshold voltage. Every bit line provided for the readout is connected to the drain terminals of two neighboring field effect transistors in the same row. The source terminals are applied to one of two potentials that differ from one another. Depending upon which of the field effect transistors is conductive upon selection of the pertinent word line, different resultant potentials are obtained on the bit line. Such potentials are then converted in the evaluation circuit into binary signals that represent the read information.

Abstract: The read only memory includes a number of word lines and a number of bit lines. The word lines and the bit lines are arranged in a matrix. Between every two of the bit lines and on every word line there forms a memory cell. The two bit lines of the memory cell are a first bit line and a second bit line. The method of programming includes the following steps. The first bit line is supplied with a first voltage. The second bit line is supplied with a second voltage. The word line is supplied with a third voltage. Bit lines at the same side of the first bit line are supplied with the first voltage. Bit lines at the same side of the second bit line are supplied with the second voltage.

Abstract: A semiconductor mask-programmable read-only-memory array structure provides double density storage of data information by means of thin film memory cell transistors formed on both sides of a layer of thin film polysilicon. At a bottom surface of a layer of thin film polysilicon which has a bottom gate oxide grown thereon, a plurality of polysilicon bottom cell wordlines intersects a plurality of bitlines to form an array of bottom cell memory transistors. The bitlines are heavily-doped diffusion regions within the layer thin film polysilicon. Additionally, a top surface of the layer of thin film polysilicon has a top gate oxide grown thereon. Over this top gate oxide, a plurality of polysilicon top cell wordlines intersects the plurality of bitlines to form an array of top cell memory transistors, thereby producing a NOR-type read-only-memory array structure with double the storage density of conventional, prior art structures.

Abstract: The invention concerns a multi-valued read-only storage location which is constructed symmetrically for storing a first or second state (M, M"') and asymmetrically for storing at least a third state (M', M"). The advantage thereof is above all that the storage capacity is doubled without notably increasing expenditure and without impairing the signal-to-noise ratio with respect to conventional storage locations. The invention is suitable for electrically programmable and mask-programmable read-only memories, in particular for those used in low voltage technology.

Abstract: In a "flat cell" read-only memory with a matrix of memory cells, each memory cell is a MOSFET of either a low threshold voltage, which can be turned on when accessed, or a high threshold voltage which cannot be turned on when accessed. Each memory cell is connected between two adjacent columns of local bit lines. These local bit lines are alternately connected to a upper bank selection switch which is connected to a main bit line, and a lower bank selection switch, which is connected to a main virtual ground line. Since these local bit lines are fabricated with diffusion layers which are resistive, the path length, hence the resistance, to access any memory cell in the matrix from the main bit line to the main virtual ground is made the same by this alternate, interdigital local bit line layout. Thus, the access time is made uniform.The layouts of two adjacent banks are mirrored, so that the bank selection switches of two adjacent banks can share a common selection line.

Abstract: A semiconductor read-only memory (ROM) device is provided. The particular semiconductor structure of this ROM device can reduce the parasitic capacitance between the bit lines and the word lines, such that the resistance-capacitance time constant of the memory cells can be reduced to thereby speed up the access time of the read operation to the memory cells. The binary data stored in each memory cell is dependent on whether one contact window is predefined to be formed in a thick insulating layer between the buried bit lines and the overlaying word lines. If the gate electrode of one memory cell is electrically connected to the associated word line via one contact window through the insulating layer, that memory cell is set to a permanently-ON state representing a first binary value; otherwise, that memory cell is set to a permanently-OFF state representing a second binary value.

Abstract: In a semiconductor storage device, a potential corresponding to a position of a word line selected from the memory cell array is applied to a bank selection line which is connected to the gate of a bank selection transistor, as an ON potential for the bank selection transistor so that it is possible to reduce the variation in the bit line potential depending upon the position of a memory cell in a bank of a ROM using a bank system.

Abstract: A memory cell (400) for storing data on an integrated circuit. The memory cell (400) is static, nonvolatile, and reprogrammable. The layout of the memory cell is compact. In a first state, the logic output from this memory cell (400) is at about voltage level at a first conductor (505); and in a second state, the logic output is at about a voltage level at a second conductor (510). The memory cell (400) of the present invention includes a first programmable memory element (515) and a second programmable memory element (520). First programmable memory element (515) is coupled between the first conductor (505) and a sensing node (405). Second programmable memory element (520) is coupled between the sensing node (405) and the second conductor (510). In the first state, first programmable memory element (515) is not programmed, while the second programmable memory element (520) is programmed.

Abstract: A semiconductor memory which includes first and second memory cells, wherein the first memory cells include first MOS transistors each having impurity diffused layers provided inside of both of a source and a drain to expanding source and drain regions, the second memory cells include second or third MOS transistors each having an impurity diffused layer provided inside of one of a source and a drain or include fourth MOS transistors each having no impurity diffused layer provided inside of either thereof, as well as a method for fabricating the semiconductor memory. Differences in threshold voltage between the first and second to fourth MOS transistors are utilized as differences in storage status between the first and second memory cells so that data "0" or "1" is stored in each memory cell.

Abstract: The present invention discloses a mask ROM having a pipeline structure using simple latch circuits. Accordingly, the mask ROM according to the present invention improves its speed and guarantees the security of the output data, by proving a clock generator and a plurality of latch circuit for storing the outputs from each of the element therein, being synchronized with the internal clock signal from the clock generating means.

Abstract: To make a memory system highly integrated, a memory system includes a memory cell array including a first unit block and a second unit block having a plurality of read-only memory (ROM) cells, a plurality of diffused lines having a first pitch with respect to each other, and connected to sources of the ROM cells, first and second bit lines made of metal and respectively connected to drains of the ROM cells in the first and second unit blocks, and first and second source lines made of metal and respectively connected to sources of the ROM cells in the first and second unit blocks. A pitch between the first bit line and the first source line is a first pitch and a pitch between the first bit line and the second source line, and a pitch between the second bit line and the second source line are a second pitch. The second pitch is at least three times larger than the first pitch.

Abstract: When a data bit is read out from a semiconductor read only memory device, a current-mirror type sense amplifier is electrically connected through a bit line, a first selector, a selected memory cell and a second selector to a discharging line so as to check a potential drop on the bit line, and each of the first and second selectors selectively connects the bit line or the discharging line to eight columns of memory cells by increasing the component switching transistors thereof so as to space the bit line from the discharging line, thereby increasing a margin for a bit line contact.