Abstract: A semiconductor integrated circuit device includes a storage element, program circuit, and sensing circuit. The storage element stores information by electrically irreversibly changing the element characteristics. The program circuit programs the storage element by electrically irreversibly changing its element characteristics. The sensing circuit senses the irreversibly changed element characteristics of the storage element in distinction from an unchanged state. The program circuit includes a high-voltage generator which irreversibly changes the element characteristics of the storage element by applying a high voltage to it, and a current source which supplies an electric current to the storage element having element characteristics changed by the high-voltage generator, thereby stabilizing the element characteristics.

Abstract: Methods and apparatus for decreasing oxide stress and increasing reliability of memory transistors are disclosed. Duration and frequency of exposure of memory transistor gates to read signals are significantly reduced. In some embodiments, after a short read cycle, the content of the memory cell is latched and maintained as long as the subsequent read attempts are directed to the same memory cell. In these embodiments the read cycle need only be long enough to latch the memory content of the cell, and as long as the subsequent read attempts target the same memory cell the latched value will be used instead of repeating the read process.

Abstract: An SRAM device includes a memory cell. The memory cell includes a first cross-coupled inverter and a second cross-coupled inverter, which is electrically connected to the first cross-coupled inverter. Each inverter includes a pull down device and a pull up device. The pull up device is electrically connected to the pull down device. A channel width ratio of the pull up device to the pull down device is preferably within a range of about 1.5 to about 0.8. A channel area ratio of the pull up device to the pull down device is preferably within a range of about 3 to about 1. A pass gate device is electrically connected to the pull down device. A channel width ratio of the pull up device to the pass gate device is preferably within a range of about 3.0 to about 1.2.

Abstract: Data encoding system and method for implementing robust non-volatile memories. A data bit is stored using two memory cells. The data bit is represented by setting a voltage level of a first memory cell to a first voltage level and setting a voltage level of a second memory cell to a second voltage level. In one embodiment, the first voltage level and the second voltage level are of opposite polarity. In one embodiment, to store a data bit having the value “0,” the first memory cell is set to a first voltage level and the second memory cell is set to a second voltage level of opposite polarity to the first voltage level, and to store a data bit having the value “1,” the first memory cell is set to a third voltage level and the second memory cell is set to a fourth voltage level of opposite polarity to the third voltage level.

Abstract: A method of programming a radiation-hardened integrated circuit includes the steps of supplying a prototype device including an SRAM memory circuit or programmable key circuit to a customer, having the customer develop working data patterns in the field in the same manner as a reading and writing to a normal RAM memory, having the customer save the final debugged data pattern, delivering the data pattern to the factory, loading the customer-developed data pattern into memory, programming the customer-developed data pattern into a number of production circuits, irradiating the production circuits at a total dosage of between 300K and 1 Meg RAD to burn the data pattern into memory, and shipping the irradiated and programmed parts to the customer.

Abstract: Each memory cell of an EPROM contains two MOSFETs and a data of each memory cell is read out by detecting a current difference between the two MOSFETs by using a differential amplifier. In such constitution as described above, even when the data is erased by irradiating an ultraviolet ray, a stable output of the differential amplifier can be obtained and, therefore, confirmation of an initialized state can be facilitated. Specifically, a channel width WA of one of the two MOSFETs constituting the memory cell is formed narrower than a channel width WB of the other. By such arrangement as described above, in an initialized state in which the ultraviolet ray is irradiated, a data signal current value IHA of the MOSFET having the channel width WA becomes smaller than a data signal current value IHB flowing in the MOSFET having the channel width WB. Accordingly, the output of the differential amplifier is fixed in accordance with a current magnitude relation of IHA<IHB, to thereby define a data “0”.

Abstract: A semiconductor memory device includes a memory cell unit including at least one semiconductor memory cell, a voltage generating circuit which produces an operating voltage to which reference is made in performing a predetermined operation on the memory cell unit. The device further includes a constant-current circuit capable of a current trimming operation and adapted to supply a constant current to the voltage generating circuit.

Abstract: A contactless Mask ROM is described, comprising a plurality of MOS-type memory cells. The memory cells include a plurality of first memory cells and a plurality of second memory cells. The first memory cells have a first channel conductivity so that they are depletion-mode MOS transistors, and the second memory cells have a second channel conductivity so that they are enhanced-mode MOS transistors. In the contactless Mask ROM, a memory cell shares two diffusions with two adjacent memory cells that are aligned with the memory cell along a first direction.

Abstract: A mask ROM includes bit lines, word lines intersecting with the bit lines and bit cells provided along the word lines, each of the bit lines being formed of a cell transistor having a gate connected to an associated one of the word lines. In the mask ROM, further provided is a source node commonly connected to respective sources of ones of the cell transistors having a gate connected to one of adjacent two word lines. A current flows from a selected bit line to a non-selected bit line via a cell transistor selected in reading out data and the source node.

Abstract: A high-density memory device and design method that utilizes some or all of the existing stacked process conductor layers provided by a manufacturing process to enhance the number of available bitlines and/or wordlines within the memory device. The memory device includes a plurality of memory cells arranged in columns and rows, a plurality of wordlines, a plurality of bitlines, at least one via-stack, wherein said existing stacked process conductor layers are used to implement at least one additional wordline or bitline. The via-stacks consist of a plurality of vias, are located close to a memory cell, and adapted to electrically connect the memory cell to multiple bitlines or multiple wordlines or both0. This design method increases the number of possible connections to or from each individual memory cell. When this design method is combined with varied configurations of basic underlying ROM cell types, even further increased cell density can be achieved.

Abstract: Methods and apparatuses prevent overtunneling in nonvolatile floating gate memory (NVM) cells. An individual cell includes a circuit with a transistor that has a floating gate that stores charge, and a capacitor structure for extracting charge from the gate, such as by tunneling. A counteracting circuit prevents extracting charge from the floating gate beyond a threshold, therefore preventing overtunneling or correcting for it. In one embodiment, the counteracting circuit supplies electrons to the floating gate, to compensate for tunneling beyond a point. In another embodiment, the counteracting circuit includes a switch, and a sensor to trigger the switch when the appropriate threshold is reached. The switch may be arranged in any number of suitable ways, such as to prevent a high voltage from being applied to the capacitor structure, or to prevent a power supply from being applied to a terminal of the transistor or to a well of the transistor.

Abstract: An upside-down MRAM comprises a sense transistor and a plurality of sense lines. A first end of the sense transistor is electrically connected to a low voltage. The sense lines are electrically connected in parallel between a high voltage and a second end of the sense transistor. Each of the sense lines has a control logic and at least one memory bit, and the memory bit is connected in series between the high voltage and the control logic.

Abstract: A random access memory including an array of single transistor memory cells and a voltage source. The voltage source is configured to receive a boosted supply voltage and a reference voltage. The voltage source is configured to provide an output voltage out of the boosted supply voltage and based on the reference voltage.

Abstract: A mask ROM small in circuit scale and low in consumption power has an n-type select transistor having a drain connected to a corresponding one of bit lines, a source connected to a data line, and a gate having a corresponding one of select signals input thereto. A p-type precharge transistor has a drain connected to a corresponding one of bit lines, a source connected to a power line, and a gate having a corresponding one of the select signals input thereto. Because the bit line is precharged by using a precharge transistor opposite in conductivity type to the select transistors, it is satisfactory to provide one precharge transistor for one bit line, greatly reducing the circuit scale.

Abstract: A method and apparatus are provided for reducing leakage current in a read only memory device. Leakage current is reduced by reducing the duration of the precharge cycle during each read cycle so that the associated leakage current will flow for a shorter time period during each cycle. The precharge phase is positioned at the beginning of each read cycle, prior to the evaluation phase. The precharge phase is terminated by a subsequent clock edge or by an internal time out prior to a subsequent clock edge. The time interval between when the columns reach their precharge voltage and the evaluation phase begins is reduced.

Abstract: A read-only memory arrangement and method for programming the memory arrangement are provided. The memory arrangement includes memory cells, which each have a transistor with two contacts and a control terminal, address lines, bit lines and a potential line. A combination of one of the address lines and one of the bit lines is uniquely assigned to each memory cell. The control terminal of each transistor is connected to the address line assigned to the respective memory cell. To program a memory cell into a first memory state, one of the contacts of the transistor of the memory cell is connected to the assigned bit line and the other of the contacts is connected to the potential line. To program a memory cell into a second memory state, no connections are established between the contacts of the transistor and either the assigned bit line or the potential line.

Abstract: In a flat-cell ROM including a plurality of memory banks, each of the memory banks comprises a memory array, a plurality of bit lines, a plurality of virtual ground lines, three select lines, and a common row of contacts shared with an adjacent memory bank. The common row of contacts are used for connecting the bit lines and virtual ground lines to bit signal lines and virtual ground lines, respectively, and the select lines are used for selecting memory cells in the memory array. With a common row of contacts shared by two adjacent banks, the ROM area is reduced.

Abstract: Methods and apparatus for accessing modules on a flash memory package concurrently during testing are disclosed. According to one aspect of the present invention, a memory device for storing data includes a plurality of modules and a logic block. The plurality of modules each include a plurality of storage elements that hold the data. The logic block is arranged to enable the plurality of modules to be accessed in parallel, and is also arranged to enable the plurality of modules to be accessed serially.

Abstract: Crosspoint memory arrays utilizing one time programmable antifuse cells are disclosed.

Abstract: Structures and methods of adding metal-to-metal capacitors to static memory cells to reduce susceptibility to SEUs. The addition of metal-to-metal capacitors is particularly suited to programmable logic devices (PLDs), because of the relatively large area required to implement an effective metal-to-metal capacitor, compared (for example) to the size of the static memory cell itself. The configuration memory cells of PLDs are typically placed next to other logic (e.g., the configurable elements controlled by the configuration memory cells) that can be overlain by the metal-to-metal capacitors. Therefore, metal-to-metal capacitors can be used in PLD configuration memory cells where they might be impractical in simple memory arrays. However, metal-to-metal capacitors can also be applied to integrated circuits other than PLDs.

Abstract: A p-channel non-volatile memory (NVM) transistor is programmed by shifting the threshold voltage of the transistor. The threshold voltage is shifted by introducing a programming current to the gate electrode of the transistor, and simultaneously introducing a negative bias to the transistor. The threshold voltage of the p-channel NVM transistor is shifted in response to the negative bias condition and the heat generated by the programming current. The high temperature accelerates the threshold voltage shift. The threshold voltage shift is accompanied by an agglomeration of material in the gate electrode. The agglomeration of material in the gate electrode is an indication of the high temperature reached during programming. The threshold voltage shift of the p-channel NVM transistor is permanent.

Abstract: A method and apparatus are provided for reducing leakage current in a read only memory device. Leakage current is reduced by applying a biased gate voltage (relative to a source voltage) to the gate of at least one of transistor in the array. The biased gate voltage is applied at least during a precharge phase of a read cycle. When the array transistors are n-channel transistors, the biased voltage is a negative bias voltage (relative to the source voltage). When the array transistors are p-channel transistors, the biased voltage is a positive bias voltage (relative to the source voltage). Applying a negative backgate bias to the transistor's p-well contact can also reduce n-channel transistor subthreshold leakage current. Thus, for an n-channel array, a negative gate voltage and backgate bias (optional) are applied to cell transistors in the off state.

Abstract: A memory cell structure of a metal (or via) programmable ROM whereby a transistor is shared between bit cells of the programmable ROM. Such a memory cell structure may include: a word line; a bit line; first and second virtual grounding lines; a grounding line; a first bit cell selected by signals of the word line and the first virtual grounding line; and a second bit cell selected by signals of the word line and the second virtual grounding line, wherein a cell transistor, one side of which is connected to the bit line is shared both by the first and second bit cells. Also, the other side of the cell transistor may be floated or connected to the bit line or, alternatively, connected to any one of the first virtual grounding line, the second virtual grounding line and the grounding line, and the gate of the cell transistor is connected to the word line.

Abstract: A semiconductor integrated circuit includes a substrate, a digital circuit formed on a triple well formed in the substrate, a first node configured to supply a well potential of the digital circuit, a second node separate from the first node, and a substrate-potential supplying circuit, formed on the substrate, having an input node to receive an input potential from the second node and an output node to supply a substrate potential to the substrate, the substrate-potential supplying circuit having no direct-current path into which a direct current substantially flows through the input node, and configured to generate at the output node an output potential following the input potential.

Abstract: The invention concerns a ROM circuit (40) including columns of storage cells, each column being connected to a bit site (BLi, BLi+1), wherein the columns are arranged in groups of two adjacent columns, each column of a group capable of being selectively activated relative to the other column of the group, thereby enabling the elimination of a connection to the ground of columns and the design of efficient reading amplifiers.

Abstract: Read only memory(ROM) integrated circuit devices include a ROM cell block. A plurality of virtual ground lines and bit lines are coupled to the ROM cell block. A precharge circuit, including a virtual ground line precharge controller, virtual ground line precharging unit, bit line precharge controller and bit line precharging unit, independently controls timing of precharging the virtual ground lines and the bit lines. The precharge circuit may be configured to deactivate precharging of the virtual ground lines before deactivating precharging of the bit lines. Precharging of the virtual ground lines may be deactivated substantially concurrently with activation of discharging of the virtual ground lines.

Abstract: A method and apparatus are provided for reducing leakage current in a read only memory device. Leakage current is reduced by precharging only a portion of the columns in a read only memory array during a given read cycle. The portion of the columns that are precharged is limited to a subset of columns that includes those columns that will be read during a given read cycle. A read column address is decoded to precharge only the portion of the columns of transistors that will be read during the given read cycle. The columns of transistors can be grouped into a plurality of sub-arrays and only those sub-arrays having columns that will be read during a given read cycle are precharged during the read cycle.

Abstract: A method of determining an optimal reading voltage for reading a two-side non-volatile memory programmed with a threshold voltage Vt is described. A first side of a memory cell is programmed to Vt, and then an I1-Vg curve of the first side and an I2-Vg curve of the second side are measured, wherein Vg is the gate voltage. A Gm1-Vg curve and a Gm2-Vg curve are plotted, wherein Gm1=dI1/dVg and Gm2=dI2/dVg. The optimal reading voltage VgO is determined as the gate voltage at the intersection of Gm1 and Gm2, corresponding to a maximal total current window Wm (=I2(VgO)?I1(VgO)).

Abstract: The present invention relates to bit cell arrays of read-only-memories, and more specifically, to a bit cell array capable of preventing a coupling effect between adjacent bit lines. In addition, the bit cell array according to the present invention does not require an additional device in order to prevent the coupling effect. In accordance with the present invention, the bit cell array comprising: a plurality of bit lines arranged in a row in a first direction; a plurality of ground lines in a row in a second direction vertical to the first direction; a plurality of word lines arranged with a zigzag line with respect to the second direction; and a plurality of ROM bit cells partially formed at a cross-section point of the bit lines and the word lines. In the meanwhile, the ROM bit cells are arranged with a zigzag line with respect to adjacent bit lines. Additionally, the ROM bit cells comprise a drain terminal, a gate terminal and a source terminal.

Abstract: A p-channel non-volatile memory (NVM) transistor is programmed by shifting the threshold voltage of the transistor. The threshold voltage is shifted by introducing a programming current to the gate electrode of the transistor, and simultaneously introducing a negative bias to the transistor. The threshold voltage of the p-channel NVM transistor is shifted in response to the negative bias condition and the heat generated by the programming current. The high temperature accelerates the threshold voltage shift. The threshold voltage shift is accompanied by an agglomeration of material in the gate electrode. The agglomeration of material in the gate electrode is an indication of the high temperature reached during programming. The threshold voltage shift of the p-channel NVM transistor is permanent.

Abstract: A compact mask programmable read-only memory (Mask ROM) is described, comprising a plurality of word lines, a plurality of bit lines, and a plurality of MOS-type and diffusion-type memory cells arranged in an array. The memory cells in one column are coupled to one bit line, and the gates of the MOS-type cells in one row are coupled to one word line via contacts, wherein two columns of memory cells share a column of contacts. A MOS-type cell shares its source and drain with two memory cells in the same column, and a diffusion-type cell directly connects with the diffusions of two adjacent memory cells. A constant number of continuous memory cells are grouped as a memory string, wherein the two diffusions of the two terminal memory cells are electrically connected to a bank select transistor and a ground line, respectively.

Abstract: A array of multi-bit Read Only Memory (ROM) cells is in a semiconductor substrate of a first conductivity type with a first concentration. Each ROM cell has a first and second regions of a second conductivity type spaced apart from one another in the substrate. A channel is between the first and second regions. The channel has three portions, a first portion, a second portion and a third portion. A gate is spaced apart and is insulated from at least the second portion of the channel. Each ROM cell has one of a plurality of N possible states, where N is greater than 2. The state of each ROM cell is determined by the existence or absence of extensions or halos that are formed in the first portion of the channel and adjacent to the first region and/or in the third portion of the channel adjacent to the second region. These extensions and halos are formed at the same time that extensions or halos are formed in MOS transistors in other parts of the integrated circuit device, thereby reducing cost.

Abstract: A virtual ground memory with low and fixed pre-charge loading is provided. First metal lines GL(n?1), GL(n), and GL(n+1) and second metal lines BL(n?1) and BL(n) are disposed in the sequence GL(n?1), BL(n?1), GL(n), BL(n) and GL(n+1). Each first metal line and the adjacent second metal line are coupled respectively to two ends of the corresponding memory cell. Word lines are used for controlling memory cells. The second metal lines BL are in high level when the memory cells which the second metal lines BL are coupled to are chosen. A first and second sense amplifier are coupled to the second metal line BL(n?1) and BL(n) respectively, and the first metal lines GL(n?1) and GL(n+1) are coupled to ground level. One of the word lines is enabled to read the corresponding memory cells. A virtual ground memory loading can be fixed by this invention.

Abstract: The present invention relates to an improved read only memory device. The read only memory device includes a read only memory cell array with a plurality of first read only memory cells and a plurality of second read only memory cells. A reference memory cell array includes a plurality of first reference memory cells and at least one second reference memory cell. A dummy memory cell array includes a plurality of first dummy memory cells and a plurality of second dummy memory cells. A reference word line selecting circuit selects the reference word line responsive to a row address.

Abstract: A phase random access memory including a plurality of access transistors, each access transistor including a drain region, and a phase-changeable film shared by the plurality of access transistors. The phase-changeable film is connected to a bitline through a first electrode and connected to each respective drain region through at least one of a plurality of second electrodes.

Abstract: A array of multi-bit Read Only Memory (ROM) cells is in a semiconductor substrate of a first conductivity type with a first concentration. Each ROM cell has a first and second regions of a second conductivity type spaced apart from one another in the substrate. A channel is between the first and second regions. The channel has three portions, a first portion, a second portion and a third portion. A gate is spaced apart and is insulated from at least the second portion of the channel. Each ROM cell has one of a plurality of N possible states, where N is greater than 2. The state of each ROM cell is determined by the existence or absence of extensions or halos that are formed in the first portion of the channel and adjacent to the first region and/or in the third portion of the channel adjacent to the second region. These extensions and halos are formed at the same time that extensions or halos are formed in MOS transistors in other parts of the integrated circuit device, thereby reducing cost.

Abstract: A method and structure for a read only memory (ROM) cell array has the first drain of a first transistor connected to a true bitline and a second drain of a second transistor connected to a complement bitline. The first transistor also includes a first source, and the second transistor includes a second source. The connection of the first source or the second source to ground programs the ROM cell. With the invention, only the first source or the second source is connected to the ground and the other is insulated from electrical connections. Further, the connection of the source to ground comprises an electrical connection formed during manufacturing of the first transistor and the second transistor.

Abstract: The present invention prevents a reading operation margin from being decreased due to a current injected into a selected bit line after passing through an unselected bit line in a memory cell array configuration using virtual ground lines. A memory cell array is constituted by being divided into at least subarrays of a plurality of columns and memory cell columns at the both ends of the subarrays are constituted so that second electrodes are not connected each other but they are separated from each other between two memory cells adjacent to each other in the row direction at the both sides of boundaries between the subarrays and respectively connected to an independent bit line or virtual ground line, and one of word lines, one of bit lines, and one of virtual ground lines are selected and one memory cell from which data will be read is selected.

Abstract: A method of programming a radiation-hardened integrated circuit includes the steps of supplying a prototype device including an SRAM memory circuit or programmable key circuit to a customer, having the customer develop working data patterns in the field in the same manner as a reading and writing to a normal RAM memory, having the customer save the final debugged data pattern, delivering the data pattern to the factory, loading the customer-developed data pattern into memory, programming the customer-developed data pattern into a number of production circuits, irradiating the production circuits at a total dosage of between 300K and 1 Meg RAD to burn the data pattern into memory, and shipping the irradiated and programmed parts to the customer.

Abstract: A memory cell stores data permanently in a memory material that can assume a first, high-resistance state and a second, low-resistance state, that is in a phase-changeable or ovonic material. A heating device is disposed to heat the memory material at different rates to a programming temperature. The memory material either has a high resistance or a low resistance after cooling, depending on the heating rate. The heating device has a switching device and a heating element in immediate vicinity to the memory material. The switching device has a field-effect transistor and a drain region of the field-effect transistor forms the heating element. Alternatively, the heating element includes a diode or a diode chain.

Abstract: A semiconductor memory component such as a mask-programmable ROM component, has two memory cell transistors adjacent to each other in one column of a memory cell field. First and a second row-select/potential-equalization lines are equidistant from the two memory cell transistors and vertically above a diffusion region, which is assigned to both memory cell transistors. The first or the second row-select/potential-equalization line can be connected both to the word line of the first memory cell transistor and to the word line of the memory cell transistor of the second memory cell for equalizing the potential with one of the two word lines.

Abstract: A half-density ROM embedded DRAM uses hard programmed non-volatile cells and unprogrammed dynamic cells. By hard programming either a first or second memory cell in a pair of cell, different data states are stored. Two word lines are used to access the memory cell pair. Because one of the cells is hard programmed, sense amplifier circuitry identifies the appropriate data state. The ROM cell can be programmed in numerous different manners. For example, ROM cells can be hard programmed by eliminating cell dielectric to short cell plates to a program voltage, or an electrical plug can be fabricated between the cell plates and shorted to a program voltage. In other embodiments, the ROM cell can be programmed using an anti-fuse programming technique, or by providing a high leakage path (not full short) such as through an active area to the substrate.

Abstract: The present invention relates to a programmable memory device and a method of setting a state for a programmable memory device. In at least one embodiment, the memory device comprises at least a level shifter adapted to stand off a high programing voltage to at least one fuse element in the memory device, wherein the high programming voltage is used to set a state of the memory device.

Abstract: A programmable circuit and its method of operation are disclosed in which a transistor is used as a programmable element. The transistor may be programmed to one of two different gate threshold voltage values for operation. During reading of the transistor, a gate threshold voltage between the two values is applied and the status of the transistor as on or off is determined to determine the program state of the transistor. The program state of the transistor can be determined by a simple latch circuit.

Abstract: Disclosed is a ROM device with a repair function where defective cells are repaired by a bit cell unit. The defective cells are repaired using a ground or operating (e.g., a supply) voltage line incorporated in the ROM device. This allows the defective cells to be repaired without separate redundant cells. After repairing, a test operation for replaced cells is not needed.

Abstract: The present invention provides a read-only memory (ROM) architecture. An exemplary ROM array includes a plurality of columns, a plurality of rows, a first plurality of transistors or other switches representing a “0” data state or low voltage state, and a second plurality of transistors or other switches representing a “1” data state or high voltage state. Each transistor has a corresponding drain coupled to a column and a gate coupled to a row. Each transistor of the first plurality has a source coupled to a source voltage bus, and each transistor of the second plurality has a source not coupled to the source voltage bus, through use of a programmable contact window during fabrication. In various embodiments, for a selected column, drains of pair-wise adjacent transistors share a common drain-column contact and common diffusion region.

Abstract: The present invention provides a read-only memory array having a flat-type structure. The read-only memory array comprises at least two memory banks having a plurality of memory cells. At least two inter-bank transistors are coupled to the two memory banks and shared by the two memory banks. Each inter-bank transistor is used for enabling to select the memory cells of the two memory banks. At least a contact commonly is coupled to the two memory banks through the two inter-bank transistors.

Abstract: A multi-bit Read Only Memory (ROM) cell has a semiconductor substrate of a first conductivity type with a first concentration. A first and second regions of a second conductivity type spaced apart from one another are in the substrate. A channel is between the first and second regions. The channel has three portions, a first portion, a second portion and a third portion. A gate is spaced apart and is insulated from at least the second portion of the channel. The ROM cell has one of a plurality of N possible states, where N is greater than 2. The possible states of the ROM cell are determined by the existence or absence of extensions or halos that are formed in the first portion of the channel and adjacent to the first region and/or in the third portion of the channel adjacent to the second region. These extensions and halos are formed at the same time that extensions or halos are formed in MOS transistors in other parts of the integrated circuit device, thereby reducing cost.

Abstract: A read only memory (ROM) embedded dynamic random access memory (DRAM) has a 6F2 architecture and uses isolation gates as hard shorting connections for ground or supply voltage connections to program ROM bits within the ROM embedded DRAM.

Abstract: A memory array including a conductive line adapted to simultaneously conduct current in at least two distinct directions relative and adjacent to a magnetic junction is provided. In some embodiments, one of the distinct directions may be substantially aligned with an elongated dimension of the magnetic junction, while another of the distinct directions may be substantially aligned with a shortened dimension of the magnetic junction. In yet other embodiments, at least one of the distinct directions may be aligned at an angle between approximately 0 degrees and approximately 90 degrees relative to an elongated dimension of the magnetic junction. In either case, a memory array is provided which includes a contiguous conductive line having a first portion arranged above a magnetic junction of the memory array and a second portion arranged below the magnetic junction. In addition, a method for operating such a magnetic memory array is provided.