Abstract: The present invention features a ROM memory cell with a non-uniform threshold voltage. The ROM memory cell includes a channel region divided into several channels deposed in parallel along the axial direction of carrier transport. Afterwards, one code-implant procedure is performed to program the memory cell to store one of multiple states, thereby constituting a multiple-state ROM, the fabrication of which does not require multiple photolithography as well as multiple implantation processes.

Abstract: A programming of memory cells in an upper block (UB) is reversely made, thereby obtaining reverse data which are opposite to desired data when the upper block (UB) is selected. An inverter circuit (IV) is additionally provided at an output of a sense amplifier (SA1) and inverts the reverse data, thus eventually obtaining the desired data. Having such configuration as to reduce the number of ON/OFF controllable memory cells, a semiconductor memory device which cuts power consumption is provided. Moreover, with OFF-state memory cells having such configuration as to suppress application of load (charge) capacity to bit lines and word lines as much as possible, the semiconductor memory device which ensures high-speed access to the memory cells is provided.

Abstract: The present invention is related to an enhanced high density Read-Only-Memory (ROM) device with select gate. A thin oxide layer is deposited on the ROM cell matrix and it is extended to the select lines which is on the top and bottom side of the ROM cell matrix to form the select gate. The ROM cell matrix can be organized more flexible by using the buried layers to pick out the unwanted gates. The metal contact can be directly made in this extended region too. Thereafter it reduces the manufacturing cost and achieves a high speed and density and simple process device.

Abstract: A ROM (read only memory) is disclosed. For via-ROMs, an isolation transistor is used to isolate adjacent pairs of memory devices instead of the more conventional field oxide isolation. The gate of the isolation transistor is grounded, insuring that conduction does not take place. For a GASAD ROM, a field oxide isolation is used.

Abstract: A semiconductor device which is capable of storing n-bits in a unit cell by providing said cell with a set of 2.sup.n -1 (n.gtoreq.2) word-lines and switching means connected or not connected to one of the word-lines and by reading data from a unit cell on the basis of an address designated by an activated word-line and a change of a signal in a bit-line according to the activated word-line.

Abstract: A three-dimensional ROM device includes a silicon substrate having plurality of parallel trenches formed in an upper surface thereof, and a plurality of raised mesa regions. Each trench has a bottom and a pair of sidewalls, and is separated from an adjacent trench by a respective mesa region. A plurality of separated, parallel source/drain regions are provided, including a first and second source/drain region located on respective opposite sides of a respective trench bottom, and a third and fourth source/drain region located on respective opposite sides of a respective raised mesa region. Each source/drain region serves as a bit line. A gate oxide layer is located on the upper surface of the silicon substrate. A plurality of sidewall oxide layers are formed on selected sidewalls and serve as channel barriers. A plurality of silicon nitride layers are formed above selected mesa regions and trench bottoms, and serve as channel barriers.

Abstract: A system and process which enables storage of more than two logic states in a memory cell. In one embodiment, a programmable resistor is coupled in series with a transistor between a supply voltage and a data read line. When an access signal is asserted, the transistor provides a conductive path, and a voltage drop is sustained by the programmable resistor. The programmable resistor has a resistance which is set during a programming step to one of a plurality of values by passing a heating current through the programmable resistor for one of a corresponding plurality of predetermined lengths of time. When the access signal is asserted, the voltage drop sustained across the programmable resistor is indicative of the stored logic state. An analog-to-digital (A/D) converter is coupled to the data read line so as to sense the voltage drop and determine the state represented.

Abstract: A redundancy memory cell array is arranged at an end of a main memory cell array in the column direction. Common bit lines and common column lines are arranged on the main memory cell array and the redundancy memory cell array. A disconnection circuit is arranged between the main memory cell array and the redundancy memory cell array for connecting or disconnecting bit lines or column lines. A column selection switch is arranged at an end of the redundancy memory cell array. A redundancy circuit disconnects bit lines or column lines by means of a disconnection circuit when an address signal specifies a defective address.

Abstract: An embedded ROM has a column of static RAM cells attached to the end of the row lines. When a row of ROM cells is activated by the row line, a RAM cell is also activated by the row line. The RAM cell indicates if the data in the selected row's ROM cells is valid. When the RAM cell indicates that the ROM data is not valid, external memory is read to obtain a patched instruction and the ROM data is ignored. The ROM's base address is translated to a base address in external memory of patch code. The ROM's offset address is used as the offset into the patch-code region of external memory. Thus address translation is minimal as the offset is not translated. A single ROM instruction can be updated by a single patch instruction in external memory, providing fine granularity of code updates. Longer update routines can be located in a patch-code overflow region of external memory.

Abstract: A semiconductor memory apparatus able to operate at a low voltage and thus preventing an increase of the operating current during charging and discharging. NMOS transistors are connected to the power supply line and bit lines, and the gates thereof are connected to a precharge signal supply line. PMOS transistors are connected to the connection points of the bit lines and sense amplifiers and the supply line of the power supply voltage. The gates thereof are connected to the precharge signal supply line through inverters. Transfer gates are connected to the connection points of the bit lines and the NMOS transistors. The gates thereof are connected to the column switch signal supply line. Only one bit line of the selected column is precharged to the power supply voltage level. The other bit lines are held at the predetermined low potential.

Abstract: A mask ROM with increased memory capacity is disclosed. Besides MOS transistors each comprising a memory cell, MOS field shield transistors for device isolation, originally provided for electrically isolating the memory cell transistors, are also used as additional memory cells in addition to providing their isolating function. To write data in one of the field shield transistor, the threshold voltage of the field shield transistor is lowered, compared to field shield transistors in other regions. This is done by ion implantation of an n-type impurity into a p-type silicon substrate in a region beneath a gate electrode of the field shield transistor (a channel region). Data is read by judging on/off of the transistors when an intermediate voltage, between a high threshold voltage and a low threshold voltage is applied to a field shield line.

Abstract: A semiconductor memory device according to the present invention includes: a memory cell array including a plurality of virtual ground lines, a plurality of bit lines, and a plurality of memory cells arranged in a matrix shape; a selection circuit; a first amplifier circuit; a second amplifier circuit; and a first control circuit and a second control circuit. The first control circuit and the second control circuit selectively charge or discharge those of the plurality of virtual ground lines corresponding to one page in accordance with the input address, the first control circuit and the second control circuit performing the charging or discharging independently of each other.

Abstract: Each column in the memory array of transistors of a programmable read only memory (ROM) can be programmed in either a conventional mode or an inverted mode. In the conventional mode, each transistor is either programmed (i.e., connected to the corresponding bit line) or unprogrammed (i.e., left unconnected to the corresponding bit line). In this way, the programming mode can be selected, independently for each column, to limit the maximum number of transistors that can be programmed in any given column to one half of the total number of transistors in the column. As such, the total capacitance along a bit line is reduced and the access time is therefore also reduced, resulting in a faster ROM. The information as to which columns are encoded using which programming modes is contained in a component of the ROM. That programming-mode information is accessed when reading data out of the memory array to determine whether or not to invert the data for the various columns.

Abstract: NMOS transistors which are provided adjacently to each other in the direction of the formation of bit lines between word lines are paired. The drains of the NMOS transistors are connected in common through a common node to form a memory cell. Between the common node and the bit line is provided a region where a contact is placed. Furthermore, regions where the contact is placed in the respective NMOS transistors are provided on a layout. By these combinations, data are stored.

Abstract: A semiconductor memory device which has a reduced current consumption. A memory block includes a pair of memory cell columns each of which includes a plurality of memory cells connected in series, the memory cell columns being connected in series in a column direction along which the memory cells are arranged, a position of each of the memory cells being indicated by address data comprising first address data and second address data. Each of a plurality of word lines is connected to a corresponding one of the memory cells included in the memory block on a one to one basis. A memory cell column selection decoder selects one of the memory cell columns based on the first address data. A word line selection decoder selects one of the word lines based on the second address data and a control signal which is logically equivalent to the first address data. Additional memory blocks may be arranged in a row direction perpendicular to the column direction.

Abstract: A multi-level memory cell structure, and a method of fabrication thereby is disclosed. In a mask ROM memory device, the conventional binary data storage cell is replaced with a 16-level data storage cell. The 16-level cell is programmed with a selected one of 16 values by forming a void in a portion of the word line over the memory cell having one of 16 widths corresponding to the preselected code to be stored therein. The portion of the word line associated with the coded memory cell has an effective remaining width corresponding to the preselected code. When the memory cell is enabled by activating its associated word line, due to the variable width of the word line forming the gate of the memory cell, one of 16 discrete currents flow in the 16-level memory cell structure. The current is indicative of the preselected code stored in the cell.

Abstract: A semiconductor read only memory device includes memory cells arranged in a matrix of rows and columns; word lines crossing the matrix, wherein one word line is connected to each row of memory cells; and bit lines interdigitated with column lines and positioned such that each column of memory cells is between a bit line and a column line. The matrix is subdivided into cells, where each cell has four memory cells arranged symmetrically about a bit line in two rows and two columns. All four of the cells are connected to the bit line at a common electrical node, wherein selected cells are connected to a column line. The memory device also includes a row select driver for selecting memory cells in a single row; a column select driver for selecting a single column line; and circuitry for selecting one of the bit lines adjacent to a column line.

Abstract: A ROM cell array in which the drains are more lightly doped than the sources. This reduces the worst-case capacitance seen by the bitlines, and consequently reduces the access time of the memory.

Abstract: A matrix memory with memory transistors arranged in rows and columns. The memory transistors can be addressed via word lines and bit lines. Control transistors are driven via control lines. The control transistors can short-circuit all of the columns of the cell array, i.e. the bit lines, except for the column in which a memory cell is located which is to be read out.

Abstract: In a semiconductor storage device, a potential corresponding to a position of a word line selected from the memory cell array is applied to a bank selection line which is connected to the gate of a bank selection transistor, as an ON potential for the bank selection transistor so that it is possible to reduce the variation in the bit line potential depending upon the position of a memory cell in a bank of a ROM using a bank system.

Abstract: A non-volatile semiconductor device can be obtained which is capable of enhancing integration level and performing accurate control of operations. A memory cell transistor of the semiconductor device in accordance with the present invention has a gate dielectric film including a ferroelectric film between a gate electrode and a semiconductor region. A back electrode is formed at the semiconductor region in a position corresponding to the gate electrode. A channel is formed at a channel formation region of the semiconductor region by applying a voltage to the back electrode, and the ferroelectric film is polarized as desired by the difference in potential between the channel and the gate electrode. Information can thus be written into the memory cell.

Abstract: A semiconductor memory device and a method for manufacturing the same are disclosed. The device includes a plurality of active regions repeatedly formed extending in parallel to each other, a device isolation region, a plurality of first gate electrodes repeatedly arranged being perpendicular to the active region and device isolation region, a source/drain region formed by being self-aligned ion-implanted into the first gate electrode, active region, and device isolation region, and a second gate electrode located between the first gate electrodes, extending in parallel to the first gate electrode, sharing the source/drain with the first gate electrode, and using the device isolation region as a channel. Thus, cell integration can be enhanced, and high speed operation and excellent yields can be easily ensured.

Abstract: A memory cell array of high density, enabling high speed read-out. Diffusion wires columnwise extending in a block in the array serve as bit and ground lines alternately disposed and gate wires parallel to each other are formed perpendicularly to the diffusion wires. Channels are defined in regions between the adjacent diffusion wires under the gate wires, whereby MOS transistors are formed. A memory circuit has such a memory cell array and a decoder connected thereto. Paired adjacent bit lines are connected through a bit line select transistor to a contact, and the contact is connected through a metal line columnwise connecting between blocks, via a transistor of decoder to a main bit line. Paired adjacent ground lines are connected through a ground line select transistor to a contact for ground line, and the contact is connected through a metal line columnwise connecting between blocks, via a transistor of decoder to a main ground line.

Abstract: Low power consuming circuitry for amplifying sensed signals in memory devices is disclosed. The low power circuitry includes a amplifier circuit having a data bus line for receiving a data signal from a selected column of a memory array. The data bus line being coupled to a first pre-charger transistor for limiting a data bus voltage swing, and a virtual ground control line for controlling a virtual ground application to a selected column of the memory array. The virtual ground application configured to provide a path to ground for the selected column, and the virtual ground control line being coupled to a second pre-charger transistor for limiting a virtual ground voltage swing. Further included is a gain transistor configured to receive the data signal from the data bus line and provide an amplified data signal to a pull down node located at an input of an inverter. And, a digital data output node located at an output of the inverter.

Abstract: The invention provides an electrically erasable and programmable nonvolatile memory having a plurality of memory cells (M1 to M8) connected in series to each other to form a NAND type flash memory array. Each of the memory cells is constructed of a floating gate, a control gate, a source region, a drain region and a channel region. Each of the memory cells is formed in a semiconductor film (3a) formed on an insulating substrate. Further, a plurality of control transistors (T1 to T8) for transmitting a voltage applied to one end of NAND array to a selected memory cell in the selective writing mode are formed of a side wall of the semiconductor film. Each of the control transistors is connected in parallel to an associated one of the memory cells.

Abstract: A semiconductor memory element is disclosed which can share the terminals easily among a plurality of memory elements and can pass a high current and which is strong against the noises. In order to accomplish this a control electrode is formed to cover the entirety of thin film regions connecting low-resistance regions. As a result, the element can have a small size and can store information with high density. Thus, a highly integrated, low power consumption non-volatile memory device can be realized with reduced size.

Abstract: A semiconductor memory includes a memory transistor having a gate connected to a word line and having a threshold level selected from a plurality of threshold levels, and a plurality of comparison transistors having gates are respectively connected to the word line, each of the comparison transistor having a threshold level selected from the reference threshold levels and the threshold levels of the comparison transistor being different from each other. The word line is driven respectively to a plurality of voltage levels, and whenever they are driven to respective values of the plurality of voltage levels, the logical level state determined based on the difference between the current flowing in the memory transistor and the current flowing in the transistor circuit is held, and multibit data stored in the memory transistor is output based on the logical level state held.

Abstract: For a nonvolatile multi-stage semiconductor memory device, a data reading sequence is given first, second, and third phases. During the first phase, a word line is driven to 2.25 V with a differential amplifier and a bias circuit activated to sense on or off of a selected memory cell. During the second phase, the word line is driven to 3.0 V with a differential amplifier and a bias circuit activated to sense on or off of the selected memory cell. This enables correct read out with a low operating voltage, such as 3.0 V, of data stored in semiconductor memory cells with a selected one of four threshold levels given to each datum. During the third phase, it is possible to use the differential amplifier and the bias circuit which are used during the first phase. Use of one differential amplifier alone is possible with two bias circuits used. Use of only first and second phases is also possible.

Abstract: In order to improve the degree of storage data integration, side walls (32) are selectively formed on side surfaces of word lines (22) to serve as masks for changing ON-state current values of memory cells by changing widths or lengths of active regions (24) of the memory cells, thereby forming a plurality of types of memory cells having different electrical properties. Thus, storage data per memory cell is so multivalued that the number of memory cells is reduced.

Abstract: The memory cells of a read-only memory are connected in parallel between adjacent bus-bit lines. The selection of tile sub-bit lines is through a selector logic decoder. The decoder has many rows of MOSFETs connected in series. Only one of MOSFETs in a row between an adjacent bit line bus and a virtual ground bus is active and controllable by a sub-word line selection signal with other MOSFETs non-conducting and connected between two adjacent sub-bit lines. These active MOSFETs in different rows are connected in series. One of these active MOSFETs is coupled to a main bit line, and another of these active MOSFETs is coupled to a virtual ground. When the active MOSFET is open, the main bit line signal and the virtual signal appear between the corresponding memory cells between these two corresponding sub-bit lines and are sensed. With this structure, the accessed memory cell is coupled between the main bit line and the virtual ground line through a number of series MOSFETs.

Abstract: A semiconductor memory device in which a plurality of data lines of a memory array comprising storage transistors arranged in a matrix form as those having a high or low threshold voltage according to stored data are divided into a plurality of blocks, and sense amplifiers for performing amplification operations dispersedly in time are used to amplify signals. Moreover, a first and a second group of sense amplifiers corresponding to odd- and even-numbered adjoining data lines are arranged so that while the output signals of one group of sense amplifiers are output, word lines are switched, and the other group of sense amplifiers are caused to perform the operation of amplifying the signals read from the memory cells corresponding to the word lines thus switched, respectively.

Abstract: A current amplification type mask-ROM having a bipolar junction transistor. The current amplification type mask-ROM includes a collector grounding part disposed in each of the plurality of bipolar junction transistors one by one, and a ground line for connecting the collector grounding part to a cell grounding part formed in one end of a cell array.

Abstract: Method and structure is disclosed for a read-only MOS semiconductor memory. An addressable array of a multiplicity of cells each comprising a single MOS transistor is coded for preselected cells by providing them with source/drain regions which are spaced apart from edges of their respective overlying gate electrode regions. This is accomplished by a masking step late in the fabrication sequence. In this way, a dense MOS memory having rapid manufacturing turn-around is provided.

Abstract: A flash-EEPROM memory array presenting a NOR architecture wherein the memory cells, organized in rows and columns and having drain regions connected to respective bit lines, source regions connected to a common source line, and control gate regions connected to respective word lines, present an asymmetrical structure wherein one of the source and drain regions presents a highly resistive portion to permit programming and erasing of the cells at different regions. The array includes bias transistors arranged in a row and each connected between a respective bit line and the common source line, for maintaining at the same potential the drain and source regions of the cells connected to the nonaddressed bit lines during programming, and so preventing spurious writing.

Abstract: A NAND ROM with an improved integration level is described. A number of trenches are formed in stripe pattern at the surface of a semiconductor substrate, and an insulating film for isolation between devices is formed at the sidewalls, respectively, of each trench. A first unit array consisting of MOSFETs connected in series is arranged in each first active region defined between two adjacent trenches. A second active region is defined in the bottom of each trench and a second unit array is arranged therein. Distinguished from the trench isolation technique which provides trenches between unit arrays, instead, according to the present invention, sidewalls of insulating film are formed. The trench width is limited to the minimum feature size involving the lithography. On the other hand, the width of the insulating-film sidewalls are independent of the limitation, permitting the size of the 64-Mbit mask ROM chip to be about 2 mm smaller.

Abstract: In a semiconductor memory comprising one main bit line D1, a pair of main ground lines VG1 and VD2, a plurality of memory cell banks to be selectively connected to the main bit line D1 and the main ground lines VG1 and VD2, and a plurality of word lines W1 to Wn extending through the memory cell banks, each of the memory cell banks includes a plurality of wirings L1, L2, L3, L4 and L5 located in parallel to each other, and a threshold of a block selection transistor BT11 connected between the main bit line D1 and the wiring L3, is lower than that of block selection transistors BT12 and BT13 connected between the main bit line D1 and the wiring L2 and between the main bit line D1 and the wiring L4, respectively.

Abstract: A clamp circuit for a read-only-memory (ROM) device provides clamp voltages which can uniformly compensate for the parasitic capacitance on ROM word lines and improve the performance of the ROM device. The clamp circuit includes an active load, a plurality of amplifiers and a transmission gate. The amplifiers have various trip voltages and are controlled by different decoding signals for providing various clamp voltages to different word lines in the ROM device. Each amplifier is composed of a NOR gate and a transistor. The amplifier trip voltages can be easily set to desired values when designing NOR gate layout patterns without additional complicated processes being introduced into the fabrication methodology of a semiconductor integrated circuit.

Abstract: A flat-cell ROM array includes a bank of field effect transistors, each having a source, drain and gate, formed by ion implantation between columns of buried N+ and under rows of polysilicon, wherein adjacent columns of buried N+ are the source and drain of at least one transistor and a corresponding row of polysilicon is the gate of the transistor. Each of these transistors is programmed to have one of a plurality of threshold voltages depending on a desired storage value. Attached to the bank of transistors is an upper selector network associated with the bank connected to a first class of alternating sets of the columns, and a lower selector network associated with the bank connected to a second class of alternating sets of the columns. A method provides steps for performing the present invention.

Abstract: A system and method for the storage of digital information wherein data that would normally be represented by multiple bits of information is effectively stored at single memory site within a ROM. This is accomplished by employing a multiple bit-line memory architecture, in conjunction with a data decoder. With this arrangement it is possible to store, at a single memory site, information that would have required up to .left brkt-top.log.sub.2 (n(n-1)/2)+1).right brkt-top. individual memory sites in a conventional ROM (where n is the number independent of bit-lines connected to an individual memory element in the invention). The invention is particularly well-suited to what would be considered relatively low-speed data retrieval systems, such as those adapted to provide audio and/or video to a user on a real time basis.

Abstract: A multi-level NAND architecture non-volatile memory device reads and programs memory cells, each cell storing more than one bit of data, by comparing to a constant current level while selectively adjusting the gate voltage on the cell or cells being read or programmed. A plurality of read and write reference cells are provided each programmed to correspond to one each of the multi-level programming wherein during reading of the memory cells, the read reference cells provide the constant current level and during writing to the memory cells, the write reference cells provide the same. Furthermore, during a read operation, corresponding write reference cells are coupled to read reference cells to gauge the reading time associated with reading of memory cells.

Abstract: A method for programming a memory cell is disclosed. The state of the memory cell is determined by the presence or absence of a spacer short. A memory cell has a floating gate, a control gate and an insulating layer separating the floating gate and the control gate. Spacers are deposited on the sides of the control gate and the insulating layer. When the cell is selected to be programmed in the "off" or non-conductive state, the spacers are in contact only with the control gate and the insulating layer. When the cell is selected to be programmed in the "on" or conductive state, the spacers are in contact with the control gate, the insulating layer, and the floating gate, thereby creating a spacer short.

Abstract: In a four-valued read only storage device, each of memory cells arrayed in matrix form at intersections of word lines and bit lines has four metal oxide semiconductor (MOS) transistors. The four MOS transistors have different combinations of two channel impurity profiles and two effective channel lengths in correspondence with storage data. Either data corresponding to the channel impurity profile or data corresponding to the effective channel length is read out from a memory cell by controlling a gate voltage and a drain voltage to be applied to a selected MOS transistor in the memory cell.

Abstract: A charge pump (10) uses Schottky diodes (12) coupled to clock signals (.phi..sub.1 and .phi..sub.2) via respective capacitors (14a-d). Regulation and control circuitry 18 provides a stable voltage output and controls the clock circuitry (16).

Abstract: An alternate metal ground (AMG) read only memory (ROM) includes an array of ROM data storage cells that are divided into segments. Each segment includes a plurality (typically 2.sup.x, e.g. 32 or 64) of word lines, a pair of segment select transistors for minimizing bit line capacitance when reading, and a pair of inner select transistors on each part of a segment to insure the connection between the connected diffusion but line and the intermediate non-connected diffusion bit line. That is, diffusion bit lines N-1, and N+1 are connected to metal bit lines via the segment select transistors. The diffusion bit lines between bit lines N-1, N and N+1 are not connected to metal bit lines. These non-connected intermediate bit lines are connected to ground via the inner or outer select transistors.

Abstract: A read-only-memory having a plurality of very narrow, closely spaced gate electrodes spanning the distance between source and drain regions. The gate electrodes consist of first and second alternating polycrystalline silicon lines having vertical sidewalls. The first lines have tapered sidewall spacers. The second lines are entirely contained between the first lines without overlap of the first lines.

Abstract: A memory cell (400) for storing data on an integrated circuit. The memory cell (400) is static, nonvolatile, and reprogrammable. The layout of the memory cell is compact. In a first state, a logic high output from this memory cell (400) is at about VDD; and in a second state, a logic low output is about VSS. The memory cell (400) of the present invention includes a first programmable memory element (515) and a second programmable memory element (520). First programmable memory element (515) is coupled between VDD (505) and a sensing node (405). Second programmable memory element (520) is coupled between the sensing node (405) and VSS (510). In the first state, first programmable memory element (515) is not programmed, while the second programmable memory element (520) is programmed. In the second state, first programmable memory element (515) is programmed, while second programmable memory element (520) is not programmed.

Abstract: A ROM array with coding after metallization comprises a plurality of first bit lines, a plurality of second bit lines, a plurality of third bit lines, a plurality of word lines, a plurality of first control lines, a plurality of second control lines and a plurality of selecting lines. Memory cells of the ROM array are formed by the intersection of the word lines and the first and second bit lines, wherein the word lines are polysilicon gates and the bit lines are drain/source diffusion regions. The third bit lines are metal lines above the first bit lines. The third bit lines are not wide enough to cover spacings between the first and second bit lines, thus exposing spaces for code implantation. The first and second control lines intersect the first and second bit lines to form a number of switches for controlling data reading paths to The memory cells. The positions and ON/OFF states of the switches are designed to provide at least two data reading paths to each memory cell.

Abstract: A write-once read-many memory system (10) for electronically securing a select portion of memory from being overwritten or erased. Memory system (10) includes one or more storage cells (25) for providing electronic storage of information. A control cell (13) is used for controlling writing and/or erasing access to the storage cells (25). Control logic (11) is provided to control access to the control cell (13). Control cell (13) and control logic (11) are used as a gate to provide selective access to storage cells (25) through write control line (19) and erase control line (21). Storage cells (25) can only be accessed when the control cell (13) in an appropriate logic state.

Abstract: A programmable semiconductor integrated circuit constructed as a Field Programmable Gate Array (FPGA) comprises basic cells each comprised of; a first stable circuit having first and second nodes and operative to respectively output, in the steady state, power supply potential and ground potential from the first and second nodes; a second stable circuit having third and fourth nodes and operative to respectively output, in the steady state, ground potential and power supply potential from the third and fourth nodes; and a control circuit for selectively connecting any one of a node pair comprised of the first and second nodes of the first stable circuit and a node pair comprised of the third and fourth nodes of the second stable circuit, or the both node pairs to first and second bit lines.

Abstract: An erasable programmable read-only memory with NAND cell structure is disclosed which has memory cells provided on a N type substrate. The memory cells are divided into NAND cell blocks each of which has a series array of memory cell transistors. Each of the transistors has a floating gate, a control gate connected to a word line and N type diffusion layers serving as its source and drain. These semiconductor layers are formed in a P type well layer formed in a surface area of a substrate. The well layer serves as a surface breakdown prevention layer. During a data erase mode data stored in all the memory cells are erased simultaneously. During the data write mode subsequent to the erase mode, when a certain NAND cell block is selected, memory cells in the NAND cell block are subjected to data writing in sequence.