Abstract: A process and structure are disclosed for a programmable array for use in a read-only memory comprising diode elements and shorted diode elements. The elements are connected across bit and wordlines. The invention utilizes lateral polysilicon diodes and metal silicide layer bridging the junction of pre-selected diodes to short pre-selected diode elements. Programming is accomplished by either forming the silicide layer across the junctions of pre-selected diodes or removing the silicide layer from the junctions of pre-selected diodes.

Abstract: A read-only data storage and retrieval device is presented having no moving parts and requiring very low power. Addressing can be accomplished sequentially where the address increments automatically or can be accomplished randomly. High density storage is achieved through the use of a highly symmetric diode matrix that is addressed in both coordinate directions; its symmetry makes the Dual-addressed Rectifier Storage (DRS) Array very scaleable, particularly when made as an integrated circuit. For even greater storage flexibility, multiple digital rectifier storage arrays can be incorporated into the device, one or more of which can be made removable and interchangeable.

Abstract: A semiconductor or memory device has a decoder circuit for decoding a plurality of external address signals. The external address signals include first and second external address signals. A first address buffer receives the first external address signals and outputs first internal address signals to first address lines. A second address buffer receives the second external address signals and outputs second internal address signals to second address lines. First predecoders have input terminals connected to the first address lines, and output first predecode signals to first predecode lines. Second predecoders have input terminals connected to the second address lines and output second predecode signals to second predecode lines. Main decoders have input terminals connected to the first predecode lines and the second predecode lines and output decode signals. The number of the first external address signals are greater than the number of the second external address signals.

Abstract: A process and structure are disclosed for a programmable array for use in a read-only memory comprising diode elements and shorted diode elements. The elements are connected across bit and wordlines. The invention utilizes lateral polysilicon diodes and metal silicide layer bridging the junction of pre-selected diodes to short pre-selected diode elements. Programming is accomplished by either forming the silicide layer across the junctions of pre-selected diodes or removing the silicide layer from the junctions of pre-selected diodes.

Abstract: A read-only memory cell capable of being programmed by the application of radiant energy. The memory cell includes a trimmable resistor, a diode and a latch. In one embodiment, the cathode of the diode is in electrical communication with a first terminal of the resistor and the anode of the diode is in electrical communication with the second terminal of the resistor. The latch has an input terminal in electrical communication with the second terminal of the resistor and an output terminal. The latch is in a first state when the trimmable resistor is untrimmed and is in a second state when the trimmable resistor is trimmed. In one embodiment, the trimmable resistor is trimmable by laser energy. The invention also relates to a method of storing data in a memory cell.

Abstract: The invention concerns a multi-valued read-only storage location which is constructed symmetrically for storing a first or second state (M, M"') and asymmetrically for storing at least a third state (M', M"). The advantage thereof is above all that the storage capacity is doubled without notably increasing expenditure and without impairing the signal-to-noise ratio with respect to conventional storage locations. The invention is suitable for electrically programmable and mask-programmable read-only memories, in particular for those used in low voltage technology.

Abstract: A memory array using structure changing memory elements in a reverse biased diode array is disclosed. A memory cell is programmed and read by reverse biasing the diode to overcome the diode's breakdown voltage. The disclosed reversed biased diode array exhibits much less substrate current leakage than a similar forward biased diode array.

Abstract: A board includes a plurality of integrated circuits operating at a first supply potential to be supplied. The board has a potential adaptation configuration with an output potential being the first supply potential and an input potential being a second supply potential to be supplied to the board.

Abstract: In accordance with the teachings of the present invention, a programmable integrated transducer amplifier circuit is provided which receives differential outputs from a transducer, such as a pressure or accelerometer transducer. The programmable integrated transducer amplifier circuit includes binary adjustable circuits that are programmed in response to binary coded signals. The binary adjustable circuits generate binary weighted currents that are employed to adjust the operating characteristics of the amplifier circuit. The binary coded signals are received from a programmable memory array which includes a plurality of memory cells that store binary information. Each of the memory cells are programmed when coupled to a programming signal. Additionally, the memory array has pretest capability for testing outputs of the memory cells prior to permanently programming the respective memory cells.

Abstract: A diode type read only memory (ROM) includes a diode as a memory cell. The diode is a logic level "on" memory cell and coupled to one of the word lines and one of the bit lines of the ROM. A relative high voltage is given to the bit line coupled to the diode and a relative low voltage is given to the corresponding word line. Therefore, the data saved in the diode can be read out.

Abstract: An extremely compact dynamic memory cell (200) includes a capacitor (204) or any other suitable stored charge device, and a diode (208) such as a Zener diode, a pair of parallel, reverse-connected diodes, or any other suitable voltage dropping device having substantially definite voltage drops when conducting in each direction. The capacitor and Zener diode are connected in series between a Row Select line (202) and a Column Bit line (210). These structures are suitable for fabrication by any of a variety of processes used to fabricate conventional semiconductor DRAMs. The memory cell is replicated millions of times and arrayed in rows and columns as in conventional one-transistor MOSFET DRAM memories to form a memory integrated circuit. Rows of cells are accessed by asserting the corresponding Row Select line, and columns are accessed by asserting the Column Bit line.

Abstract: A read-only data storage and retrieval device is presented having no moving parts and requiring very low power. Addressing can be accomplished sequentially where the address increments automatically or can be accomplished randomly. High density storage is achieved through the use of a highly symmetric diode matrix that is addressed in both coordinate directions; its symmetry makes the Dual-addressed Rectifier Storage (DRS) Array very scaleable, particularly when made as an integrated circuit. For even greater storage flexibility, multiple digital rectifier storage arrays can be incorporated into the device, one or more of which can be made removable and interchangeable.

Abstract: The present invention teaches a memory comprising an array of memory cells. Each cell of the array in the memory comprises a bus, and a diode, preferably a zener diode, having a substantially low breakdown voltage. Further, each cell comprises a programmable element, preferably an antifuse, for selectively coupling the diode with the bus.

Abstract: A high density multistate SRAM cell including N negative differential resistance diodes connected in series and to a load. The diodes and the load defining a memory node having N+1 stable states. A write transistor having a drain connected to the memory node and adapted to receive N+1 different amplitudes of voltage on the source, and a write signal on the gate. An amplifier having an input terminal connected to the memory node, and a read switch having an input terminal connected to the output terminal of the amplifier. A plurality of cells connected into a matrix with N+1 sense amplifiers associated with each column of the matrix so as to provide an output for each of the N+1 different amplitudes.

Abstract: An integrated memory device can be used as a Content Addressable Memory (CAM) or as a Random Addressable Memory (RAM) for applications in data compression, video compression or Autosophy robots. Memory addressing employs long chains of Field Effect Transistors, forming a logical AND function, and programmable non volatile connection cells which can be implemented either as programmable fuses or memory transistors including PROM, EPROM, EEPROM or FLUSH technologies. Each connection cell is programmable for either connection or non connection. Each chain of Field Effect Transistors may generate any arbitrary output address code which is programmed via diodes and the same non volatile connection cells used to decode the input data words. The device combines extreme low power consumption with very fast search access speed. Devices implemented as flexible thin foils can be folded into very large, compact and robust memory arrays.

Abstract: A "zener-zap" memory cell with pretest capability for testing effects that would be realized from permanently programming the memory cell is provided. The memory cell is addressable and provides a binary signal at an output. The memory cell uses a zener diode as a memory element which is permanently programmed when selectively coupled to a programming voltage which exceeds the reverse breakdown voltage of the zener diode. The memory cell has a test circuit for generating the programmed binary signal at the output of the memory cell prior to permanently programming the zener diode and when coupled to a pretest voltage.

Abstract: To protect the thin tunnel oxide layer interposed between the floating gate region of memory cells and the substrate and which are subject to in-process damage, when the wafer is subjected to radiation, provision is made for a diode, connected between the control gate region of the cells and the substrate. The diode defines a conductive path that, when normal operating voltage is applied to the control gate regions, is turned off and has no effect on normal operation of the memory, and which is turned on to permit the passage of charges between the control gate region and the substrate, when the control gate potential exceeds normal operating potential but is less than the breakdown voltage of the tunnel oxide divided by the coupling factor of the control and floating gate regions of the cells. The diode is appropriately formed prior to patterning the control gate regions of the cells.

Abstract: A memory is formed from an array of switchless integrated circuit memory cells in a high-density configuration. These cells comprise a capacitor and two diodes in a configuration where one diode is used to charge one pole of the capacitor, and the other diode is used to discharge it from that same pole, over separate paired lines used respectively for charging and discharging, as well as reading. The other pole of the capacitor is tied to a single line used for both charging and discharging, and in support of reading. Drive and sense circuitry located at the periphery of the cell array is used to perform interconnect switching functions while writing or reading charges on cells in the array. Alternative high-density switched cell variations are also described. The cell arrays are fabricated on monolithic integrated circuits which are interconnected with one another by using a method which deposits and etches conductive material which links conductive traces between the monolithic dice.

Abstract: A semiconductor device includes a number of programmable elements arranged in a matrix of rows and columns. The elements each have a doped semiconductor region (10) and a conductor region (20) which are mutually separated by an insulating layer (8). The conductor region (20) can be a material suitable for forming a rectifying junction (35) with the material of the semiconductor region (10). Within a row, the conductor regions of the programmable elements present therein are coupled to a common row conductor (21 . . . 23), and within a column the semiconductor regions of the programmable elements situated therein are connected to a common column conductor (11 . . . 14). To program an element, a programming voltage V.sub.

Abstract: An electronic matrix array device such as a data store, e.g. a datacard, or an electro-optic active matrix display, has crossing sets of row and column conductors and matrix elements such as memory or picture cells at the crossing intersections. At least some of the matrix elements include a two-terminal thin film non-linear impedance element which may be bi-directional, such as a MIM, or unidirectional, such as a diode. The array device also includes a row address decoder for addressing the row conductors and a column address decoder for addressing the column conductors, either or both decoders having respective stages for respective conductors of the relevant set of conductors.

Abstract: A non-volatile memory cell including a pn diode and a circuit for sensing the logic state of the pn diode such that a logic one state indicates that the diode is in its normal state, while the other logic state is created by fusing the diode for creating a short circuit. The circuit for sensing the logic state of the diode includes a circuit for developing a sense voltage across the diode, a first comparator for comparing the sense voltage with a first reference voltage greater than the normal junction voltage, a second comparator for comparing the sense voltage with a second reference voltage less than the normal junction voltage but greater than the fused junction voltage and a circuit responsive to the outputs of the first and second comparators to provide an output signal which has a first value if the sense voltage is between the first and second reference voltages and a second value if the sense voltage is not between the first and second reference voltages.

Abstract: The present invention teaches a memory comprising an array of memory cells. Each cell of the array in the memory comprises a bus, and a diode, preferably a zener diode, having a substantially low breakdown voltage. Further, each cell comprises a programmable element, preferably an antifuse, for selectively coupling the diode with the bus.

Abstract: An optical memory which allows for the high-speed random access of two-dimensional information. Portions of a light receiver made from material with photovoltaic or photoconductive effect are connected to corresponding portions of a ferroelectric liquid crystal panel through an amplifier layer. To write, a light image is shown on the light receiver. When light striking each portion of the light receiver is sufficiently strong, the state of the corresponding part of the liquid crystal panel is changed. The state of the panel can be read with an image scanner for scanning the liquid crystal panel.

Abstract: The present invention provides a programmable structure for a programmable read-only memory (PROM) which utilizes one-sided ozone spacers constructed on the digit lines as one time programmable nodes. An oxide/nitride/oxide layer (ONO) is used as an interface between underlying parallel rows of digit lines, having one-sided ozone spacers, and overlying parallel columns of word lines in a programmable read only memory With a each digit line passing under each word line in a row/column matrix is formed thereby providing a programmable digit/word line matrix. Each crossing point of the digit and word lines in the matrix will be permanently programmed to either a one or a zero by rupturing the thin ONO dielectric interface by applying the appropriate voltage potential between the associated digit/word line conductors.

Abstract: A thin-film ROM device includes an array of open circuit and closed-circuit cells (5 to 8) formed from a stack of thin films (12,21,22,23,11) on a glass or other substrate (10). The semiconductor films (21,22,23) may be of hydrogenated amorphous silicon. At least one of the semiconductor films (21,22,23) is removed from some of the closed-circuit cell areas (5,7,8) before depositing the next film. In this way, at least a second type of thin-film diode (MIM, MIN, MIP) is formed having a different conduction characteristic to that of a first type (NIP), so increasing the information content of the ROM array. A lower semiconductor film (23) can be readily etched away from the lower electrode film (11) by a selective etching treatment in which the electrode film (11) acts as an etch stop. By monitoring emissions during plasma etching, an upper semiconductor film (21 or 22) can be removed from a lower semiconductor film (22 or 23).

Abstract: A memory cell comprising a memory region of amorphous silicon, such memory region having a first state of substantial electrical nonconductivity programmable to a second state of substantial electrical conductivity in response to an electrical programming signal applied thereto. The memory region is disposed over a metal Schottky contact, such as platinum-silicide (PtSi), formed in a support body. A first barrier layer comprising a refractory metal such as titanium-tungsten (TiW) is disposed between the memory region and Schottky contact. A first input terminal comprising a metal strip conductor, such as aluminum, is disposed over the memory region, with a second refractory metal barrier layer being disposed between the memory region and metal strip conductor. A second input terminal is disposed within the support body.

Abstract: A parallel distributed processor comprises matrices of unit cells arranged in a stacked configuration. Each unit cell includes a chalcogenide body which may be set and reset to a plurality of values of a given physical property. Interconnections between the unit cells are established via the chalcogenide materials and the pattern and strength of the interconnections is determined by the set values of the chalcogenide. The processor is readily adapted to the construction of neural network computing systems.

Abstract: A memory matrix comprises a plurality of word lines, a plurality of bit lines, and a stacked diode and voltage-variable resistor structure interconnecting bit lines to word lines. The stacked diode and voltage-variable resistor structure includes a doped region in a semiconductor substrate defining a work line, a doped polycrystalline silicon layer over said word line and forming a p-n junction therewith, and an amorphized region in the doped polycrystalline silicon layer having increased resistance over the non-amorphized portion of the doped polycrystalline silicon layer. A contact is made to the amorphized polycrystalline silicon material which preferably includes a titanium-tungsten barrier layer and an aluminum layer over the barrier layer.

Abstract: A monolithic integrated circuit memory control operating through the use of MOS field-effect transistors with diode or bipolar circuit arrangement for the bit line column switching.

Abstract: A semiconductor memory circuit includes a plurality of programmable memory cells capable of being programmed by a predetermined current; a plurality of bit lines connected with memory cells, a plurality of current distributors corresponding to the bit lines for connecting selected bit lines to an output terminal based on selection signals and separating non-selected bit lines from the output terminal, and a plurality of switching circuits corresponding to the bit lines for connecting non-selected bit lines to a low level potential point based on the selection signals. The determination of the existence of the inter-cell leakage is carried out precisely and easily.

Abstract: A semiconductor device having a vertical transistor consisting of a semiconductor substrate, a first semiconductor region, and a second semiconductor region operatively functioning as a collector, a base, and an emitter of a transistor. By providing a high concentration region in the first semiconductor region, the base width of the transistor is narrowed. In a PROM, a reverse current preventing transistor with such a narrowed base width in each memory cell can be driven by a decoder/driver with a lowered driving power consumption.

Abstract: A memory device comprises an access circuit for setting a selected one of word lines to a low (or high) level responsive to a row address and for setting a selected one of bit lines to a high (or low) level responsive to a columnm address so as to designate a memory cell within a memory cell array, a comparing circuit driven by a constant current source for reading out information from the designated memory cell via the bit lines by comparing the bit line level with a reference level, an output circuit for outputting the information read out by the comparing circuit, and a control circuit for either setting all of the word lines and bit lines to a high level or setting all of the word lines and bit lines to have a high impedance and setting the impedance at an output of the output circuit to a high impedance when the memory device is disabled, so as to reduce the power consumption when the memory device is disabled.

Abstract: In a junction-shorting type PROM, including transistors, a highly doped region having the same conductivity type as a base is provided between a pair of memory cells. This region is a base contact region which commonly connects paired bases at a surface terminal connected to a word line. The base contact region also extends into the substrate, which is a collector, and prevents minority carries in each of the paired bases from diffusing into an adjacent base, and thus, prevents influence between the paired memory cells. The base contact region may be isolated from emitter regions by a narrow groove filled with insulation material. The narrow groove is deeper than the emitter regions but shallower than the substrate. A memory cell block composed of the paired cells and the base contact region is isolated at its circumference by the narrow groove.

Abstract: With an audiovisual information presentation system, pictorial image data, drawn on paper sheets in advance and to be optically projected on a screen using an optical projector, is sequentially sensed by a TV camea. Speech corresponding to the image data is input through a microphone. A data storage unit stores the image data and corresponding audio data together with code data for identifying pairs of image and audio data. When a search mode is designated, a desired pair of image and audio data is automatically searched from the data storage unit under the control of a CPU, and is reproduced by electrical monitor display units and a loudspeaker unit independent of image display on the projection screen.

Abstract: The problem of the distributed voltage drop along a resistive word line through which fusible elements of a circuit array are selectively programmed to a state of high resistance (effective open circuit) is circumvented by incorporated an auxiliary word line driver as part of the array. The auxiliary word line driver is coupled to the word line at a location apart from the main word line driver, so as to reduce the effective resistance and consequential voltage drop along the word line. As a result, for each memory cell along a respective word line there is sufficient "rupturing current" capability, whereby each fusible element of the memory array may be successfully programmed regardless of its physical location within the array.

Abstract: A semiconductor PROM contains a group of PROM cells (12) each consisting of a pair of opposing diodes oriented vertically with their common intermediate region (22 and 24) fully adjoining a recessed oxide insulating region (16). The PN junction (30) of the upper diode of each pair lies in non-monocrystalline semiconductor material. A composite buried layer consisting of buried regions (32) which adjoin the insulating region below the lower cell regions (20) and a buried web (44) which laterally surrounds each buried region is employed to improve programming efficiency as well as provide intermediate electrical connections.

Abstract: Current switches are used to control current into the columns during READ operations of a PROM. The circuit provides one such switch for each of the columns of the PROM and makes possible the use of a single current source which is connected to each of the switches but supplies current only to the column of the PROM that is currently selected for reading. A high voltage pre-bias is applied to the collectors of the NPN transistors used as current switches such that turn-on speed is improved because the collector parasitic capacitances are pre-charged to near the supply potential.

Abstract: A programmable read-only memory device of a junction destruction type is provided with a test circuit for the purpose of detecting a parasitic thyristor effect which may occur in the data programming operation by the user. The test circuit includes first and second additional row lines, a first diode connected between the first additional row line and one column line, a second diode connected between the second additional row line and another column line adjacent to the one column line, and a transistor of a base-open type connected between the second additional row line and the one column line.

Abstract: An I.sup.2 L programmable read only memory (PROM) row driver circuit sinks current from a row of memory elements when selectively activated. The circuit operates in the read mode at very low power levels and down to 1.0 volt. The circuit has two current sinking capabilities, a low current capability for the read mode and a high current capability for the program mode. Switching between modes is accomplished merely by changing the voltage on a power supply terminal; 1-3 volts for the read mode and 9-12 volts for program.

Abstract: A programmable logic array chip is provided with an auxiliary grid pattern of conductive paths. Connecting elements can be selectively activated to connect certain ones of the auxiliary paths to the normal grid pattern paths which are connected to functional elements. In such manner, it is possible to provide a logic array chip that has increased flexibility in terms of user programmable functions.

Abstract: An apparatus for displaying in real-time a previously recorded video sequence includes a main memory wherein digitized video gray-scale information is stored for selected non-interlaced fields of video images to be displayed. The memory unit is formed of interconnected substrates. Each substrate is a ROM which includes storage elements and a layer of amorphous silicon alloy which forms an array of diode isolation elements. Column select and read-out circuitry as well as row select circuitry for each of the substrates are formed, on each corresponding substrate, utilizing the same amorphous silicon alloy. Digitized fields of presorted information are read out and stored in pairs in an interpolator circuit which is used to form interlaced fields to be displayed timewise between the digitally stored fields. The digitized fields are converted by a digital-to-analog converter and added to sync signals to form a composite analog video signal adapted to drive a raster scan display unit.

Abstract: An I.sup.2 L programmable read only memory (PROM) output circuit has a selectable dual non-inverting input differential amplifier with each non-inverting input connected to a different column of memory elements. In the read mode the circuit operates at very low power levels and down to 1 volt. To program the memory elements, the circuit includes two selectable programming current sources which self extinguish as soon as the memory element being programmed changes from its unprogrammed to its programmed state. Switching between the read and program modes is accomplished merely by changing the voltage on the B+ terminal; 1-3 volts for read and 9-12 volts for program.

Abstract: An integrated Schottky logic (ISL) read only memory (ROM) uses ISL drivers and decoders connected to wordlines and data bitlines. The pattern of data stored in the ISL is determined by Schottky diodes which are connected between selected data bitlines and wordlines. Improved performance is achieved by using a leakage current compensation source (such as a wordline pullup resistor) connected to each wordline, and by using a programmable dummy load (such as one or more dummy bitlines). The pullup resistors compensate for bitline loading sensitivity caused by leakage currents of the workline drivers. The dummy bitlines are selectively connected to those wordlines which are lightly loaded to compensate for wordline loading sensitivity and thus equalize access time and improve wordline decoder noise margins.

Abstract: In a method of electrically altering the characteristics of a semiconductor device, a lateral polysilicon zener diode's zener knee voltage may be shifted either to a higher or lower voltage. An electrical potential may be applied in the forward direction to shift the zener knee to a higher voltage level. An electrical potential may be applied in the reverse bias direction to shift the zener knee to a lower voltage. In the limit, the zener may be changed into a forward diode of reverse polarity with respect to the original zener. The electrical potential used should be of appropriate magnitude to melt the polysilicon without damage to the zener's terminals. This induces migration of the impurities causing a rediffusion of impurities thereby altering the characteristics of the diode. This method may be used to program a PROM by either converting the zener to a diode or not to program each binary bit.

Abstract: A solid state semiconductor device is disclosed which is programmable so as to alter the impedance between its two terminals. In many embodiments, the device is programmable to have any one of four conditions: a first in which the electrical impedance is relatively high in both directions; a second in which the impedance is relatively high in one direction and relatively low in the opposite direction; a third in which the impedance is relatively high in the opposite direction and relatively low in the first direction; and a fourth in which the impedance is relatively low in both directions. Such a programmable device can be made with semiconductor layers which form two series coupled back-to-back diodes, each of which can be selectively programmed to lose its rectifying feature. Structures are disclosed which include a plurality of such programmable devices in one or more separately programmable planes, each with its own addressing means.

Abstract: An electronic device is provided which includes first and second memory arrays, each capable of storing data at locations therein, and an address decoder positioned between the first and second memory arrays for decoding address signals input thereto and corresponding to the locations. The address decoder is advantageously configured as a set of ISL gates or MESFET logic gates. It is further advantageous to form the memory arrays of Schottky diodes which, when employed with the ISL configuration for an address decoder, utilizes the same Schottky diode in the memory arrays as are utilized in the ISL gates. A further refinement provides a precharged circuit for each bit line.

Abstract: A reduced-area, read-only memory, including a programmable read-only memory, accomplished with a first step of removing one word address line from the word decoder input and one bit address line from the bit decoder input. The number of decoder output lines is thus cut in half. Adjacent line-driving transistors are driven by the same decoder output line. The removed word decoder input, and its complement, drive auxiliary bit lines; the removed bit decoder input and its complement drive auxiliary word lines. Circuitry connected at crossovers of word lines with auxiliary bit lines and bit lines with auxiliary word lines selectively suppress the selection of one line of each pair of lines that is driven by a single decoder output. The invention is particularly effective when utilized with Schottky diodes insulated from the semiconductor substrate. In the memory cells the Schottky diodes can be connected in series with voltage-programmable resistors to provide a reduced-area, programmable, read-only memory.

Abstract: In fabricating a PROM cell, an electrical isolation mechanism (44 and 32) is formed in a semiconductive body to separate islands of an upper zone (36) of first type conductivity (N) in the body. A semiconductor is introduced into one of the islands to produce a region (48) of opposite type conductivity (P) that forms a PN junction with adjacent semiconductive material of the island. Ions are implanted to convert a surface layer (60) of the region into a highly resistive amorphous form which is irreversibly switchable to a low resistance state. A path of first type conductivity extending from the PN junction through another of the islands to its upper surface is created in the body to complete the basic cell.

Abstract: In fabricating a PROM cell, an electrical isolation mechanism (44 and 32) is formed in a semiconductive body to separate islands of an upper zone (36) of first type conductivity (N) in the body. A semiconductor impurity is introduced into one of the islands to produce a region (48) of opposite type conductivity (P) that forms a PN junction laterally bounded by the island's side boundaries. A highly resistive amorphous semiconductive layer (58) which is irreversibly switchable to a low resistive state is deposited above the region in such a manner as to be electrically coupled to the region. A path of first type conductivity extending from the PN junction through another of the islands to its upper surface is created in the body to complete the basic cell.

Abstract: The semiconductor device relates to a shorted junction type programmable read only memory semiconductor device. The memory consists of a semiconductor region including a PN junction or a Schottky junction and a control electrode coupled to the junction. The junction is destroyed or shorted by causing a field or carrier injection effect in the semiconductor region with a voltage impressed on the control electrode.